projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
generic: rtl8366: cleanup MIB counter printing
[openwrt/openwrt.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0509
45 #define RTL8366S_CHIP_ID_8366 0x5937
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0430
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0431
66 #define RTL8366_LED_0_1_CTRL_REG 0x0432
67 #define RTL8366_LED_2_3_CTRL_REG 0x0433
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x13F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
124
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_5 | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_5)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
146
147 struct rtl8366rb {
148 struct device *parent;
149 struct rtl8366_smi smi;
150 struct switch_dev dev;
151 char buf[4096];
152 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
153 struct dentry *debugfs_root;
154 #endif
155 };
156
157 struct rtl8366rb_vlan_mc {
158 u16 reserved2:1;
159 u16 priority:3;
160 u16 vid:12;
161 u16 untag:8;
162 u16 member:8;
163 u16 stag_mbr:8;
164 u16 stag_idx:3;
165 u16 reserved1:2;
166 u16 fid:3;
167 };
168
169 struct rtl8366rb_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172 u16 untag:8;
173 u16 member:8;
174 u16 reserved2:13;
175 u16 fid:3;
176 };
177
178 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
179 u16 gl_dbg_reg;
180 #endif
181
182 struct mib_counter {
183 unsigned offset;
184 unsigned length;
185 const char *name;
186 };
187
188 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
189 { 0, 4, "IfInOctets" },
190 { 4, 4, "EtherStatsOctets" },
191 { 8, 2, "EtherStatsUnderSizePkts" },
192 { 10, 2, "EtherFragments" },
193 { 12, 2, "EtherStatsPkts64Octets" },
194 { 14, 2, "EtherStatsPkts65to127Octets" },
195 { 16, 2, "EtherStatsPkts128to255Octets" },
196 { 18, 2, "EtherStatsPkts256to511Octets" },
197 { 20, 2, "EtherStatsPkts512to1023Octets" },
198 { 22, 2, "EtherStatsPkts1024to1518Octets" },
199 { 24, 2, "EtherOversizeStats" },
200 { 26, 2, "EtherStatsJabbers" },
201 { 28, 2, "IfInUcastPkts" },
202 { 30, 2, "EtherStatsMulticastPkts" },
203 { 32, 2, "EtherStatsBroadcastPkts" },
204 { 34, 2, "EtherStatsDropEvents" },
205 { 36, 2, "Dot3StatsFCSErrors" },
206 { 38, 2, "Dot3StatsSymbolErrors" },
207 { 40, 2, "Dot3InPauseFrames" },
208 { 42, 2, "Dot3ControlInUnknownOpcodes" },
209 { 44, 4, "IfOutOctets" },
210 { 48, 2, "Dot3StatsSingleCollisionFrames" },
211 { 50, 2, "Dot3StatMultipleCollisionFrames" },
212 { 52, 2, "Dot3sDeferredTransmissions" },
213 { 54, 2, "Dot3StatsLateCollisions" },
214 { 56, 2, "EtherStatsCollisions" },
215 { 58, 2, "Dot3StatsExcessiveCollisions" },
216 { 60, 2, "Dot3OutPauseFrames" },
217 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
218 { 64, 2, "Dot1dTpPortInDiscards" },
219 { 66, 2, "IfOutUcastPkts" },
220 { 68, 2, "IfOutMulticastPkts" },
221 { 70, 2, "IfOutBroadcastPkts" },
222 };
223
224 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
225 {
226 return container_of(smi, struct rtl8366rb, smi);
227 }
228
229 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
230 {
231 return container_of(sw, struct rtl8366rb, dev);
232 }
233
234 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
235 {
236 struct rtl8366rb *rtl = sw_to_rtl8366rb(sw);
237 return &rtl->smi;
238 }
239
240 static int rtl8366rb_reset_chip(struct rtl8366_smi *smi)
241 {
242 int timeout = 10;
243 u32 data;
244
245 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
246 RTL8366_CHIP_CTRL_RESET_HW);
247 do {
248 msleep(1);
249 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
250 return -EIO;
251
252 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
253 break;
254 } while (--timeout);
255
256 if (!timeout) {
257 printk("Timeout waiting for the switch to reset\n");
258 return -EIO;
259 }
260
261 return 0;
262 }
263
264 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
265 u32 phy_no, u32 page, u32 addr, u32 *data)
266 {
267 u32 reg;
268 int ret;
269
270 if (phy_no > RTL8366S_PHY_NO_MAX)
271 return -EINVAL;
272
273 if (page > RTL8366S_PHY_PAGE_MAX)
274 return -EINVAL;
275
276 if (addr > RTL8366S_PHY_ADDR_MAX)
277 return -EINVAL;
278
279 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
280 RTL8366S_PHY_CTRL_READ);
281 if (ret)
282 return ret;
283
284 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
285 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
286 (addr & RTL8366S_PHY_REG_MASK);
287
288 ret = rtl8366_smi_write_reg(smi, reg, 0);
289 if (ret)
290 return ret;
291
292 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
293 if (ret)
294 return ret;
295
296 return 0;
297 }
298
299 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
300 u32 phy_no, u32 page, u32 addr, u32 data)
301 {
302 u32 reg;
303 int ret;
304
305 if (phy_no > RTL8366S_PHY_NO_MAX)
306 return -EINVAL;
307
308 if (page > RTL8366S_PHY_PAGE_MAX)
309 return -EINVAL;
310
311 if (addr > RTL8366S_PHY_ADDR_MAX)
312 return -EINVAL;
313
314 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
315 RTL8366S_PHY_CTRL_WRITE);
316 if (ret)
317 return ret;
318
319 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
320 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
321 (addr & RTL8366S_PHY_REG_MASK);
322
323 ret = rtl8366_smi_write_reg(smi, reg, data);
324 if (ret)
325 return ret;
326
327 return 0;
328 }
329
330 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
331 int port, unsigned long long *val)
332 {
333 int i;
334 int err;
335 u32 addr, data;
336 u64 mibvalue;
337
338 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
339 return -EINVAL;
340
341 addr = RTL8366S_MIB_COUNTER_BASE +
342 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
343 rtl8366rb_mib_counters[counter].offset;
344
345 /*
346 * Writing access counter address first
347 * then ASIC will prepare 64bits counter wait for being retrived
348 */
349 data = 0; /* writing data will be discard by ASIC */
350 err = rtl8366_smi_write_reg(smi, addr, data);
351 if (err)
352 return err;
353
354 /* read MIB control register */
355 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
356 if (err)
357 return err;
358
359 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
360 return -EBUSY;
361
362 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
363 return -EIO;
364
365 mibvalue = 0;
366 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
367 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
368 if (err)
369 return err;
370
371 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
372 }
373
374 *val = mibvalue;
375 return 0;
376 }
377
378 static int rtl8366rb_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
379 struct rtl8366_vlan_4k *vlan4k)
380 {
381 struct rtl8366rb_vlan_4k vlan4k_priv;
382 int err;
383 u32 data;
384 u16 *tableaddr;
385
386 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
387 vlan4k_priv.vid = vid;
388
389 if (vid >= RTL8366_NUM_VIDS)
390 return -EINVAL;
391
392 tableaddr = (u16 *)&vlan4k_priv;
393
394 /* write VID */
395 data = *tableaddr;
396 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
397 if (err)
398 return err;
399
400 /* write table access control word */
401 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
402 RTL8366S_TABLE_VLAN_READ_CTRL);
403 if (err)
404 return err;
405
406 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
407 if (err)
408 return err;
409
410 *tableaddr = data;
411 tableaddr++;
412
413 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
414 &data);
415 if (err)
416 return err;
417
418 *tableaddr = data;
419 tableaddr++;
420
421 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
422 &data);
423 if (err)
424 return err;
425 *tableaddr = data;
426
427 vlan4k->vid = vid;
428 vlan4k->untag = vlan4k_priv.untag;
429 vlan4k->member = vlan4k_priv.member;
430 vlan4k->fid = vlan4k_priv.fid;
431
432 return 0;
433 }
434
435 static int rtl8366rb_set_vlan_4k(struct rtl8366_smi *smi,
436 const struct rtl8366_vlan_4k *vlan4k)
437 {
438 struct rtl8366rb_vlan_4k vlan4k_priv;
439 int err;
440 u32 data;
441 u16 *tableaddr;
442
443 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
444 vlan4k->member > RTL8366_PORT_ALL ||
445 vlan4k->untag > RTL8366_PORT_ALL ||
446 vlan4k->fid > RTL8366S_FIDMAX)
447 return -EINVAL;
448
449 vlan4k_priv.vid = vlan4k->vid;
450 vlan4k_priv.untag = vlan4k->untag;
451 vlan4k_priv.member = vlan4k->member;
452 vlan4k_priv.fid = vlan4k->fid;
453
454 tableaddr = (u16 *)&vlan4k_priv;
455
456 data = *tableaddr;
457
458 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
459 if (err)
460 return err;
461
462 tableaddr++;
463
464 data = *tableaddr;
465
466 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
467 data);
468 if (err)
469 return err;
470
471 tableaddr++;
472
473 data = *tableaddr;
474
475 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
476 data);
477 if (err)
478 return err;
479
480 /* write table access control word */
481 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
482 RTL8366S_TABLE_VLAN_WRITE_CTRL);
483
484 return err;
485 }
486
487 static int rtl8366rb_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
488 struct rtl8366_vlan_mc *vlanmc)
489 {
490 struct rtl8366rb_vlan_mc vlanmc_priv;
491 int err;
492 u32 addr;
493 u32 data;
494 u16 *tableaddr;
495
496 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
497
498 if (index >= RTL8366_NUM_VLANS)
499 return -EINVAL;
500
501 tableaddr = (u16 *)&vlanmc_priv;
502
503 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
504 err = rtl8366_smi_read_reg(smi, addr, &data);
505 if (err)
506 return err;
507
508 *tableaddr = data;
509 tableaddr++;
510
511 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
512 err = rtl8366_smi_read_reg(smi, addr, &data);
513 if (err)
514 return err;
515
516 *tableaddr = data;
517 tableaddr++;
518
519 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
520 err = rtl8366_smi_read_reg(smi, addr, &data);
521 if (err)
522 return err;
523
524 *tableaddr = data;
525
526 vlanmc->vid = vlanmc_priv.vid;
527 vlanmc->priority = vlanmc_priv.priority;
528 vlanmc->untag = vlanmc_priv.untag;
529 vlanmc->member = vlanmc_priv.member;
530 vlanmc->fid = vlanmc_priv.fid;
531
532 return 0;
533 }
534
535 static int rtl8366rb_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
536 const struct rtl8366_vlan_mc *vlanmc)
537 {
538 struct rtl8366rb_vlan_mc vlanmc_priv;
539 int err;
540 u32 addr;
541 u32 data;
542 u16 *tableaddr;
543
544 if (index >= RTL8366_NUM_VLANS ||
545 vlanmc->vid >= RTL8366_NUM_VIDS ||
546 vlanmc->priority > RTL8366S_PRIORITYMAX ||
547 vlanmc->member > RTL8366_PORT_ALL ||
548 vlanmc->untag > RTL8366_PORT_ALL ||
549 vlanmc->fid > RTL8366S_FIDMAX)
550 return -EINVAL;
551
552 vlanmc_priv.vid = vlanmc->vid;
553 vlanmc_priv.priority = vlanmc->priority;
554 vlanmc_priv.untag = vlanmc->untag;
555 vlanmc_priv.member = vlanmc->member;
556 vlanmc_priv.stag_mbr = 0;
557 vlanmc_priv.stag_idx = 0;
558 vlanmc_priv.fid = vlanmc->fid;
559
560 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
561
562 tableaddr = (u16 *)&vlanmc_priv;
563 data = *tableaddr;
564
565 err = rtl8366_smi_write_reg(smi, addr, data);
566 if (err)
567 return err;
568
569 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
570
571 tableaddr++;
572 data = *tableaddr;
573
574 err = rtl8366_smi_write_reg(smi, addr, data);
575 if (err)
576 return err;
577
578 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
579
580 tableaddr++;
581 data = *tableaddr;
582
583 err = rtl8366_smi_write_reg(smi, addr, data);
584 if (err)
585 return err;
586 return 0;
587 }
588
589 static int rtl8366rb_get_port_vlan_index(struct rtl8366_smi *smi, int port,
590 int *val)
591 {
592 u32 data;
593 int err;
594
595 if (port >= RTL8366_NUM_PORTS)
596 return -EINVAL;
597
598 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
599 &data);
600 if (err)
601 return err;
602
603 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
604 RTL8366S_PORT_VLAN_CTRL_MASK;
605
606 return 0;
607
608 }
609
610 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
611 int *val)
612 {
613 struct rtl8366_vlan_mc vlanmc;
614 int err;
615 int index;
616
617 err = rtl8366rb_get_port_vlan_index(smi, port, &index);
618 if (err)
619 return err;
620
621 err = rtl8366rb_get_vlan_mc(smi, index, &vlanmc);
622 if (err)
623 return err;
624
625 *val = vlanmc.vid;
626 return 0;
627 }
628
629 static int rtl8366rb_set_port_vlan_index(struct rtl8366_smi *smi, int port,
630 int index)
631 {
632 u32 data;
633 int err;
634
635 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
636 return -EINVAL;
637
638 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
639 &data);
640 if (err)
641 return err;
642
643 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
644 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
645 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
646 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
647
648 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
649 data);
650 return err;
651 }
652
653 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366_smi *smi, int port,
654 int val)
655 {
656 int i;
657 struct rtl8366_vlan_mc vlanmc;
658 struct rtl8366_vlan_4k vlan4k;
659
660 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
661 return -EINVAL;
662
663 /* Updating the 4K entry; lookup it and change the port member set */
664 rtl8366rb_get_vlan_4k(smi, val, &vlan4k);
665 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
666 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
667 rtl8366rb_set_vlan_4k(smi, &vlan4k);
668
669 /*
670 * For the 16 entries more work needs to be done. First see if such
671 * VID is already there and change it
672 */
673 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
674 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
675
676 /* Try to find an existing vid and update port member set */
677 if (val == vlanmc.vid) {
678 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
679 rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
680
681 /* Now update PVID register settings */
682 rtl8366rb_set_port_vlan_index(smi, port, i);
683
684 return 0;
685 }
686 }
687
688 /*
689 * PVID could not be found from vlan table. Replace unused (one that
690 * has no member ports) with new one
691 */
692 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
693 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
694
695 /*
696 * See if this vlan member configuration is unused. It is
697 * unused if member set contains no ports or CPU port only
698 */
699 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
700 vlanmc.vid = val;
701 vlanmc.priority = 0;
702 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
703 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
704 vlanmc.fid = 0;
705
706 rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
707
708 /* Now update PVID register settings */
709 rtl8366rb_set_port_vlan_index(smi, port, i);
710
711 return 0;
712 }
713 }
714
715 dev_err(smi->parent,
716 "All 16 vlan member configurations are in use\n");
717
718 return -EINVAL;
719 }
720
721
722 static int rtl8366rb_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
723 {
724 u32 data = 0;
725
726 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
727
728 if (enable)
729 data |= RTL8366_CHIP_CTRL_VLAN;
730 else
731 data &= ~RTL8366_CHIP_CTRL_VLAN;
732
733 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
734 }
735
736 static int rtl8366rb_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
737 {
738 u32 data = 0;
739
740 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
741
742 if (enable)
743 data |= RTL8366_CHIP_CTRL_VLAN_4KTB;
744 else
745 data &= ~RTL8366_CHIP_CTRL_VLAN_4KTB;
746
747 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
748 }
749
750 static int rtl8366rb_reset_vlan(struct rtl8366_smi *smi)
751 {
752 struct rtl8366_vlan_4k vlan4k;
753 struct rtl8366_vlan_mc vlanmc;
754 int err;
755 int i;
756
757 /* clear 16 VLAN member configuration */
758 vlanmc.vid = 0;
759 vlanmc.priority = 0;
760 vlanmc.member = 0;
761 vlanmc.untag = 0;
762 vlanmc.fid = 0;
763 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
764 err = rtl8366rb_set_vlan_mc(smi, i, &vlanmc);
765 if (err)
766 return err;
767 }
768
769 /* Set a default VLAN with vid 1 to 4K table for all ports */
770 vlan4k.vid = 1;
771 vlan4k.member = RTL8366_PORT_ALL;
772 vlan4k.untag = RTL8366_PORT_ALL;
773 vlan4k.fid = 0;
774 err = rtl8366rb_set_vlan_4k(smi, &vlan4k);
775 if (err)
776 return err;
777
778 /* Set all ports PVID to default VLAN */
779 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
780 err = rtl8366rb_set_vlan_port_pvid(smi, i, 0);
781 if (err)
782 return err;
783 }
784
785 return 0;
786 }
787
788 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
789 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
790 {
791 file->private_data = inode->i_private;
792 return 0;
793 }
794
795 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
796 char __user *user_buf,
797 size_t count, loff_t *ppos)
798 {
799 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
800 struct rtl8366_smi *smi = &rtl->smi;
801 int i, j, len = 0;
802 char *buf = rtl->buf;
803
804 len += snprintf(buf + len, sizeof(rtl->buf) - len,
805 "%-36s %12s %12s %12s %12s %12s %12s\n",
806 "Counter",
807 "Port 0", "Port 1", "Port 2",
808 "Port 3", "Port 4", "Port 5");
809
810 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
811 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
812 rtl8366rb_mib_counters[i].name);
813 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
814 unsigned long long counter = 0;
815
816 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
817 len += snprintf(buf + len,
818 sizeof(rtl->buf) - len,
819 "%12llu ", counter);
820 else
821 len += snprintf(buf + len,
822 sizeof(rtl->buf) - len,
823 "%12s ", "error");
824 }
825 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
826 }
827
828 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
829 }
830
831 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
832 char __user *user_buf,
833 size_t count, loff_t *ppos)
834 {
835 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
836 struct rtl8366_smi *smi = &rtl->smi;
837 int i, j, len = 0;
838 char *buf = rtl->buf;
839
840 len += snprintf(buf + len, sizeof(rtl->buf) - len,
841 "VLAN Member Config:\n");
842 len += snprintf(buf + len, sizeof(rtl->buf) - len,
843 "\t id \t vid \t prio \t member \t untag \t fid "
844 "\tports\n");
845
846 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
847 struct rtl8366_vlan_mc vlanmc;
848
849 rtl8366rb_get_vlan_mc(smi, i, &vlanmc);
850
851 len += snprintf(buf + len, sizeof(rtl->buf) - len,
852 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
853 "\t", i, vlanmc.vid, vlanmc.priority,
854 vlanmc.member, vlanmc.untag, vlanmc.fid);
855
856 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
857 int index = 0;
858 if (!rtl8366rb_get_port_vlan_index(smi, j, &index)) {
859 if (index == i)
860 len += snprintf(buf + len,
861 sizeof(rtl->buf) - len,
862 "%d", j);
863 }
864 }
865 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
866 }
867
868 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
869 }
870
871 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
872 char __user *user_buf,
873 size_t count, loff_t *ppos)
874 {
875 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
876 struct rtl8366_smi *smi = &rtl->smi;
877 u32 t, reg = gl_dbg_reg;
878 int err, len = 0;
879 char *buf = rtl->buf;
880
881 memset(buf, '\0', sizeof(rtl->buf));
882
883 err = rtl8366_smi_read_reg(smi, reg, &t);
884 if (err) {
885 len += snprintf(buf, sizeof(rtl->buf),
886 "Read failed (reg: 0x%04x)\n", reg);
887 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
888 }
889
890 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
891 reg, t);
892
893 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
894 }
895
896 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
897 const char __user *user_buf,
898 size_t count, loff_t *ppos)
899 {
900 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
901 struct rtl8366_smi *smi = &rtl->smi;
902 unsigned long data;
903 u32 reg = gl_dbg_reg;
904 int err;
905 size_t len;
906 char *buf = rtl->buf;
907
908 len = min(count, sizeof(rtl->buf) - 1);
909 if (copy_from_user(buf, user_buf, len)) {
910 dev_err(rtl->parent, "copy from user failed\n");
911 return -EFAULT;
912 }
913
914 buf[len] = '\0';
915 if (len > 0 && buf[len - 1] == '\n')
916 buf[len - 1] = '\0';
917
918
919 if (strict_strtoul(buf, 16, &data)) {
920 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
921 } else {
922 err = rtl8366_smi_write_reg(smi, reg, data);
923 if (err) {
924 dev_err(rtl->parent,
925 "writing reg 0x%04x val 0x%04lx failed\n",
926 reg, data);
927 }
928 }
929
930 return count;
931 }
932
933 static const struct file_operations fops_rtl8366rb_regs = {
934 .read = rtl8366rb_read_debugfs_reg,
935 .write = rtl8366rb_write_debugfs_reg,
936 .open = rtl8366rb_debugfs_open,
937 .owner = THIS_MODULE
938 };
939
940 static const struct file_operations fops_rtl8366rb_vlan = {
941 .read = rtl8366rb_read_debugfs_vlan,
942 .open = rtl8366rb_debugfs_open,
943 .owner = THIS_MODULE
944 };
945
946 static const struct file_operations fops_rtl8366rb_mibs = {
947 .read = rtl8366rb_read_debugfs_mibs,
948 .open = rtl8366rb_debugfs_open,
949 .owner = THIS_MODULE
950 };
951
952 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
953 {
954 struct dentry *node;
955 struct dentry *root;
956
957 if (!rtl->debugfs_root)
958 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
959
960 if (!rtl->debugfs_root) {
961 dev_err(rtl->parent, "Unable to create debugfs dir\n");
962 return;
963 }
964 root = rtl->debugfs_root;
965
966 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
967 if (!node) {
968 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
969 "reg");
970 return;
971 }
972
973 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
974 &fops_rtl8366rb_regs);
975 if (!node) {
976 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
977 "val");
978 return;
979 }
980
981 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
982 &fops_rtl8366rb_vlan);
983 if (!node) {
984 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
985 "vlan");
986 return;
987 }
988
989 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
990 &fops_rtl8366rb_mibs);
991 if (!node) {
992 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
993 "mibs");
994 return;
995 }
996 }
997
998 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
999 {
1000 if (rtl->debugfs_root) {
1001 debugfs_remove_recursive(rtl->debugfs_root);
1002 rtl->debugfs_root = NULL;
1003 }
1004 }
1005
1006 #else
1007 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
1008 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
1009 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1010
1011 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
1012 const struct switch_attr *attr,
1013 struct switch_val *val)
1014 {
1015 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1016 u32 data = 0;
1017
1018 if (val->value.i == 1) {
1019 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1020 data |= (1 << 2);
1021 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1022 }
1023
1024 return 0;
1025 }
1026
1027 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1028 const struct switch_attr *attr,
1029 struct switch_val *val)
1030 {
1031 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1032 u32 data;
1033
1034 if (attr->ofs == 1) {
1035 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1036
1037 if (data & RTL8366_CHIP_CTRL_VLAN)
1038 val->value.i = 1;
1039 else
1040 val->value.i = 0;
1041 } else if (attr->ofs == 2) {
1042 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1043
1044 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1045 val->value.i = 1;
1046 else
1047 val->value.i = 0;
1048 }
1049
1050 return 0;
1051 }
1052
1053 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1054 const struct switch_attr *attr,
1055 struct switch_val *val)
1056 {
1057 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1058 u32 data;
1059
1060 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1061
1062 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1063
1064 return 0;
1065 }
1066
1067 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1068 const struct switch_attr *attr,
1069 struct switch_val *val)
1070 {
1071 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1072 u32 data;
1073
1074 if (val->value.i >= 6)
1075 return -EINVAL;
1076
1077 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1078
1079 data &= ~RTL8366_LED_BLINKRATE_MASK;
1080 data |= val->value.i;
1081
1082 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1083
1084 return 0;
1085 }
1086
1087 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1088 const struct switch_attr *attr,
1089 struct switch_val *val)
1090 {
1091 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1092
1093 if (attr->ofs == 1)
1094 return rtl8366rb_vlan_set_vlan(smi, val->value.i);
1095 else
1096 return rtl8366rb_vlan_set_4ktable(smi, val->value.i);
1097 }
1098
1099 static const char *rtl8366rb_speed_str(unsigned speed)
1100 {
1101 switch (speed) {
1102 case 0:
1103 return "10baseT";
1104 case 1:
1105 return "100baseT";
1106 case 2:
1107 return "1000baseT";
1108 }
1109
1110 return "unknown";
1111 }
1112
1113 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1114 const struct switch_attr *attr,
1115 struct switch_val *val)
1116 {
1117 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1118 struct rtl8366_smi *smi = &rtl->smi;
1119 u32 len = 0, data = 0;
1120
1121 if (val->port_vlan >= RTL8366_NUM_PORTS)
1122 return -EINVAL;
1123
1124 memset(rtl->buf, '\0', sizeof(rtl->buf));
1125 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1126 (val->port_vlan / 2), &data);
1127
1128 if (val->port_vlan % 2)
1129 data = data >> 8;
1130
1131 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1132 len = snprintf(rtl->buf, sizeof(rtl->buf),
1133 "port:%d link:up speed:%s %s-duplex %s%s%s",
1134 val->port_vlan,
1135 rtl8366rb_speed_str(data &
1136 RTL8366S_PORT_STATUS_SPEED_MASK),
1137 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1138 "full" : "half",
1139 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1140 "tx-pause ": "",
1141 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1142 "rx-pause " : "",
1143 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1144 "nway ": "");
1145 } else {
1146 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1147 val->port_vlan);
1148 }
1149
1150 val->value.s = rtl->buf;
1151 val->len = len;
1152
1153 return 0;
1154 }
1155
1156 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1157 const struct switch_attr *attr,
1158 struct switch_val *val)
1159 {
1160 int i;
1161 u32 len = 0;
1162 struct rtl8366_vlan_mc vlanmc;
1163 struct rtl8366_vlan_4k vlan4k;
1164 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1165 struct rtl8366_smi *smi = &rtl->smi;
1166 char *buf = rtl->buf;
1167
1168 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1169 return -EINVAL;
1170
1171 memset(buf, '\0', sizeof(rtl->buf));
1172
1173 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1174 rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1175
1176 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1177 val->port_vlan);
1178
1179 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1180 int index = 0;
1181 if (!rtl8366rb_get_port_vlan_index(smi, i, &index) &&
1182 index == val->port_vlan)
1183 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1184 "%d", i);
1185 }
1186 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1187
1188 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1189 "\t\t vid \t prio \t member \t untag \t fid\n");
1190 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1191 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1192 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1193 vlanmc.vid, vlanmc.priority, vlanmc.member,
1194 vlanmc.untag, vlanmc.fid);
1195 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1196 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1197 "%d \t \t 0x%04x \t 0x%04x \t %d",
1198 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1199
1200 val->value.s = buf;
1201 val->len = len;
1202
1203 return 0;
1204 }
1205
1206 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1207 const struct switch_attr *attr,
1208 struct switch_val *val)
1209 {
1210 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1211 u32 data = 0;
1212
1213 if (val->port_vlan >= RTL8366_NUM_PORTS)
1214 return -EINVAL;
1215
1216 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1217 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1218 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1219 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1220 } else {
1221 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1222 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1223 (val->value.i << (val->port_vlan * 4));
1224 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1225 }
1226
1227 return 0;
1228 }
1229
1230 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1231 const struct switch_attr *attr,
1232 struct switch_val *val)
1233 {
1234 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1235 u32 data = 0;
1236
1237 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1238 return -EINVAL;
1239
1240 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1241 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1242
1243 return 0;
1244 }
1245
1246 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1247 const struct switch_attr *attr,
1248 struct switch_val *val)
1249 {
1250 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1251 u32 data = 0;
1252
1253 if (val->port_vlan >= RTL8366_NUM_PORTS)
1254 return -EINVAL;
1255
1256 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1257 data |= (1 << (val->port_vlan + 3));
1258 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1259
1260 return 0;
1261 }
1262
1263 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1264 const struct switch_attr *attr,
1265 struct switch_val *val)
1266 {
1267 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1268 struct rtl8366_smi *smi = &rtl->smi;
1269 int i, len = 0;
1270 unsigned long long counter = 0;
1271 char *buf = rtl->buf;
1272
1273 if (val->port_vlan >= RTL8366_NUM_PORTS)
1274 return -EINVAL;
1275
1276 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1277 "Port %d MIB counters\n",
1278 val->port_vlan);
1279
1280 for (i = 0; i < ARRAY_SIZE(rtl8366rb_mib_counters); ++i) {
1281 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1282 "%-36s: ", rtl8366rb_mib_counters[i].name);
1283 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1284 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1285 "%llu\n", counter);
1286 else
1287 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1288 "%s\n", "error");
1289 }
1290
1291 val->value.s = buf;
1292 val->len = len;
1293 return 0;
1294 }
1295
1296 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1297 struct switch_val *val)
1298 {
1299 struct rtl8366_vlan_mc vlanmc;
1300 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1301 struct switch_port *port;
1302 int i;
1303
1304 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1305 return -EINVAL;
1306
1307 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1308
1309 port = &val->value.ports[0];
1310 val->len = 0;
1311 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1312 if (!(vlanmc.member & BIT(i)))
1313 continue;
1314
1315 port->id = i;
1316 port->flags = (vlanmc.untag & BIT(i)) ?
1317 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1318 val->len++;
1319 port++;
1320 }
1321 return 0;
1322 }
1323
1324 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1325 struct switch_val *val)
1326 {
1327 struct rtl8366_vlan_mc vlanmc;
1328 struct rtl8366_vlan_4k vlan4k;
1329 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1330 struct switch_port *port;
1331 int i;
1332
1333 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1334 return -EINVAL;
1335
1336 rtl8366rb_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1337 rtl8366rb_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1338
1339 vlanmc.untag = 0;
1340 vlanmc.member = 0;
1341
1342 port = &val->value.ports[0];
1343 for (i = 0; i < val->len; i++, port++) {
1344 vlanmc.member |= BIT(port->id);
1345
1346 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1347 vlanmc.untag |= BIT(port->id);
1348 }
1349
1350 vlan4k.member = vlanmc.member;
1351 vlan4k.untag = vlanmc.untag;
1352
1353 rtl8366rb_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1354 rtl8366rb_set_vlan_4k(smi, &vlan4k);
1355 return 0;
1356 }
1357
1358 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1359 {
1360 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1361 return rtl8366rb_get_vlan_port_pvid(smi, port, val);
1362 }
1363
1364 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1365 {
1366 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1367 return rtl8366rb_set_vlan_port_pvid(smi, port, val);
1368 }
1369
1370 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1371 {
1372 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1373 int err;
1374
1375 err = rtl8366rb_reset_chip(smi);
1376 if (err)
1377 return err;
1378
1379 return rtl8366rb_reset_vlan(smi);
1380 }
1381
1382 static struct switch_attr rtl8366rb_globals[] = {
1383 {
1384 .type = SWITCH_TYPE_INT,
1385 .name = "enable_vlan",
1386 .description = "Enable VLAN mode",
1387 .set = rtl8366rb_sw_set_vlan_enable,
1388 .get = rtl8366rb_sw_get_vlan_enable,
1389 .max = 1,
1390 .ofs = 1
1391 }, {
1392 .type = SWITCH_TYPE_INT,
1393 .name = "enable_vlan4k",
1394 .description = "Enable VLAN 4K mode",
1395 .set = rtl8366rb_sw_set_vlan_enable,
1396 .get = rtl8366rb_sw_get_vlan_enable,
1397 .max = 1,
1398 .ofs = 2
1399 }, {
1400 .type = SWITCH_TYPE_INT,
1401 .name = "reset_mibs",
1402 .description = "Reset all MIB counters",
1403 .set = rtl8366rb_sw_reset_mibs,
1404 .get = NULL,
1405 .max = 1
1406 }, {
1407 .type = SWITCH_TYPE_INT,
1408 .name = "blinkrate",
1409 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1410 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1411 .set = rtl8366rb_sw_set_blinkrate,
1412 .get = rtl8366rb_sw_get_blinkrate,
1413 .max = 5
1414 },
1415 };
1416
1417 static struct switch_attr rtl8366rb_port[] = {
1418 {
1419 .type = SWITCH_TYPE_STRING,
1420 .name = "link",
1421 .description = "Get port link information",
1422 .max = 1,
1423 .set = NULL,
1424 .get = rtl8366rb_sw_get_port_link,
1425 }, {
1426 .type = SWITCH_TYPE_INT,
1427 .name = "reset_mib",
1428 .description = "Reset single port MIB counters",
1429 .max = 1,
1430 .set = rtl8366rb_sw_reset_port_mibs,
1431 .get = NULL,
1432 }, {
1433 .type = SWITCH_TYPE_STRING,
1434 .name = "mib",
1435 .description = "Get MIB counters for port",
1436 .max = 33,
1437 .set = NULL,
1438 .get = rtl8366rb_sw_get_port_mib,
1439 }, {
1440 .type = SWITCH_TYPE_INT,
1441 .name = "led",
1442 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1443 .max = 15,
1444 .set = rtl8366rb_sw_set_port_led,
1445 .get = rtl8366rb_sw_get_port_led,
1446 },
1447 };
1448
1449 static struct switch_attr rtl8366rb_vlan[] = {
1450 {
1451 .type = SWITCH_TYPE_STRING,
1452 .name = "info",
1453 .description = "Get vlan information",
1454 .max = 1,
1455 .set = NULL,
1456 .get = rtl8366rb_sw_get_vlan_info,
1457 },
1458 };
1459
1460 /* template */
1461 static struct switch_dev rtl8366_switch_dev = {
1462 .name = "RTL8366S",
1463 .cpu_port = RTL8366_PORT_NUM_CPU,
1464 .ports = RTL8366_NUM_PORTS,
1465 .vlans = RTL8366_NUM_VLANS,
1466 .attr_global = {
1467 .attr = rtl8366rb_globals,
1468 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1469 },
1470 .attr_port = {
1471 .attr = rtl8366rb_port,
1472 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1473 },
1474 .attr_vlan = {
1475 .attr = rtl8366rb_vlan,
1476 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1477 },
1478
1479 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1480 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1481 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1482 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1483 .reset_switch = rtl8366rb_sw_reset_switch,
1484 };
1485
1486 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1487 {
1488 struct switch_dev *dev = &rtl->dev;
1489 int err;
1490
1491 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1492 dev->priv = rtl;
1493 dev->devname = dev_name(rtl->parent);
1494
1495 err = register_switch(dev, NULL);
1496 if (err)
1497 dev_err(rtl->parent, "switch registration failed\n");
1498
1499 return err;
1500 }
1501
1502 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1503 {
1504 unregister_switch(&rtl->dev);
1505 }
1506
1507 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1508 {
1509 struct rtl8366_smi *smi = bus->priv;
1510 u32 val = 0;
1511 int err;
1512
1513 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1514 if (err)
1515 return 0xffff;
1516
1517 return val;
1518 }
1519
1520 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1521 {
1522 struct rtl8366_smi *smi = bus->priv;
1523 u32 t;
1524 int err;
1525
1526 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1527 /* flush write */
1528 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1529
1530 return err;
1531 }
1532
1533 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1534 {
1535 return (bus->read == rtl8366rb_mii_read &&
1536 bus->write == rtl8366rb_mii_write);
1537 }
1538
1539 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1540 {
1541 struct rtl8366_smi *smi = &rtl->smi;
1542 int ret;
1543
1544 ret = rtl8366rb_reset_chip(smi);
1545 if (ret)
1546 return ret;
1547
1548 rtl8366rb_debugfs_init(rtl);
1549 return 0;
1550 }
1551
1552 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1553 {
1554 u32 chip_id = 0;
1555 u32 chip_ver = 0;
1556 int ret;
1557
1558 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1559 if (ret) {
1560 dev_err(smi->parent, "unable to read chip id\n");
1561 return ret;
1562 }
1563
1564 switch (chip_id) {
1565 case RTL8366S_CHIP_ID_8366:
1566 break;
1567 default:
1568 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1569 return -ENODEV;
1570 }
1571
1572 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1573 &chip_ver);
1574 if (ret) {
1575 dev_err(smi->parent, "unable to read chip version\n");
1576 return ret;
1577 }
1578
1579 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1580 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1581
1582 return 0;
1583 }
1584
1585 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1586 .detect = rtl8366rb_detect,
1587 .mii_read = rtl8366rb_mii_read,
1588 .mii_write = rtl8366rb_mii_write,
1589 };
1590
1591 static int __init rtl8366rb_probe(struct platform_device *pdev)
1592 {
1593 static int rtl8366_smi_version_printed;
1594 struct rtl8366rb_platform_data *pdata;
1595 struct rtl8366rb *rtl;
1596 struct rtl8366_smi *smi;
1597 int err;
1598
1599 if (!rtl8366_smi_version_printed++)
1600 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1601 " version " RTL8366S_DRIVER_VER"\n");
1602
1603 pdata = pdev->dev.platform_data;
1604 if (!pdata) {
1605 dev_err(&pdev->dev, "no platform data specified\n");
1606 err = -EINVAL;
1607 goto err_out;
1608 }
1609
1610 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1611 if (!rtl) {
1612 dev_err(&pdev->dev, "no memory for private data\n");
1613 err = -ENOMEM;
1614 goto err_out;
1615 }
1616
1617 rtl->parent = &pdev->dev;
1618
1619 smi = &rtl->smi;
1620 smi->parent = &pdev->dev;
1621 smi->gpio_sda = pdata->gpio_sda;
1622 smi->gpio_sck = pdata->gpio_sck;
1623 smi->ops = &rtl8366rb_smi_ops;
1624
1625 err = rtl8366_smi_init(smi);
1626 if (err)
1627 goto err_free_rtl;
1628
1629 platform_set_drvdata(pdev, rtl);
1630
1631 err = rtl8366rb_setup(rtl);
1632 if (err)
1633 goto err_clear_drvdata;
1634
1635 err = rtl8366rb_switch_init(rtl);
1636 if (err)
1637 goto err_clear_drvdata;
1638
1639 return 0;
1640
1641 err_clear_drvdata:
1642 platform_set_drvdata(pdev, NULL);
1643 rtl8366_smi_cleanup(smi);
1644 err_free_rtl:
1645 kfree(rtl);
1646 err_out:
1647 return err;
1648 }
1649
1650 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1651 {
1652 if (!rtl8366rb_mii_bus_match(phydev->bus))
1653 return -EINVAL;
1654
1655 return 0;
1656 }
1657
1658 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1659 {
1660 return 0;
1661 }
1662
1663 static struct phy_driver rtl8366rb_phy_driver = {
1664 .phy_id = 0x001cc960,
1665 .name = "Realtek RTL8366RB",
1666 .phy_id_mask = 0x1ffffff0,
1667 .features = PHY_GBIT_FEATURES,
1668 .config_aneg = rtl8366rb_phy_config_aneg,
1669 .config_init = rtl8366rb_phy_config_init,
1670 .read_status = genphy_read_status,
1671 .driver = {
1672 .owner = THIS_MODULE,
1673 },
1674 };
1675
1676 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1677 {
1678 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1679
1680 if (rtl) {
1681 rtl8366rb_switch_cleanup(rtl);
1682 rtl8366rb_debugfs_remove(rtl);
1683 platform_set_drvdata(pdev, NULL);
1684 rtl8366_smi_cleanup(&rtl->smi);
1685 kfree(rtl);
1686 }
1687
1688 return 0;
1689 }
1690
1691 static struct platform_driver rtl8366rb_driver = {
1692 .driver = {
1693 .name = RTL8366RB_DRIVER_NAME,
1694 .owner = THIS_MODULE,
1695 },
1696 .probe = rtl8366rb_probe,
1697 .remove = __devexit_p(rtl8366rb_remove),
1698 };
1699
1700 static int __init rtl8366rb_module_init(void)
1701 {
1702 int ret;
1703 ret = platform_driver_register(&rtl8366rb_driver);
1704 if (ret)
1705 return ret;
1706
1707 ret = phy_driver_register(&rtl8366rb_phy_driver);
1708 if (ret)
1709 goto err_platform_unregister;
1710
1711 return 0;
1712
1713 err_platform_unregister:
1714 platform_driver_unregister(&rtl8366rb_driver);
1715 return ret;
1716 }
1717 module_init(rtl8366rb_module_init);
1718
1719 static void __exit rtl8366rb_module_exit(void)
1720 {
1721 phy_driver_unregister(&rtl8366rb_phy_driver);
1722 platform_driver_unregister(&rtl8366rb_driver);
1723 }
1724 module_exit(rtl8366rb_module_exit);
1725
1726 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1727 MODULE_VERSION(RTL8366S_DRIVER_VER);
1728 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1729 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1730 MODULE_LICENSE("GPL v2");
1731 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);
OpenWrt Source Repository