target/linux/ifxmips/files/arch/mips/ifxmips/clock.c

   1 /*
   2  *   This program is free software; you can redistribute it and/or modify
   3  *   it under the terms of the GNU General Public License as published by
   4  *   the Free Software Foundation; either version 2 of the License, or
   5  *   (at your option) any later version.
   6  *
   7  *   This program is distributed in the hope that it will be useful,
   8  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  *   GNU General Public License for more details.
  11  *
  12  *   You should have received a copy of the GNU General Public License
  13  *   along with this program; if not, write to the Free Software
  14  *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
  15  *
  16  *   Copyright (C) 2007 Xu Liang, infineon
  17  *   Copyright (C) 2008 John Crispin <blogic@openwrt.org>
  18  */
  19
  20 #include <linux/kernel.h>
  21 #include <linux/module.h>
  22 #include <linux/version.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/miscdevice.h>
  26 #include <linux/init.h>
  27 #include <linux/uaccess.h>
  28 #include <linux/unistd.h>
  29 #include <asm/irq.h>
  30 #include <asm/div64.h>
  31 #include <linux/errno.h>
  32 #include <asm/ifxmips/ifxmips.h>
  33 #include <asm/mach-ifxmips/cgu.h>
  34
  35 static unsigned int cgu_get_pll0_fdiv(void);
  36 unsigned int ifxmips_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
  37
  38 #define DDR_HZ ifxmips_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
  39
  40 static inline unsigned int get_input_clock(int pll)
  41 {
  42         switch (pll) {
  43         case 0:
  44                 if (ifxmips_r32(IFXMIPS_CGU_PLL0_CFG) & CGU_PLL0_SRC)
  45                         return BASIS_INPUT_CRYSTAL_USB;
  46                 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
  47                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  48                 else
  49                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  50         case 1:
  51                 if (CGU_PLL1_SRC)
  52                         return BASIS_INPUT_CRYSTAL_USB;
  53                 else if (CGU_PLL0_PHASE_DIVIDER_ENABLE)
  54                         return BASIC_INPUT_CLOCK_FREQUENCY_1;
  55                 else
  56                         return BASIC_INPUT_CLOCK_FREQUENCY_2;
  57         case 2:
  58                 switch (CGU_PLL2_SRC) {
  59                 case 0:
  60                         return cgu_get_pll0_fdiv();
  61                 case 1:
  62                         return CGU_PLL2_PHASE_DIVIDER_ENABLE ?
  63                                 BASIC_INPUT_CLOCK_FREQUENCY_1 :
  64                                 BASIC_INPUT_CLOCK_FREQUENCY_2;
  65                 case 2:
  66                         return BASIS_INPUT_CRYSTAL_USB;
  67                 }
  68         default:
  69                 return 0;
  70         }
  71 }
  72
  73 static inline unsigned int cal_dsm(int pll, unsigned int num, unsigned int den)
  74 {
  75         u64 res, clock = get_input_clock(pll);
  76
  77         res = num * clock;
  78         do_div(res, den);
  79         return res;
  80 }
  81
  82 static inline unsigned int mash_dsm(int pll, unsigned int M, unsigned int N,
  83         unsigned int K)
  84 {
  85         unsigned int num = ((N + 1) << 10) + K;
  86         unsigned int den = (M + 1) << 10;
  87
  88         return cal_dsm(pll, num, den);
  89 }
  90
  91 static inline unsigned int ssff_dsm_1(int pll, unsigned int M, unsigned int N,
  92         unsigned int K)
  93 {
  94         unsigned int num = ((N + 1) << 11) + K + 512;
  95         unsigned int den = (M + 1) << 11;
  96
  97         return cal_dsm(pll, num, den);
  98 }
  99
 100 static inline unsigned int ssff_dsm_2(int pll, unsigned int M, unsigned int N,
 101         unsigned int K)
 102 {
 103         unsigned int num = K >= 512 ?
 104                 ((N + 1) << 12) + K - 512 : ((N + 1) << 12) + K + 3584;
 105         unsigned int den = (M + 1) << 12;
 106
 107         return cal_dsm(pll, num, den);
 108 }
 109
 110 static inline unsigned int dsm(int pll, unsigned int M, unsigned int N,
 111         unsigned int K, unsigned int dsmsel, unsigned int phase_div_en)
 112 {
 113         if (!dsmsel)
 114                 return mash_dsm(pll, M, N, K);
 115         else if (!phase_div_en)
 116                 return mash_dsm(pll, M, N, K);
 117         else
 118                 return ssff_dsm_2(pll, M, N, K);
 119 }
 120
 121 static inline unsigned int cgu_get_pll0_fosc(void)
 122 {
 123         if (CGU_PLL0_BYPASS)
 124                 return get_input_clock(0);
 125         else
 126                 return !CGU_PLL0_CFG_FRAC_EN
 127                         ? dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, 0, CGU_PLL0_CFG_DSMSEL,
 128                                 CGU_PLL0_PHASE_DIVIDER_ENABLE)
 129                         : dsm(0, CGU_PLL0_CFG_PLLM, CGU_PLL0_CFG_PLLN, CGU_PLL0_CFG_PLLK,
 130                                 CGU_PLL0_CFG_DSMSEL, CGU_PLL0_PHASE_DIVIDER_ENABLE);
 131 }
 132
 133 static unsigned int cgu_get_pll0_fdiv(void)
 134 {
 135         unsigned int div = CGU_PLL2_CFG_INPUT_DIV + 1;
 136         return (cgu_get_pll0_fosc() + (div >> 1)) / div;
 137 }
 138
 139 unsigned int cgu_get_io_region_clock(void)
 140 {
 141         unsigned int ret = cgu_get_pll0_fosc();
 142         switch (ifxmips_r32(IFXMIPS_CGU_PLL2_CFG) & CGU_SYS_DDR_SEL) {
 143         default:
 144         case 0:
 145                 return (ret + 1) / 2;
 146         case 1:
 147                 return (ret * 2 + 2) / 5;
 148         case 2:
 149                 return (ret + 1) / 3;
 150         case 3:
 151                 return (ret + 2) / 4;
 152         }
 153 }
 154
 155 void cgu_setup_pci_clk(int external_clock)
 156 {
 157         /* set clock to 33Mhz */
 158         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~0xf00000,
 159                 IFXMIPS_CGU_IFCCR);
 160         ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | 0x800000,
 161                 IFXMIPS_CGU_IFCCR);
 162         if (external_clock) {
 163                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) & ~(1 << 16),
 164                         IFXMIPS_CGU_IFCCR);
 165                 ifxmips_w32((1 << 30), IFXMIPS_CGU_PCICR);
 166         } else {
 167                 ifxmips_w32(ifxmips_r32(IFXMIPS_CGU_IFCCR) | (1 << 16),
 168                         IFXMIPS_CGU_IFCCR);
 169                 ifxmips_w32((1 << 31) | (1 << 30), IFXMIPS_CGU_PCICR);
 170         }
 171 }
 172
 173 unsigned int cgu_get_fpi_bus_clock(int fpi)
 174 {
 175         unsigned int ret = cgu_get_io_region_clock();
 176         if ((fpi == 2) && (ifxmips_r32(IFXMIPS_CGU_SYS) & CGU_SYS_FPI_SEL))
 177                 ret >>= 1;
 178         return ret;
 179 }
 180 EXPORT_SYMBOL(cgu_get_fpi_bus_clock);
 181
 182 unsigned int ifxmips_get_cpu_hz(void)
 183 {
 184         unsigned int ddr_clock = DDR_HZ;
 185         switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc) {
 186         case 0:
 187                 return CLOCK_333M;
 188         case 4:
 189                 return ddr_clock;
 190         }
 191         return ddr_clock << 1;
 192 }
 193 EXPORT_SYMBOL(ifxmips_get_cpu_hz);
 194
 195 unsigned int ifxmips_get_fpi_hz(void)
 196 {
 197         unsigned int ddr_clock = DDR_HZ;
 198         if (ifxmips_r32(IFXMIPS_CGU_SYS) & 0x40)
 199                 return ddr_clock >> 1;
 200         return ddr_clock;
 201 }
 202 EXPORT_SYMBOL(ifxmips_get_fpi_hz);