target/linux/imx6/files-3.10/drivers/pci/host/pcie-designware.h

   1 /*
   2  * Synopsys Designware PCIe host controller driver
   3  *
   4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * Author: Jingoo Han <jg1.han@samsung.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 struct pcie_port_info {
  15         u32             cfg0_size;
  16         u32             cfg1_size;
  17         u32             io_size;
  18         u32             mem_size;
  19         phys_addr_t     io_bus_addr;
  20         phys_addr_t     mem_bus_addr;
  21 };
  22
  23 struct pcie_port {
  24         struct device           *dev;
  25         u8                      root_bus_nr;
  26         void __iomem            *dbi_base;
  27         u64                     cfg0_base;
  28         void __iomem            *va_cfg0_base;
  29         u64                     cfg1_base;
  30         void __iomem            *va_cfg1_base;
  31         u64                     io_base;
  32         u64                     mem_base;
  33         spinlock_t              conf_lock;
  34         struct resource         cfg;
  35         struct resource         io;
  36         struct resource         mem;
  37         struct pcie_port_info   config;
  38         int                     irq;
  39         u32                     lanes;
  40         struct pcie_host_ops    *ops;
  41 };
  42
  43 struct pcie_host_ops {
  44         void (*readl_rc)(struct pcie_port *pp,
  45                         void __iomem *dbi_base, u32 *val);
  46         void (*writel_rc)(struct pcie_port *pp,
  47                         u32 val, void __iomem *dbi_base);
  48         int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val);
  49         int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val);
  50         int (*link_up)(struct pcie_port *pp);
  51         void (*host_init)(struct pcie_port *pp);
  52 };
  53
  54 extern unsigned long global_io_offset;
  55
  56 int cfg_read(void __iomem *addr, int where, int size, u32 *val);
  57 int cfg_write(void __iomem *addr, int where, int size, u32 val);
  58 int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
  59 int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
  60 int dw_pcie_link_up(struct pcie_port *pp);
  61 void dw_pcie_setup_rc(struct pcie_port *pp);
  62 int dw_pcie_host_init(struct pcie_port *pp);
  63 int dw_pcie_setup(int nr, struct pci_sys_data *sys);
  64 struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
  65 int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);