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1385661b048618ed2936ff22581e8707e94f22b8
[openwrt/staging/mkresin.git] / target / linux / imx6 / patches-3.10 / 110-gateworks-ventana.patch
1 --- a/arch/arm/boot/dts/Makefile
2 +++ b/arch/arm/boot/dts/Makefile
3 @@ -117,6 +117,15 @@ dtb-$(CONFIG_ARCH_MXC) += \
4 imx6dl-sabresd.dtb \
5 imx6dl-wandboard.dtb \
6 imx6q-arm2.dtb \
7 + imx6q-gw51xx.dtb \
8 + imx6q-gw52xx.dtb \
9 + imx6q-gw53xx.dtb \
10 + imx6q-gw54xx.dtb \
11 + imx6q-gw5400-a.dtb \
12 + imx6dl-gw51xx.dtb \
13 + imx6dl-gw52xx.dtb \
14 + imx6dl-gw53xx.dtb \
15 + imx6dl-gw54xx.dtb \
16 imx6q-sabreauto.dtb \
17 imx6q-sabrelite.dtb \
18 imx6q-sabresd.dtb \
19 --- a/arch/arm/boot/dts/imx6q.dtsi
20 +++ b/arch/arm/boot/dts/imx6q.dtsi
21 @@ -212,6 +212,30 @@
22 MX6Q_PAD_SD4_DAT0__NAND_DQS 0x00b1
23 >;
24 };
25 +
26 + /* No strobe */
27 + pinctrl_gpmi_nand_2: gpmi-nand-2 {
28 + fsl,pins = <
29 + MX6Q_PAD_NANDF_CLE__NAND_CLE 0xb0b1
30 + MX6Q_PAD_NANDF_ALE__NAND_ALE 0xb0b1
31 + MX6Q_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
32 + MX6Q_PAD_NANDF_RB0__NAND_READY_B 0xb000
33 + MX6Q_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
34 + MX6Q_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
35 + MX6Q_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
36 + MX6Q_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
37 + MX6Q_PAD_SD4_CMD__NAND_RE_B 0xb0b1
38 + MX6Q_PAD_SD4_CLK__NAND_WE_B 0xb0b1
39 + MX6Q_PAD_NANDF_D0__NAND_DATA00 0xb0b1
40 + MX6Q_PAD_NANDF_D1__NAND_DATA01 0xb0b1
41 + MX6Q_PAD_NANDF_D2__NAND_DATA02 0xb0b1
42 + MX6Q_PAD_NANDF_D3__NAND_DATA03 0xb0b1
43 + MX6Q_PAD_NANDF_D4__NAND_DATA04 0xb0b1
44 + MX6Q_PAD_NANDF_D5__NAND_DATA05 0xb0b1
45 + MX6Q_PAD_NANDF_D6__NAND_DATA06 0xb0b1
46 + MX6Q_PAD_NANDF_D7__NAND_DATA07 0xb0b1
47 + >;
48 + };
49 };
50
51 i2c1 {
52 @@ -230,6 +254,12 @@
53 MX6Q_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
54 >;
55 };
56 + pinctrl_i2c2_2: i2c2grp-2 {
57 + fsl,pins = <
58 + MX6Q_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
59 + MX6Q_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
60 + >;
61 + };
62 };
63
64 i2c3 {
65 @@ -239,6 +269,12 @@
66 MX6Q_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
67 >;
68 };
69 + pinctrl_i2c3_2: i2c3grp-2 {
70 + fsl,pins = <
71 + MX6Q_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
72 + MX6Q_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
73 + >;
74 + };
75 };
76
77 uart1 {
78 @@ -248,6 +284,12 @@
79 MX6Q_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
80 >;
81 };
82 + pinctrl_uart1_2: uart1grp-2 {
83 + fsl,pins = <
84 + MX6Q_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
85 + MX6Q_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
86 + >;
87 + };
88 };
89
90 uart2 {
91 @@ -257,6 +299,21 @@
92 MX6Q_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
93 >;
94 };
95 + pinctrl_uart2_3: uart2grp-3 {
96 + fsl,pins = <
97 + MX6Q_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
98 + MX6Q_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
99 + >;
100 + };
101 + };
102 +
103 + uart3 {
104 + pinctrl_uart3_3: uart3grp-3 {
105 + fsl,pins = <
106 + MX6Q_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
107 + MX6Q_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
108 + >;
109 + };
110 };
111
112 uart4 {
113 @@ -267,6 +324,15 @@
114 >;
115 };
116 };
117 +
118 + uart5 {
119 + pinctrl_uart5_1: uart5grp-1 {
120 + fsl,pins = <
121 + MX6Q_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
122 + MX6Q_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
123 + >;
124 + };
125 + };
126
127 usbotg {
128 pinctrl_usbotg_1: usbotggrp-1 {
129 --- a/arch/arm/boot/dts/imx6dl.dtsi
130 +++ b/arch/arm/boot/dts/imx6dl.dtsi
131 @@ -37,6 +37,18 @@
132 compatible = "fsl,imx6dl-iomuxc";
133 reg = <0x020e0000 0x4000>;
134
135 + /* shared pinctrl settings */
136 + audmux {
137 + pinctrl_audmux_1: audmux-1 {
138 + fsl,pins = <
139 + MX6DL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
140 + MX6DL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
141 + MX6DL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
142 + MX6DL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
143 + >;
144 + };
145 + };
146 +
147 enet {
148 pinctrl_enet_1: enetgrp-1 {
149 fsl,pins = <
150 @@ -105,6 +117,59 @@
151 };
152 };
153
154 + gpmi-nand {
155 + /* No strobe */
156 + pinctrl_gpmi_nand_2: gpmi-nand-2 {
157 + fsl,pins = <
158 + MX6DL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
159 + MX6DL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
160 + MX6DL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
161 + MX6DL_PAD_NANDF_RB0__NAND_READY_B 0xb000
162 + MX6DL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
163 + MX6DL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
164 + MX6DL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
165 + MX6DL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
166 + MX6DL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
167 + MX6DL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
168 + MX6DL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
169 + MX6DL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
170 + MX6DL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
171 + MX6DL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
172 + MX6DL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
173 + MX6DL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
174 + MX6DL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
175 + MX6DL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
176 + >;
177 + };
178 + };
179 +
180 + i2c1 {
181 + pinctrl_i2c1_1: i2c1grp-1 {
182 + fsl,pins = <
183 + MX6DL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
184 + MX6DL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
185 + >;
186 + };
187 + };
188 +
189 + i2c2 {
190 + pinctrl_i2c2_2: i2c2grp-2 {
191 + fsl,pins = <
192 + MX6DL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
193 + MX6DL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
194 + >;
195 + };
196 + };
197 +
198 + i2c3 {
199 + pinctrl_i2c3_2: i2c3grp-2 {
200 + fsl,pins = <
201 + MX6DL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
202 + MX6DL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
203 + >;
204 + };
205 + };
206 +
207 uart1 {
208 pinctrl_uart1_1: uart1grp-1 {
209 fsl,pins = <
210 @@ -112,6 +177,30 @@
211 MX6DL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
212 >;
213 };
214 + pinctrl_uart1_2: uart1grp-2 {
215 + fsl,pins = <
216 + MX6DL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
217 + MX6DL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
218 + >;
219 + };
220 + };
221 +
222 + uart2 {
223 + pinctrl_uart2_3: uart2grp-3 {
224 + fsl,pins = <
225 + MX6DL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
226 + MX6DL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
227 + >;
228 + };
229 + };
230 +
231 + uart3 {
232 + pinctrl_uart3_3: uart3grp-3 {
233 + fsl,pins = <
234 + MX6DL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
235 + MX6DL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
236 + >;
237 + };
238 };
239
240 uart4 {
241 @@ -123,7 +212,22 @@
242 };
243 };
244
245 + uart5 {
246 + pinctrl_uart5_1: uart5grp-1 {
247 + fsl,pins = <
248 + MX6DL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
249 + MX6DL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
250 + >;
251 + };
252 + };
253 +
254 usbotg {
255 + pinctrl_usbotg_1: usbotggrp-1 {
256 + fsl,pins = <
257 + MX6DL_PAD_GPIO_1__USB_OTG_ID 0x17059
258 + >;
259 + };
260 +
261 pinctrl_usbotg_2: usbotggrp-2 {
262 fsl,pins = <
263 MX6DL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
Staging tree of Mathias Kresin