target/linux/ipq806x/patches/0093-ARM-dts-qcom-Update-msm8660-device-trees.patch

   1 From 355bf7c6410f5b6e37b5c2b28ebe59bb701c42d6 Mon Sep 17 00:00:00 2001
   2 From: Kumar Gala <galak@codeaurora.org>
   3 Date: Wed, 28 May 2014 12:12:40 -0500
   4 Subject: [PATCH 093/182] ARM: dts: qcom: Update msm8660 device trees
   5
   6 * Move SoC peripherals into an SoC container node
   7 * Move serial enabling into board file (qcom-msm8660-surf.dts)
   8 * Cleanup cpu node to match binding spec, enable-method and compatible
   9   should be per cpu, not part of the container
  10 * Add GSBI node and configuration of GSBI controller
  11
  12 Signed-off-by: Kumar Gala <galak@codeaurora.org>
  13 ---
  14  arch/arm/boot/dts/qcom-msm8660-surf.dts |   10 +++
  15  arch/arm/boot/dts/qcom-msm8660.dtsi     |  115 ++++++++++++++++++-------------
  16  2 files changed, 78 insertions(+), 47 deletions(-)
  17
  18 diff --git a/arch/arm/boot/dts/qcom-msm8660-surf.dts b/arch/arm/boot/dts/qcom-msm8660-surf.dts
  19 index 169bad9..45180ad 100644
  20 --- a/arch/arm/boot/dts/qcom-msm8660-surf.dts
  21 +++ b/arch/arm/boot/dts/qcom-msm8660-surf.dts
  22 @@ -3,4 +3,14 @@
  23  / {
  24         model = "Qualcomm MSM8660 SURF";
  25         compatible = "qcom,msm8660-surf", "qcom,msm8660";
  26 +
  27 +       soc {
  28 +               gsbi@19c00000 {
  29 +                       status = "ok";
  30 +                       qcom,mode = <GSBI_PROT_I2C_UART>;
  31 +                       serial@19c40000 {
  32 +                               status = "ok";
  33 +                       };
  34 +               };
  35 +       };
  36  };
  37 diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
  38 index c52a9e9..53837aaa2f 100644
  39 --- a/arch/arm/boot/dts/qcom-msm8660.dtsi
  40 +++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
  41 @@ -3,6 +3,7 @@
  42  /include/ "skeleton.dtsi"
  43
  44  #include <dt-bindings/clock/qcom,gcc-msm8660.h>
  45 +#include <dt-bindings/soc/qcom,gsbi.h>
  46
  47  / {
  48         model = "Qualcomm MSM8660";
  49 @@ -12,16 +13,18 @@
  50         cpus {
  51                 #address-cells = <1>;
  52                 #size-cells = <0>;
  53 -               compatible = "qcom,scorpion";
  54 -               enable-method = "qcom,gcc-msm8660";
  55
  56                 cpu@0 {
  57 +                       compatible = "qcom,scorpion";
  58 +                       enable-method = "qcom,gcc-msm8660";
  59                         device_type = "cpu";
  60                         reg = <0>;
  61                         next-level-cache = <&L2>;
  62                 };
  63
  64                 cpu@1 {
  65 +                       compatible = "qcom,scorpion";
  66 +                       enable-method = "qcom,gcc-msm8660";
  67                         device_type = "cpu";
  68                         reg = <1>;
  69                         next-level-cache = <&L2>;
  70 @@ -33,55 +36,73 @@
  71                 };
  72         };
  73
  74 -       intc: interrupt-controller@2080000 {
  75 -               compatible = "qcom,msm-8660-qgic";
  76 -               interrupt-controller;
  77 -               #interrupt-cells = <3>;
  78 -               reg = < 0x02080000 0x1000 >,
  79 -                     < 0x02081000 0x1000 >;
  80 -       };
  81 +       soc: soc {
  82 +               #address-cells = <1>;
  83 +               #size-cells = <1>;
  84 +               ranges;
  85 +               compatible = "simple-bus";
  86
  87 -       timer@2000000 {
  88 -               compatible = "qcom,scss-timer", "qcom,msm-timer";
  89 -               interrupts = <1 0 0x301>,
  90 -                            <1 1 0x301>,
  91 -                            <1 2 0x301>;
  92 -               reg = <0x02000000 0x100>;
  93 -               clock-frequency = <27000000>,
  94 -                                 <32768>;
  95 -               cpu-offset = <0x40000>;
  96 -       };
  97 +               intc: interrupt-controller@2080000 {
  98 +                       compatible = "qcom,msm-8660-qgic";
  99 +                       interrupt-controller;
 100 +                       #interrupt-cells = <3>;
 101 +                       reg = < 0x02080000 0x1000 >,
 102 +                             < 0x02081000 0x1000 >;
 103 +               };
 104
 105 -       msmgpio: gpio@800000 {
 106 -               compatible = "qcom,msm-gpio";
 107 -               reg = <0x00800000 0x4000>;
 108 -               gpio-controller;
 109 -               #gpio-cells = <2>;
 110 -               ngpio = <173>;
 111 -               interrupts = <0 16 0x4>;
 112 -               interrupt-controller;
 113 -               #interrupt-cells = <2>;
 114 -       };
 115 +               timer@2000000 {
 116 +                       compatible = "qcom,scss-timer", "qcom,msm-timer";
 117 +                       interrupts = <1 0 0x301>,
 118 +                                    <1 1 0x301>,
 119 +                                    <1 2 0x301>;
 120 +                       reg = <0x02000000 0x100>;
 121 +                       clock-frequency = <27000000>,
 122 +                                         <32768>;
 123 +                       cpu-offset = <0x40000>;
 124 +               };
 125
 126 -       gcc: clock-controller@900000 {
 127 -               compatible = "qcom,gcc-msm8660";
 128 -               #clock-cells = <1>;
 129 -               #reset-cells = <1>;
 130 -               reg = <0x900000 0x4000>;
 131 -       };
 132 +               msmgpio: gpio@800000 {
 133 +                       compatible = "qcom,msm-gpio";
 134 +                       reg = <0x00800000 0x4000>;
 135 +                       gpio-controller;
 136 +                       #gpio-cells = <2>;
 137 +                       ngpio = <173>;
 138 +                       interrupts = <0 16 0x4>;
 139 +                       interrupt-controller;
 140 +                       #interrupt-cells = <2>;
 141 +               };
 142
 143 -       serial@19c40000 {
 144 -               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 145 -               reg = <0x19c40000 0x1000>,
 146 -                     <0x19c00000 0x1000>;
 147 -               interrupts = <0 195 0x0>;
 148 -               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 149 -               clock-names = "core", "iface";
 150 -       };
 151 +               gcc: clock-controller@900000 {
 152 +                       compatible = "qcom,gcc-msm8660";
 153 +                       #clock-cells = <1>;
 154 +                       #reset-cells = <1>;
 155 +                       reg = <0x900000 0x4000>;
 156 +               };
 157 +
 158 +               gsbi12: gsbi@19c00000 {
 159 +                       compatible = "qcom,gsbi-v1.0.0";
 160 +                       reg = <0x19c00000 0x100>;
 161 +                       clocks = <&gcc GSBI12_H_CLK>;
 162 +                       clock-names = "iface";
 163 +                       #address-cells = <1>;
 164 +                       #size-cells = <1>;
 165 +                       ranges;
 166
 167 -       qcom,ssbi@500000 {
 168 -               compatible = "qcom,ssbi";
 169 -               reg = <0x500000 0x1000>;
 170 -               qcom,controller-type = "pmic-arbiter";
 171 +                       serial@19c40000 {
 172 +                               compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
 173 +                               reg = <0x19c40000 0x1000>,
 174 +                                     <0x19c00000 0x1000>;
 175 +                               interrupts = <0 195 0x0>;
 176 +                               clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
 177 +                               clock-names = "core", "iface";
 178 +                               status = "disabled";
 179 +                       };
 180 +               };
 181 +
 182 +               qcom,ssbi@500000 {
 183 +                       compatible = "qcom,ssbi";
 184 +                       reg = <0x500000 0x1000>;
 185 +                       qcom,controller-type = "pmic-arbiter";
 186 +               };
 187         };
 188  };
 189 --
 190 1.7.10.4
 191