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kernel: update 3.14 to 3.14.18
[openwrt/staging/yousong.git] / target / linux / ipq806x / patches / 0129-clk-qcom-Add-support-for-NSS-GMAC-clocks-and-resets.patch
1 From 92fde23153240a6173645dabe4d99f4aa6570bb7 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Mon, 28 Apr 2014 16:01:03 -0700
4 Subject: [PATCH 129/182] clk: qcom: Add support for NSS/GMAC clocks and
5 resets
6
7 The NSS driver expects one virtual clock that actually represents
8 two clocks (one for each UBI32 core). Register the ubi32 core
9 clocks and also make a wrapper virtual clock called nss_core_clk
10 to be used by the driver. This will properly handle switching the
11 rates of both clocks at the same time like how the NSS driver
12 expects it. Also add the TCM clock and the NSS resets.
13
14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 ---
16 drivers/clk/qcom/gcc-ipq806x.c | 710 +++++++++++++++++++++++++-
17 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 3 +
18 include/dt-bindings/reset/qcom,gcc-ipq806x.h | 43 ++
19 3 files changed, 755 insertions(+), 1 deletion(-)
20
21 --- a/drivers/clk/qcom/gcc-ipq806x.c
22 +++ b/drivers/clk/qcom/gcc-ipq806x.c
23 @@ -32,6 +32,33 @@
24 #include "clk-branch.h"
25 #include "reset.h"
26
27 +static struct clk_pll pll0 = {
28 + .l_reg = 0x30c4,
29 + .m_reg = 0x30c8,
30 + .n_reg = 0x30cc,
31 + .config_reg = 0x30d4,
32 + .mode_reg = 0x30c0,
33 + .status_reg = 0x30d8,
34 + .status_bit = 16,
35 + .clkr.hw.init = &(struct clk_init_data){
36 + .name = "pll0",
37 + .parent_names = (const char *[]){ "pxo" },
38 + .num_parents = 1,
39 + .ops = &clk_pll_ops,
40 + },
41 +};
42 +
43 +static struct clk_regmap pll0_vote = {
44 + .enable_reg = 0x34c0,
45 + .enable_mask = BIT(0),
46 + .hw.init = &(struct clk_init_data){
47 + .name = "pll0_vote",
48 + .parent_names = (const char *[]){ "pll0" },
49 + .num_parents = 1,
50 + .ops = &clk_pll_vote_ops,
51 + },
52 +};
53 +
54 static struct clk_pll pll3 = {
55 .l_reg = 0x3164,
56 .m_reg = 0x3168,
57 @@ -102,11 +129,46 @@ static struct clk_regmap pll14_vote = {
58 },
59 };
60
61 +#define NSS_PLL_RATE(f, _l, _m, _n, i) \
62 + { \
63 + .freq = f, \
64 + .l = _l, \
65 + .m = _m, \
66 + .n = _n, \
67 + .ibits = i, \
68 + }
69 +
70 +static struct pll_freq_tbl pll18_freq_tbl[] = {
71 + NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
72 + NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
73 +};
74 +
75 +static struct clk_pll pll18 = {
76 + .l_reg = 0x31a4,
77 + .m_reg = 0x31a8,
78 + .n_reg = 0x31ac,
79 + .config_reg = 0x31b4,
80 + .mode_reg = 0x31a0,
81 + .status_reg = 0x31b8,
82 + .status_bit = 16,
83 + .post_div_shift = 16,
84 + .post_div_width = 1,
85 + .freq_tbl = pll18_freq_tbl,
86 + .clkr.hw.init = &(struct clk_init_data){
87 + .name = "pll18",
88 + .parent_names = (const char *[]){ "pxo" },
89 + .num_parents = 1,
90 + .ops = &clk_pll_ops,
91 + },
92 +};
93 +
94 #define P_PXO 0
95 #define P_PLL8 1
96 #define P_PLL3 1
97 #define P_PLL0 2
98 #define P_CXO 2
99 +#define P_PLL14 3
100 +#define P_PLL18 4
101
102 static const u8 gcc_pxo_pll8_map[] = {
103 [P_PXO] = 0,
104 @@ -157,6 +219,22 @@ static const char *gcc_pxo_pll8_pll0_map
105 "pll0",
106 };
107
108 +static const u8 gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
109 + [P_PXO] = 0,
110 + [P_PLL8] = 4,
111 + [P_PLL0] = 2,
112 + [P_PLL14] = 5,
113 + [P_PLL18] = 1,
114 +};
115 +
116 +static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = {
117 + "pxo",
118 + "pll8_vote",
119 + "pll0_vote",
120 + "pll14",
121 + "pll18",
122 +};
123 +
124 static struct freq_tbl clk_tbl_gsbi_uart[] = {
125 { 1843200, P_PLL8, 2, 6, 625 },
126 { 3686400, P_PLL8, 2, 12, 625 },
127 @@ -2132,12 +2210,567 @@ static struct clk_branch usb_fs1_h_clk =
128 },
129 };
130
131 +static const struct freq_tbl clk_tbl_gmac[] = {
132 + { 133000000, P_PLL0, 1, 50, 301 },
133 + { }
134 +};
135 +
136 +static struct clk_dyn_rcg gmac_core1_src = {
137 + .ns_reg[0] = 0x3cac,
138 + .ns_reg[1] = 0x3cb0,
139 + .md_reg[0] = 0x3ca4,
140 + .md_reg[1] = 0x3ca8,
141 + .bank_reg = 0x3ca0,
142 + .mn[0] = {
143 + .mnctr_en_bit = 8,
144 + .mnctr_reset_bit = 7,
145 + .mnctr_mode_shift = 5,
146 + .n_val_shift = 16,
147 + .m_val_shift = 16,
148 + .width = 8,
149 + },
150 + .mn[1] = {
151 + .mnctr_en_bit = 8,
152 + .mnctr_reset_bit = 7,
153 + .mnctr_mode_shift = 5,
154 + .n_val_shift = 16,
155 + .m_val_shift = 16,
156 + .width = 8,
157 + },
158 + .s[0] = {
159 + .src_sel_shift = 0,
160 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
161 + },
162 + .s[1] = {
163 + .src_sel_shift = 0,
164 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
165 + },
166 + .p[0] = {
167 + .pre_div_shift = 3,
168 + .pre_div_width = 2,
169 + },
170 + .p[1] = {
171 + .pre_div_shift = 3,
172 + .pre_div_width = 2,
173 + },
174 + .mux_sel_bit = 0,
175 + .freq_tbl = clk_tbl_gmac,
176 + .clkr = {
177 + .enable_reg = 0x3ca0,
178 + .enable_mask = BIT(1),
179 + .hw.init = &(struct clk_init_data){
180 + .name = "gmac_core1_src",
181 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
182 + .num_parents = 5,
183 + .ops = &clk_dyn_rcg_ops,
184 + },
185 + },
186 +};
187 +
188 +static struct clk_branch gmac_core1_clk = {
189 + .halt_reg = 0x3c20,
190 + .halt_bit = 4,
191 + .hwcg_reg = 0x3cb4,
192 + .hwcg_bit = 6,
193 + .clkr = {
194 + .enable_reg = 0x3cb4,
195 + .enable_mask = BIT(4),
196 + .hw.init = &(struct clk_init_data){
197 + .name = "gmac_core1_clk",
198 + .parent_names = (const char *[]){
199 + "gmac_core1_src",
200 + },
201 + .num_parents = 1,
202 + .ops = &clk_branch_ops,
203 + .flags = CLK_SET_RATE_PARENT,
204 + },
205 + },
206 +};
207 +
208 +static struct clk_dyn_rcg gmac_core2_src = {
209 + .ns_reg[0] = 0x3ccc,
210 + .ns_reg[1] = 0x3cd0,
211 + .md_reg[0] = 0x3cc4,
212 + .md_reg[1] = 0x3cc8,
213 + .bank_reg = 0x3ca0,
214 + .mn[0] = {
215 + .mnctr_en_bit = 8,
216 + .mnctr_reset_bit = 7,
217 + .mnctr_mode_shift = 5,
218 + .n_val_shift = 16,
219 + .m_val_shift = 16,
220 + .width = 8,
221 + },
222 + .mn[1] = {
223 + .mnctr_en_bit = 8,
224 + .mnctr_reset_bit = 7,
225 + .mnctr_mode_shift = 5,
226 + .n_val_shift = 16,
227 + .m_val_shift = 16,
228 + .width = 8,
229 + },
230 + .s[0] = {
231 + .src_sel_shift = 0,
232 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
233 + },
234 + .s[1] = {
235 + .src_sel_shift = 0,
236 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
237 + },
238 + .p[0] = {
239 + .pre_div_shift = 3,
240 + .pre_div_width = 2,
241 + },
242 + .p[1] = {
243 + .pre_div_shift = 3,
244 + .pre_div_width = 2,
245 + },
246 + .mux_sel_bit = 0,
247 + .freq_tbl = clk_tbl_gmac,
248 + .clkr = {
249 + .enable_reg = 0x3cc0,
250 + .enable_mask = BIT(1),
251 + .hw.init = &(struct clk_init_data){
252 + .name = "gmac_core2_src",
253 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
254 + .num_parents = 5,
255 + .ops = &clk_dyn_rcg_ops,
256 + },
257 + },
258 +};
259 +
260 +static struct clk_branch gmac_core2_clk = {
261 + .halt_reg = 0x3c20,
262 + .halt_bit = 5,
263 + .hwcg_reg = 0x3cd4,
264 + .hwcg_bit = 6,
265 + .clkr = {
266 + .enable_reg = 0x3cd4,
267 + .enable_mask = BIT(4),
268 + .hw.init = &(struct clk_init_data){
269 + .name = "gmac_core2_clk",
270 + .parent_names = (const char *[]){
271 + "gmac_core2_src",
272 + },
273 + .num_parents = 1,
274 + .ops = &clk_branch_ops,
275 + .flags = CLK_SET_RATE_PARENT,
276 + },
277 + },
278 +};
279 +
280 +static struct clk_dyn_rcg gmac_core3_src = {
281 + .ns_reg[0] = 0x3cec,
282 + .ns_reg[1] = 0x3cf0,
283 + .md_reg[0] = 0x3ce4,
284 + .md_reg[1] = 0x3ce8,
285 + .bank_reg = 0x3ce0,
286 + .mn[0] = {
287 + .mnctr_en_bit = 8,
288 + .mnctr_reset_bit = 7,
289 + .mnctr_mode_shift = 5,
290 + .n_val_shift = 16,
291 + .m_val_shift = 16,
292 + .width = 8,
293 + },
294 + .mn[1] = {
295 + .mnctr_en_bit = 8,
296 + .mnctr_reset_bit = 7,
297 + .mnctr_mode_shift = 5,
298 + .n_val_shift = 16,
299 + .m_val_shift = 16,
300 + .width = 8,
301 + },
302 + .s[0] = {
303 + .src_sel_shift = 0,
304 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
305 + },
306 + .s[1] = {
307 + .src_sel_shift = 0,
308 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
309 + },
310 + .p[0] = {
311 + .pre_div_shift = 3,
312 + .pre_div_width = 2,
313 + },
314 + .p[1] = {
315 + .pre_div_shift = 3,
316 + .pre_div_width = 2,
317 + },
318 + .mux_sel_bit = 0,
319 + .freq_tbl = clk_tbl_gmac,
320 + .clkr = {
321 + .enable_reg = 0x3ce0,
322 + .enable_mask = BIT(1),
323 + .hw.init = &(struct clk_init_data){
324 + .name = "gmac_core3_src",
325 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
326 + .num_parents = 5,
327 + .ops = &clk_dyn_rcg_ops,
328 + },
329 + },
330 +};
331 +
332 +static struct clk_branch gmac_core3_clk = {
333 + .halt_reg = 0x3c20,
334 + .halt_bit = 6,
335 + .hwcg_reg = 0x3cf4,
336 + .hwcg_bit = 6,
337 + .clkr = {
338 + .enable_reg = 0x3cf4,
339 + .enable_mask = BIT(4),
340 + .hw.init = &(struct clk_init_data){
341 + .name = "gmac_core3_clk",
342 + .parent_names = (const char *[]){
343 + "gmac_core3_src",
344 + },
345 + .num_parents = 1,
346 + .ops = &clk_branch_ops,
347 + .flags = CLK_SET_RATE_PARENT,
348 + },
349 + },
350 +};
351 +
352 +static struct clk_dyn_rcg gmac_core4_src = {
353 + .ns_reg[0] = 0x3d0c,
354 + .ns_reg[1] = 0x3d10,
355 + .md_reg[0] = 0x3d04,
356 + .md_reg[1] = 0x3d08,
357 + .bank_reg = 0x3d00,
358 + .mn[0] = {
359 + .mnctr_en_bit = 8,
360 + .mnctr_reset_bit = 7,
361 + .mnctr_mode_shift = 5,
362 + .n_val_shift = 16,
363 + .m_val_shift = 16,
364 + .width = 8,
365 + },
366 + .mn[1] = {
367 + .mnctr_en_bit = 8,
368 + .mnctr_reset_bit = 7,
369 + .mnctr_mode_shift = 5,
370 + .n_val_shift = 16,
371 + .m_val_shift = 16,
372 + .width = 8,
373 + },
374 + .s[0] = {
375 + .src_sel_shift = 0,
376 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
377 + },
378 + .s[1] = {
379 + .src_sel_shift = 0,
380 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
381 + },
382 + .p[0] = {
383 + .pre_div_shift = 3,
384 + .pre_div_width = 2,
385 + },
386 + .p[1] = {
387 + .pre_div_shift = 3,
388 + .pre_div_width = 2,
389 + },
390 + .mux_sel_bit = 0,
391 + .freq_tbl = clk_tbl_gmac,
392 + .clkr = {
393 + .enable_reg = 0x3d00,
394 + .enable_mask = BIT(1),
395 + .hw.init = &(struct clk_init_data){
396 + .name = "gmac_core4_src",
397 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
398 + .num_parents = 5,
399 + .ops = &clk_dyn_rcg_ops,
400 + },
401 + },
402 +};
403 +
404 +static struct clk_branch gmac_core4_clk = {
405 + .halt_reg = 0x3c20,
406 + .halt_bit = 7,
407 + .hwcg_reg = 0x3d14,
408 + .hwcg_bit = 6,
409 + .clkr = {
410 + .enable_reg = 0x3d14,
411 + .enable_mask = BIT(4),
412 + .hw.init = &(struct clk_init_data){
413 + .name = "gmac_core4_clk",
414 + .parent_names = (const char *[]){
415 + "gmac_core4_src",
416 + },
417 + .num_parents = 1,
418 + .ops = &clk_branch_ops,
419 + .flags = CLK_SET_RATE_PARENT,
420 + },
421 + },
422 +};
423 +
424 +static const struct freq_tbl clk_tbl_nss_tcm[] = {
425 + { 266000000, P_PLL0, 3, 0, 0 },
426 + { 400000000, P_PLL0, 2, 0, 0 },
427 + { }
428 +};
429 +
430 +static struct clk_dyn_rcg nss_tcm_src = {
431 + .ns_reg[0] = 0x3dc4,
432 + .ns_reg[1] = 0x3dc8,
433 + .bank_reg = 0x3dc0,
434 + .s[0] = {
435 + .src_sel_shift = 0,
436 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
437 + },
438 + .s[1] = {
439 + .src_sel_shift = 0,
440 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
441 + },
442 + .p[0] = {
443 + .pre_div_shift = 3,
444 + .pre_div_width = 4,
445 + },
446 + .p[1] = {
447 + .pre_div_shift = 3,
448 + .pre_div_width = 4,
449 + },
450 + .mux_sel_bit = 0,
451 + .freq_tbl = clk_tbl_nss_tcm,
452 + .clkr = {
453 + .enable_reg = 0x3dc0,
454 + .enable_mask = BIT(1),
455 + .hw.init = &(struct clk_init_data){
456 + .name = "nss_tcm_src",
457 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
458 + .num_parents = 5,
459 + .ops = &clk_dyn_rcg_ops,
460 + },
461 + },
462 +};
463 +
464 +static struct clk_branch nss_tcm_clk = {
465 + .halt_reg = 0x3c20,
466 + .halt_bit = 14,
467 + .clkr = {
468 + .enable_reg = 0x3dd0,
469 + .enable_mask = BIT(6) | BIT(4),
470 + .hw.init = &(struct clk_init_data){
471 + .name = "nss_tcm_clk",
472 + .parent_names = (const char *[]){
473 + "nss_tcm_src",
474 + },
475 + .num_parents = 1,
476 + .ops = &clk_branch_ops,
477 + .flags = CLK_SET_RATE_PARENT,
478 + },
479 + },
480 +};
481 +
482 +static const struct freq_tbl clk_tbl_nss[] = {
483 + { 110000000, P_PLL18, 1, 1, 5 },
484 + { 275000000, P_PLL18, 2, 0, 0 },
485 + { 550000000, P_PLL18, 1, 0, 0 },
486 + { 733000000, P_PLL18, 1, 0, 0 },
487 + { }
488 +};
489 +
490 +static struct clk_dyn_rcg ubi32_core1_src_clk = {
491 + .ns_reg[0] = 0x3d2c,
492 + .ns_reg[1] = 0x3d30,
493 + .md_reg[0] = 0x3d24,
494 + .md_reg[1] = 0x3d28,
495 + .bank_reg = 0x3d20,
496 + .mn[0] = {
497 + .mnctr_en_bit = 8,
498 + .mnctr_reset_bit = 7,
499 + .mnctr_mode_shift = 5,
500 + .n_val_shift = 16,
501 + .m_val_shift = 16,
502 + .width = 8,
503 + },
504 + .mn[1] = {
505 + .mnctr_en_bit = 8,
506 + .mnctr_reset_bit = 7,
507 + .mnctr_mode_shift = 5,
508 + .n_val_shift = 16,
509 + .m_val_shift = 16,
510 + .width = 8,
511 + },
512 + .s[0] = {
513 + .src_sel_shift = 0,
514 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
515 + },
516 + .s[1] = {
517 + .src_sel_shift = 0,
518 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
519 + },
520 + .p[0] = {
521 + .pre_div_shift = 3,
522 + .pre_div_width = 2,
523 + },
524 + .p[1] = {
525 + .pre_div_shift = 3,
526 + .pre_div_width = 2,
527 + },
528 + .mux_sel_bit = 0,
529 + .freq_tbl = clk_tbl_nss,
530 + .clkr = {
531 + .enable_reg = 0x3d20,
532 + .enable_mask = BIT(1),
533 + .hw.init = &(struct clk_init_data){
534 + .name = "ubi32_core1_src_clk",
535 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
536 + .num_parents = 5,
537 + .ops = &clk_dyn_rcg_ops,
538 + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
539 + },
540 + },
541 +};
542 +
543 +static struct clk_dyn_rcg ubi32_core2_src_clk = {
544 + .ns_reg[0] = 0x3d4c,
545 + .ns_reg[1] = 0x3d50,
546 + .md_reg[0] = 0x3d44,
547 + .md_reg[1] = 0x3d48,
548 + .bank_reg = 0x3d40,
549 + .mn[0] = {
550 + .mnctr_en_bit = 8,
551 + .mnctr_reset_bit = 7,
552 + .mnctr_mode_shift = 5,
553 + .n_val_shift = 16,
554 + .m_val_shift = 16,
555 + .width = 8,
556 + },
557 + .mn[1] = {
558 + .mnctr_en_bit = 8,
559 + .mnctr_reset_bit = 7,
560 + .mnctr_mode_shift = 5,
561 + .n_val_shift = 16,
562 + .m_val_shift = 16,
563 + .width = 8,
564 + },
565 + .s[0] = {
566 + .src_sel_shift = 0,
567 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
568 + },
569 + .s[1] = {
570 + .src_sel_shift = 0,
571 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
572 + },
573 + .p[0] = {
574 + .pre_div_shift = 3,
575 + .pre_div_width = 2,
576 + },
577 + .p[1] = {
578 + .pre_div_shift = 3,
579 + .pre_div_width = 2,
580 + },
581 + .mux_sel_bit = 0,
582 + .freq_tbl = clk_tbl_nss,
583 + .clkr = {
584 + .enable_reg = 0x3d40,
585 + .enable_mask = BIT(1),
586 + .hw.init = &(struct clk_init_data){
587 + .name = "ubi32_core2_src_clk",
588 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
589 + .num_parents = 5,
590 + .ops = &clk_dyn_rcg_ops,
591 + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
592 + },
593 + },
594 +};
595 +
596 +static int nss_core_clk_set_rate(struct clk_hw *hw, unsigned long rate,
597 + unsigned long parent_rate)
598 +{
599 + int ret;
600 +
601 + ret = clk_dyn_rcg_ops.set_rate(&ubi32_core1_src_clk.clkr.hw, rate,
602 + parent_rate);
603 + if (ret)
604 + return ret;
605 +
606 + return clk_dyn_rcg_ops.set_rate(&ubi32_core2_src_clk.clkr.hw, rate,
607 + parent_rate);
608 +}
609 +
610 +static int
611 +nss_core_clk_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
612 + unsigned long parent_rate, u8 index)
613 +{
614 + int ret;
615 +
616 + ret = clk_dyn_rcg_ops.set_rate_and_parent(
617 + &ubi32_core1_src_clk.clkr.hw, rate, parent_rate, index);
618 + if (ret)
619 + return ret;
620 +
621 + ret = clk_dyn_rcg_ops.set_rate_and_parent(
622 + &ubi32_core2_src_clk.clkr.hw, rate, parent_rate, index);
623 + return ret;
624 +}
625 +
626 +static long nss_core_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
627 + unsigned long *p_rate, struct clk **p)
628 +{
629 + return clk_dyn_rcg_ops.determine_rate(&ubi32_core1_src_clk.clkr.hw,
630 + rate, p_rate, p);
631 +}
632 +
633 +static unsigned long
634 +nss_core_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
635 +{
636 + return clk_dyn_rcg_ops.recalc_rate(&ubi32_core1_src_clk.clkr.hw,
637 + parent_rate);
638 +}
639 +
640 +static u8 nss_core_clk_get_parent(struct clk_hw *hw)
641 +{
642 + return clk_dyn_rcg_ops.get_parent(&ubi32_core1_src_clk.clkr.hw);
643 +}
644 +
645 +static int nss_core_clk_set_parent(struct clk_hw *hw, u8 i)
646 +{
647 + int ret;
648 +
649 + ret = clk_dyn_rcg_ops.set_parent(&ubi32_core1_src_clk.clkr.hw, i);
650 + if (ret)
651 + return ret;
652 +
653 + return clk_dyn_rcg_ops.set_parent(&ubi32_core2_src_clk.clkr.hw, i);
654 +}
655 +
656 +static struct clk *nss_core_clk_get_safe_parent(struct clk_hw *hw)
657 +{
658 + return clk_get_parent_by_index(hw->clk,
659 + ubi32_core2_src_clk.s[0].parent_map[P_PLL8]);
660 +}
661 +
662 +static const struct clk_ops clk_ops_nss_core = {
663 + .set_rate = nss_core_clk_set_rate,
664 + .set_rate_and_parent = nss_core_clk_set_rate_and_parent,
665 + .determine_rate = nss_core_clk_determine_rate,
666 + .recalc_rate = nss_core_clk_recalc_rate,
667 + .get_parent = nss_core_clk_get_parent,
668 + .set_parent = nss_core_clk_set_parent,
669 + .get_safe_parent = nss_core_clk_get_safe_parent,
670 +};
671 +
672 +/* Virtual clock for nss core clocks */
673 +static struct clk_regmap nss_core_clk = {
674 + .hw.init = &(struct clk_init_data){
675 + .name = "nss_core_clk",
676 + .ops = &clk_ops_nss_core,
677 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
678 + .num_parents = 5,
679 + .flags = CLK_SET_RATE_PARENT,
680 + },
681 +};
682 +
683 static struct clk_regmap *gcc_ipq806x_clks[] = {
684 + [PLL0] = &pll0.clkr,
685 + [PLL0_VOTE] = &pll0_vote,
686 [PLL3] = &pll3.clkr,
687 [PLL8] = &pll8.clkr,
688 [PLL8_VOTE] = &pll8_vote,
689 [PLL14] = &pll14.clkr,
690 [PLL14_VOTE] = &pll14_vote,
691 + [PLL18] = &pll18.clkr,
692 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
693 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
694 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
695 @@ -2232,6 +2865,19 @@ static struct clk_regmap *gcc_ipq806x_cl
696 [USB_FS1_XCVR_SRC] = &usb_fs1_xcvr_clk_src.clkr,
697 [USB_FS1_XCVR_CLK] = &usb_fs1_xcvr_clk.clkr,
698 [USB_FS1_SYSTEM_CLK] = &usb_fs1_sys_clk.clkr,
699 + [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
700 + [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
701 + [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
702 + [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
703 + [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
704 + [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
705 + [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
706 + [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
707 + [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
708 + [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
709 + [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
710 + [NSSTCM_CLK] = &nss_tcm_clk.clkr,
711 + [NSS_CORE_CLK] = &nss_core_clk,
712 };
713
714 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
715 @@ -2350,6 +2996,48 @@ static const struct qcom_reset_map gcc_i
716 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
717 [NSSFB0_RESET] = { 0x3b60, 6 },
718 [NSSFB1_RESET] = { 0x3b60, 7 },
719 + [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
720 + [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
721 + [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
722 + [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
723 + [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
724 + [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
725 + [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
726 + [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
727 + [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
728 + [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
729 + [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
730 + [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
731 + [GMAC_AHB_RESET] = { 0x3e24, 0 },
732 + [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
733 + [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
734 + [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
735 + [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
736 + [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
737 + [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
738 + [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
739 + [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
740 + [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
741 + [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
742 + [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
743 + [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
744 + [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
745 + [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
746 + [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
747 + [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
748 + [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
749 + [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
750 + [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
751 + [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
752 + [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
753 + [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
754 + [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
755 + [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
756 + [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
757 + [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
758 + [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
759 + [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
760 + [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
761 };
762
763 static const struct regmap_config gcc_ipq806x_regmap_config = {
764 @@ -2378,6 +3066,8 @@ static int gcc_ipq806x_probe(struct plat
765 {
766 struct clk *clk;
767 struct device *dev = &pdev->dev;
768 + struct regmap *regmap;
769 + int ret;
770
771 /* Temporary until RPM clocks supported */
772 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
773 @@ -2388,7 +3078,25 @@ static int gcc_ipq806x_probe(struct plat
774 if (IS_ERR(clk))
775 return PTR_ERR(clk);
776
777 - return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
778 + ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
779 + if (ret)
780 + return ret;
781 +
782 + regmap = dev_get_regmap(dev, NULL);
783 + if (!regmap)
784 + return -ENODEV;
785 +
786 + /* Setup PLL18 static bits */
787 + regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
788 + regmap_write(regmap, 0x31b0, 0x3080);
789 +
790 + /* Set GMAC footswitch sleep/wakeup values */
791 + regmap_write(regmap, 0x3cb8, 8);
792 + regmap_write(regmap, 0x3cd8, 8);
793 + regmap_write(regmap, 0x3cf8, 8);
794 + regmap_write(regmap, 0x3d18, 8);
795 +
796 + return 0;
797 }
798
799 static int gcc_ipq806x_remove(struct platform_device *pdev)
800 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
801 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
802 @@ -289,5 +289,8 @@
803 #define UBI32_CORE2_CLK_SRC 277
804 #define UBI32_CORE1_CLK 278
805 #define UBI32_CORE2_CLK 279
806 +#define NSSTCM_CLK_SRC 280
807 +#define NSSTCM_CLK 281
808 +#define NSS_CORE_CLK 282 /* Virtual */
809
810 #endif
811 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
812 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
813 @@ -129,4 +129,47 @@
814 #define USB30_1_PHY_RESET 112
815 #define NSSFB0_RESET 113
816 #define NSSFB1_RESET 114
817 +#define UBI32_CORE1_CLKRST_CLAMP_RESET 115
818 +#define UBI32_CORE1_CLAMP_RESET 116
819 +#define UBI32_CORE1_AHB_RESET 117
820 +#define UBI32_CORE1_AXI_RESET 118
821 +#define UBI32_CORE2_CLKRST_CLAMP_RESET 119
822 +#define UBI32_CORE2_CLAMP_RESET 120
823 +#define UBI32_CORE2_AHB_RESET 121
824 +#define UBI32_CORE2_AXI_RESET 122
825 +#define GMAC_CORE1_RESET 123
826 +#define GMAC_CORE2_RESET 124
827 +#define GMAC_CORE3_RESET 125
828 +#define GMAC_CORE4_RESET 126
829 +#define GMAC_AHB_RESET 127
830 +#define NSS_CH0_RST_RX_CLK_N_RESET 128
831 +#define NSS_CH0_RST_TX_CLK_N_RESET 129
832 +#define NSS_CH0_RST_RX_125M_N_RESET 130
833 +#define NSS_CH0_HW_RST_RX_125M_N_RESET 131
834 +#define NSS_CH0_RST_TX_125M_N_RESET 132
835 +#define NSS_CH1_RST_RX_CLK_N_RESET 133
836 +#define NSS_CH1_RST_TX_CLK_N_RESET 134
837 +#define NSS_CH1_RST_RX_125M_N_RESET 135
838 +#define NSS_CH1_HW_RST_RX_125M_N_RESET 136
839 +#define NSS_CH1_RST_TX_125M_N_RESET 137
840 +#define NSS_CH2_RST_RX_CLK_N_RESET 138
841 +#define NSS_CH2_RST_TX_CLK_N_RESET 139
842 +#define NSS_CH2_RST_RX_125M_N_RESET 140
843 +#define NSS_CH2_HW_RST_RX_125M_N_RESET 141
844 +#define NSS_CH2_RST_TX_125M_N_RESET 142
845 +#define NSS_CH3_RST_RX_CLK_N_RESET 143
846 +#define NSS_CH3_RST_TX_CLK_N_RESET 144
847 +#define NSS_CH3_RST_RX_125M_N_RESET 145
848 +#define NSS_CH3_HW_RST_RX_125M_N_RESET 146
849 +#define NSS_CH3_RST_TX_125M_N_RESET 147
850 +#define NSS_RST_RX_250M_125M_N_RESET 148
851 +#define NSS_RST_TX_250M_125M_N_RESET 149
852 +#define NSS_QSGMII_TXPI_RST_N_RESET 150
853 +#define NSS_QSGMII_CDR_RST_N_RESET 151
854 +#define NSS_SGMII2_CDR_RST_N_RESET 152
855 +#define NSS_SGMII3_CDR_RST_N_RESET 153
856 +#define NSS_CAL_PRBS_RST_N_RESET 154
857 +#define NSS_LCKDT_RST_N_RESET 155
858 +#define NSS_SRDS_N_RESET 156
859 +
860 #endif
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