target/linux/ipq806x/patches/0135-spi-qup-Add-support-for-v1.1.1.patch

   1 From 8b9de04ef3aaa154f30baf1ac703a2d3b474ad4e Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Thu, 12 Jun 2014 14:34:12 -0500
   4 Subject: [PATCH 135/182] spi: qup: Add support for v1.1.1
   5
   6 This patch adds support for v1.1.1 of the SPI QUP controller.
   7
   8 Signed-off-by: Andy Gross <agross@codeaurora.org>
   9 ---
  10  .../devicetree/bindings/spi/qcom,spi-qup.txt       |    6 +++-
  11  drivers/spi/spi-qup.c                              |   36 ++++++++++++--------
  12  2 files changed, 27 insertions(+), 15 deletions(-)
  13
  14 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  15 +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
  16 @@ -7,7 +7,11 @@ SPI in master mode supports up to 50MHz,
  17  data path from 4 bits to 32 bits and numerous protocol variants.
  18
  19  Required properties:
  20 -- compatible:     Should contain "qcom,spi-qup-v2.1.1" or "qcom,spi-qup-v2.2.1"
  21 +- compatible:     Should contain:
  22 +                 "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
  23 +                 "qcom,spi-qup-v2.1.1" for 8974 and later
  24 +                 "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
  25 +
  26  - reg:            Should contain base register location and length
  27  - interrupts:     Interrupt number used by this controller
  28
  29 --- a/drivers/spi/spi-qup.c
  30 +++ b/drivers/spi/spi-qup.c
  31 @@ -142,6 +142,7 @@ struct spi_qup {
  32         int                     w_size; /* bytes per SPI word */
  33         int                     tx_bytes;
  34         int                     rx_bytes;
  35 +       int                     qup_v1;
  36  };
  37
  38
  39 @@ -420,7 +421,9 @@ static int spi_qup_io_config(struct spi_
  40         config |= QUP_CONFIG_SPI_MODE;
  41         writel_relaxed(config, controller->base + QUP_CONFIG);
  42
  43 -       writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
  44 +       /* only write to OPERATIONAL_MASK when register is present */
  45 +       if (!controller->qup_v1)
  46 +               writel_relaxed(0, controller->base + QUP_OPERATIONAL_MASK);
  47         return 0;
  48  }
  49
  50 @@ -486,7 +489,7 @@ static int spi_qup_probe(struct platform
  51         struct resource *res;
  52         struct device *dev;
  53         void __iomem *base;
  54 -       u32 data, max_freq, iomode;
  55 +       u32 max_freq, iomode;
  56         int ret, irq, size;
  57
  58         dev = &pdev->dev;
  59 @@ -529,15 +532,6 @@ static int spi_qup_probe(struct platform
  60                 return ret;
  61         }
  62
  63 -       data = readl_relaxed(base + QUP_HW_VERSION);
  64 -
  65 -       if (data < QUP_HW_VERSION_2_1_1) {
  66 -               clk_disable_unprepare(cclk);
  67 -               clk_disable_unprepare(iclk);
  68 -               dev_err(dev, "v.%08x is not supported\n", data);
  69 -               return -ENXIO;
  70 -       }
  71 -
  72         master = spi_alloc_master(dev, sizeof(struct spi_qup));
  73         if (!master) {
  74                 clk_disable_unprepare(cclk);
  75 @@ -570,6 +564,10 @@ static int spi_qup_probe(struct platform
  76         controller->cclk = cclk;
  77         controller->irq = irq;
  78
  79 +       /* set v1 flag if device is version 1 */
  80 +       if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
  81 +               controller->qup_v1 = 1;
  82 +
  83         spin_lock_init(&controller->lock);
  84         init_completion(&controller->done);
  85
  86 @@ -593,8 +591,8 @@ static int spi_qup_probe(struct platform
  87         size = QUP_IO_M_INPUT_FIFO_SIZE(iomode);
  88         controller->in_fifo_sz = controller->in_blk_sz * (2 << size);
  89
  90 -       dev_info(dev, "v.%08x IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
  91 -                data, controller->in_blk_sz, controller->in_fifo_sz,
  92 +       dev_info(dev, "IN:block:%d, fifo:%d, OUT:block:%d, fifo:%d\n",
  93 +                controller->in_blk_sz, controller->in_fifo_sz,
  94                  controller->out_blk_sz, controller->out_fifo_sz);
  95
  96         writel_relaxed(1, base + QUP_SW_RESET);
  97 @@ -607,10 +605,19 @@ static int spi_qup_probe(struct platform
  98
  99         writel_relaxed(0, base + QUP_OPERATIONAL);
 100         writel_relaxed(0, base + QUP_IO_M_MODES);
 101 -       writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
 102 +
 103 +       if (!controller->qup_v1)
 104 +               writel_relaxed(0, base + QUP_OPERATIONAL_MASK);
 105 +
 106         writel_relaxed(SPI_ERROR_CLK_UNDER_RUN | SPI_ERROR_CLK_OVER_RUN,
 107                        base + SPI_ERROR_FLAGS_EN);
 108
 109 +       /* if earlier version of the QUP, disable INPUT_OVERRUN */
 110 +       if (controller->qup_v1)
 111 +               writel_relaxed(QUP_ERROR_OUTPUT_OVER_RUN |
 112 +                       QUP_ERROR_INPUT_UNDER_RUN | QUP_ERROR_OUTPUT_UNDER_RUN,
 113 +                       base + QUP_ERROR_FLAGS_EN);
 114 +
 115         writel_relaxed(0, base + SPI_CONFIG);
 116         writel_relaxed(SPI_IO_C_NO_TRI_STATE, base + SPI_IO_CONTROL);
 117
 118 @@ -732,6 +739,7 @@ static int spi_qup_remove(struct platfor
 119  }
 120
 121  static struct of_device_id spi_qup_dt_match[] = {
 122 +       { .compatible = "qcom,spi-qup-v1.1.1", },
 123         { .compatible = "qcom,spi-qup-v2.1.1", },
 124         { .compatible = "qcom,spi-qup-v2.2.1", },
 125         { }