ipq806x: add support for Arris TR4400 v2 / RAC2V1A
[openwrt/staging/chunkeey.git] / target / linux / ipq806x / patches-5.10 / 082-ipq8064-dtsi-tweaks.patch
1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
3 @@ -20,7 +20,7 @@
4 #address-cells = <1>;
5 #size-cells = <0>;
6
7 - cpu@0 {
8 + cpu0: cpu@0 {
9 compatible = "qcom,krait";
10 enable-method = "qcom,kpss-acc-v1";
11 device_type = "cpu";
12 @@ -30,7 +30,7 @@
13 qcom,saw = <&saw0>;
14 };
15
16 - cpu@1 {
17 + cpu1: cpu@1 {
18 compatible = "qcom,krait";
19 enable-method = "qcom,kpss-acc-v1";
20 device_type = "cpu";
21 @@ -67,7 +67,7 @@
22 no-map;
23 };
24
25 - smem@41000000 {
26 + smem: smem@41000000 {
27 reg = <0x41000000 0x200000>;
28 no-map;
29 };
30 @@ -128,6 +128,7 @@
31 gpio-ranges = <&qcom_pinmux 0 0 69>;
32 #gpio-cells = <2>;
33 interrupt-controller;
34 + #address-cells = <0>;
35 #interrupt-cells = <2>;
36 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
37
38 @@ -155,6 +156,7 @@
39 function = "pcie3_rst";
40 drive-strength = <12>;
41 bias-disable;
42 + output-low;
43 };
44 };
45
46 @@ -190,6 +192,7 @@
47 intc: interrupt-controller@2000000 {
48 compatible = "qcom,msm-qgic2";
49 interrupt-controller;
50 + #address-cells = <0>;
51 #interrupt-cells = <3>;
52 reg = <0x02000000 0x1000>,
53 <0x02002000 0x1000>;
54 @@ -219,21 +222,23 @@
55 acc0: clock-controller@2088000 {
56 compatible = "qcom,kpss-acc-v1";
57 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
58 + clock-output-names = "acpu0_aux";
59 };
60
61 acc1: clock-controller@2098000 {
62 compatible = "qcom,kpss-acc-v1";
63 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
64 + clock-output-names = "acpu1_aux";
65 };
66
67 saw0: regulator@2089000 {
68 - compatible = "qcom,saw2";
69 + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
70 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
71 regulator;
72 };
73
74 saw1: regulator@2099000 {
75 - compatible = "qcom,saw2";
76 + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
77 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
78 regulator;
79 };
80 @@ -251,7 +256,7 @@
81
82 syscon-tcsr = <&tcsr>;
83
84 - serial@12490000 {
85 + gsbi2_serial: serial@12490000 {
86 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
87 reg = <0x12490000 0x1000>,
88 <0x12480000 0x1000>;
89 @@ -261,7 +266,7 @@
90 status = "disabled";
91 };
92
93 - i2c@124a0000 {
94 + gsbi2_i2c: i2c@124a0000 {
95 compatible = "qcom,i2c-qup-v1.1.1";
96 reg = <0x124a0000 0x1000>;
97 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
98 @@ -326,7 +331,7 @@
99
100 syscon-tcsr = <&tcsr>;
101
102 - serial@1a240000 {
103 + gsbi5_serial: serial@1a240000 {
104 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
105 reg = <0x1a240000 0x1000>,
106 <0x1a200000 0x1000>;
107 @@ -397,7 +402,7 @@
108 status = "disabled";
109 };
110
111 - sata@29000000 {
112 + sata: sata@29000000 {
113 compatible = "qcom,ipq806x-ahci", "generic-ahci";
114 reg = <0x29000000 0x180>;
115
116 @@ -430,13 +435,35 @@
117 reg = <0x00700000 0x1000>;
118 #address-cells = <1>;
119 #size-cells = <1>;
120 +
121 + tsens_calib: calib@400 {
122 + reg = <0x400 0xb>;
123 + };
124 + tsens_backup: backup@410 {
125 + reg = <0x410 0xb>;
126 + };
127 + speedbin_efuse: speedbin@0c0 {
128 + reg = <0x0c0 0x4>;
129 + };
130 };
131
132 gcc: clock-controller@900000 {
133 - compatible = "qcom,gcc-ipq8064";
134 + compatible = "qcom,gcc-ipq8064", "syscon";
135 reg = <0x00900000 0x4000>;
136 #clock-cells = <1>;
137 #reset-cells = <1>;
138 + #power-domain-cells = <1>;
139 +
140 + tsens: thermal-sensor@900000 {
141 + compatible = "qcom,ipq8064-tsens";
142 +
143 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
144 + nvmem-cell-names = "calib", "calib_backup";
145 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
146 + interrupt-names = "uplow";
147 + #thermal-sensor-cells = <1>;
148 + #qcom,sensors = <11>;
149 + };
150 };
151
152 tcsr: syscon@1a400000 {
153 @@ -622,7 +649,7 @@
154
155 gmac0: ethernet@37000000 {
156 device_type = "network";
157 - compatible = "qcom,ipq806x-gmac";
158 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
159 reg = <0x37000000 0x200000>;
160 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-names = "macirq";
162 @@ -645,7 +672,7 @@
163
164 gmac1: ethernet@37200000 {
165 device_type = "network";
166 - compatible = "qcom,ipq806x-gmac";
167 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
168 reg = <0x37200000 0x200000>;
169 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
170 interrupt-names = "macirq";
171 @@ -668,7 +695,7 @@
172
173 gmac2: ethernet@37400000 {
174 device_type = "network";
175 - compatible = "qcom,ipq806x-gmac";
176 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
177 reg = <0x37400000 0x200000>;
178 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
179 interrupt-names = "macirq";
180 @@ -691,7 +718,7 @@
181
182 gmac3: ethernet@37600000 {
183 device_type = "network";
184 - compatible = "qcom,ipq806x-gmac";
185 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
186 reg = <0x37600000 0x200000>;
187 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
188 interrupt-names = "macirq";
189 @@ -740,13 +767,13 @@
190 qcom,ee = <0>;
191 };
192
193 - amba {
194 - compatible = "simple-bus";
195 + amba: amba {
196 + compatible = "arm,amba-bus";
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges;
200
201 - sdcc@12400000 {
202 + sdcc1: sdcc@12400000 {
203 status = "disabled";
204 compatible = "arm,pl18x", "arm,primecell";
205 arm,primecell-periphid = <0x00051180>;
206 @@ -760,13 +787,12 @@
207 non-removable;
208 cap-sd-highspeed;
209 cap-mmc-highspeed;
210 - mmc-ddr-1_8v;
211 vmmc-supply = <&vsdcc_fixed>;
212 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
213 dma-names = "tx", "rx";
214 };
215
216 - sdcc@12180000 {
217 + sdcc3: sdcc@12180000 {
218 compatible = "arm,pl18x", "arm,primecell";
219 arm,primecell-periphid = <0x00051180>;
220 status = "disabled";