target/linux/ipq806x/patches-5.10/097-4-ipq806x-gcc-add-missing-clk-and-reset-for-crypto-eng.patch

   1 From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Sun, 7 Feb 2021 17:23:38 +0100
   4 Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
   5
   6 Add missing clk and reset needed for nss additional core and crypto
   7 engine.
   8
   9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  10 ---
  11  drivers/clk/qcom/gcc-ipq806x.c               | 250 +++++++++++++++++++
  12  include/dt-bindings/clock/qcom,gcc-ipq806x.h |   5 +-
  13  include/dt-bindings/reset/qcom,gcc-ipq806x.h |   5 +
  14  3 files changed, 259 insertions(+), 1 deletion(-)
  15
  16 --- a/drivers/clk/qcom/gcc-ipq806x.c
  17 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  18 @@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
  19
  20  static struct pll_freq_tbl pll18_freq_tbl[] = {
  21         NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
  22 +       NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
  23         NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
  24 +       NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
  25  };
  26
  27  static struct clk_pll pll18 = {
  28 @@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
  29         },
  30  };
  31
  32 +static struct clk_pll pll11 = {
  33 +       .l_reg = 0x3184,
  34 +       .m_reg = 0x3188,
  35 +       .n_reg = 0x318c,
  36 +       .config_reg = 0x3194,
  37 +       .mode_reg = 0x3180,
  38 +       .status_reg = 0x3198,
  39 +       .status_bit = 16,
  40 +       .clkr.hw.init = &(struct clk_init_data){
  41 +               .name = "pll11",
  42 +               .parent_names = (const char *[]){ "pxo" },
  43 +               .num_parents = 1,
  44 +               .ops = &clk_pll_ops,
  45 +       },
  46 +};
  47 +
  48  enum {
  49         P_PXO,
  50         P_PLL8,
  51 @@ -253,6 +271,7 @@ enum {
  52         P_CXO,
  53         P_PLL14,
  54         P_PLL18,
  55 +       P_PLL11,
  56  };
  57
  58  static const struct parent_map gcc_pxo_pll8_map[] = {
  59 @@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p
  60         "pll18",
  61  };
  62
  63 +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
  64 +       { P_PXO, 0 },
  65 +       { P_PLL8, 4 },
  66 +       { P_PLL0, 2 },
  67 +       { P_PLL14, 5 },
  68 +       { P_PLL18, 1 },
  69 +       { P_PLL11, 3 },
  70 +};
  71 +
  72 +static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
  73 +       "pxo",
  74 +       "pll8_vote",
  75 +       "pll0_vote",
  76 +       "pll14",
  77 +       "pll18",
  78 +       "pll11"
  79 +};
  80 +
  81 +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
  82 +       { P_PXO, 0 },
  83 +       { P_PLL3, 6 },
  84 +       { P_PLL0, 2 },
  85 +       { P_PLL14, 5 },
  86 +       { P_PLL18, 1 },
  87 +       { P_PLL11, 3 },
  88 +};
  89 +
  90 +static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
  91 +       "pxo",
  92 +       "pll3",
  93 +       "pll0_vote",
  94 +       "pll14",
  95 +       "pll18",
  96 +       "pll11"
  97 +};
  98 +
  99  static struct freq_tbl clk_tbl_gsbi_uart[] = {
 100         {  1843200, P_PLL8, 2,  6, 625 },
 101         {  3686400, P_PLL8, 2, 12, 625 },
 102 @@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc
 103         {  20210000, P_PLL8,  1, 1,  19 },
 104         {  24000000, P_PLL8,  4, 1,   4 },
 105         {  48000000, P_PLL8,  4, 1,   2 },
 106 +       {  52000000, P_PLL8,  1, 2,  15 }, /* 51.2 Mhz */
 107         {  64000000, P_PLL8,  3, 1,   2 },
 108         {  96000000, P_PLL8,  4, 0,   0 },
 109         { 192000000, P_PLL8,  2, 0,   0 },
 110 @@ -2647,7 +2703,9 @@ static const struct freq_tbl clk_tbl_nss
 111         { 110000000, P_PLL18, 1, 1, 5 },
 112         { 275000000, P_PLL18, 2, 0, 0 },
 113         { 550000000, P_PLL18, 1, 0, 0 },
 114 +       { 600000000, P_PLL18, 1, 0, 0 },
 115         { 733000000, P_PLL18, 1, 0, 0 },
 116 +       { 800000000, P_PLL18, 1, 0, 0 },
 117         { }
 118  };
 119
 120 @@ -2759,6 +2817,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
 121         },
 122  };
 123
 124 +static const struct freq_tbl clk_tbl_ce5_core[] = {
 125 +       { 150000000, P_PLL3, 8, 1, 1 },
 126 +       { 213200000, P_PLL11, 5, 1, 1 },
 127 +       { }
 128 +};
 129 +
 130 +static struct clk_dyn_rcg ce5_core_src = {
 131 +       .ns_reg[0] = 0x36C4,
 132 +       .ns_reg[1] = 0x36C8,
 133 +       .bank_reg = 0x36C0,
 134 +       .s[0] = {
 135 +               .src_sel_shift = 0,
 136 +               .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
 137 +       },
 138 +       .s[1] = {
 139 +               .src_sel_shift = 0,
 140 +               .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
 141 +       },
 142 +       .p[0] = {
 143 +               .pre_div_shift = 3,
 144 +               .pre_div_width = 4,
 145 +       },
 146 +       .p[1] = {
 147 +               .pre_div_shift = 3,
 148 +               .pre_div_width = 4,
 149 +       },
 150 +       .mux_sel_bit = 0,
 151 +       .freq_tbl = clk_tbl_ce5_core,
 152 +       .clkr = {
 153 +               .enable_reg = 0x36C0,
 154 +               .enable_mask = BIT(1),
 155 +               .hw.init = &(struct clk_init_data){
 156 +                       .name = "ce5_core_src",
 157 +                       .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
 158 +                       .num_parents = 6,
 159 +                       .ops = &clk_dyn_rcg_ops,
 160 +               },
 161 +       },
 162 +};
 163 +
 164 +static struct clk_branch ce5_core_clk = {
 165 +       .halt_reg = 0x2FDC,
 166 +       .halt_bit = 5,
 167 +       .hwcg_reg = 0x36CC,
 168 +       .hwcg_bit = 6,
 169 +       .clkr = {
 170 +               .enable_reg = 0x36CC,
 171 +               .enable_mask = BIT(4),
 172 +               .hw.init = &(struct clk_init_data){
 173 +                       .name = "ce5_core_clk",
 174 +                       .parent_names = (const char *[]){
 175 +                               "ce5_core_src",
 176 +                       },
 177 +                       .num_parents = 1,
 178 +                       .ops = &clk_branch_ops,
 179 +                       .flags = CLK_SET_RATE_PARENT,
 180 +               },
 181 +       },
 182 +};
 183 +
 184 +static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
 185 +       { 160000000, P_PLL0, 5, 1, 1 },
 186 +       { 213200000, P_PLL11, 5, 1, 1 },
 187 +       { }
 188 +};
 189 +
 190 +static struct clk_dyn_rcg ce5_a_clk_src = {
 191 +       .ns_reg[0] = 0x3d84,
 192 +       .ns_reg[1] = 0x3d88,
 193 +       .bank_reg = 0x3d80,
 194 +       .s[0] = {
 195 +               .src_sel_shift = 0,
 196 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 197 +       },
 198 +       .s[1] = {
 199 +               .src_sel_shift = 0,
 200 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 201 +       },
 202 +       .p[0] = {
 203 +               .pre_div_shift = 3,
 204 +               .pre_div_width = 4,
 205 +       },
 206 +       .p[1] = {
 207 +               .pre_div_shift = 3,
 208 +               .pre_div_width = 4,
 209 +       },
 210 +       .mux_sel_bit = 0,
 211 +       .freq_tbl = clk_tbl_ce5_a_clk,
 212 +       .clkr = {
 213 +               .enable_reg = 0x3d80,
 214 +               .enable_mask = BIT(1),
 215 +               .hw.init = &(struct clk_init_data){
 216 +                       .name = "ce5_a_clk_src",
 217 +                       .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
 218 +                       .num_parents = 6,
 219 +                       .ops = &clk_dyn_rcg_ops,
 220 +               },
 221 +       },
 222 +};
 223 +
 224 +static struct clk_branch ce5_a_clk = {
 225 +       .halt_reg = 0x3c20,
 226 +       .halt_bit = 12,
 227 +       .hwcg_reg = 0x3d8c,
 228 +       .hwcg_bit = 6,
 229 +       .clkr = {
 230 +               .enable_reg = 0x3d8c,
 231 +               .enable_mask = BIT(4),
 232 +               .hw.init = &(struct clk_init_data){
 233 +                       .name = "ce5_a_clk",
 234 +                       .parent_names = (const char *[]){
 235 +                               "ce5_a_clk_src",
 236 +                       },
 237 +                       .num_parents = 1,
 238 +                       .ops = &clk_branch_ops,
 239 +                       .flags = CLK_SET_RATE_PARENT,
 240 +               },
 241 +       },
 242 +};
 243 +
 244 +static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
 245 +       { 160000000, P_PLL0, 5, 1, 1 },
 246 +       { 213200000, P_PLL11, 5, 1, 1 },
 247 +       { }
 248 +};
 249 +
 250 +static struct clk_dyn_rcg ce5_h_clk_src = {
 251 +       .ns_reg[0] = 0x3c64,
 252 +       .ns_reg[1] = 0x3c68,
 253 +       .bank_reg = 0x3c60,
 254 +       .s[0] = {
 255 +               .src_sel_shift = 0,
 256 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 257 +       },
 258 +       .s[1] = {
 259 +               .src_sel_shift = 0,
 260 +               .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
 261 +       },
 262 +       .p[0] = {
 263 +               .pre_div_shift = 3,
 264 +               .pre_div_width = 4,
 265 +       },
 266 +       .p[1] = {
 267 +               .pre_div_shift = 3,
 268 +               .pre_div_width = 4,
 269 +       },
 270 +       .mux_sel_bit = 0,
 271 +       .freq_tbl = clk_tbl_ce5_h_clk,
 272 +       .clkr = {
 273 +               .enable_reg = 0x3c60,
 274 +               .enable_mask = BIT(1),
 275 +               .hw.init = &(struct clk_init_data){
 276 +                       .name = "ce5_h_clk_src",
 277 +                       .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
 278 +                       .num_parents = 6,
 279 +                       .ops = &clk_dyn_rcg_ops,
 280 +               },
 281 +       },
 282 +};
 283 +
 284 +static struct clk_branch ce5_h_clk = {
 285 +       .halt_reg = 0x3c20,
 286 +       .halt_bit = 11,
 287 +       .hwcg_reg = 0x3c6c,
 288 +       .hwcg_bit = 6,
 289 +       .clkr = {
 290 +               .enable_reg = 0x3c6c,
 291 +               .enable_mask = BIT(4),
 292 +               .hw.init = &(struct clk_init_data){
 293 +                       .name = "ce5_h_clk",
 294 +                       .parent_names = (const char *[]){
 295 +                               "ce5_h_clk_src",
 296 +                       },
 297 +                       .num_parents = 1,
 298 +                       .ops = &clk_branch_ops,
 299 +                       .flags = CLK_SET_RATE_PARENT,
 300 +               },
 301 +       },
 302 +};
 303 +
 304  static struct clk_regmap *gcc_ipq806x_clks[] = {
 305         [PLL0] = &pll0.clkr,
 306         [PLL0_VOTE] = &pll0_vote,
 307 @@ -2766,6 +3004,7 @@ static struct clk_regmap *gcc_ipq806x_cl
 308         [PLL4_VOTE] = &pll4_vote,
 309         [PLL8] = &pll8.clkr,
 310         [PLL8_VOTE] = &pll8_vote,
 311 +       [PLL11] = &pll11.clkr,
 312         [PLL14] = &pll14.clkr,
 313         [PLL14_VOTE] = &pll14_vote,
 314         [PLL18] = &pll18.clkr,
 315 @@ -2880,6 +3119,12 @@ static struct clk_regmap *gcc_ipq806x_cl
 316         [PLL9] = &hfpll0.clkr,
 317         [PLL10] = &hfpll1.clkr,
 318         [PLL12] = &hfpll_l2.clkr,
 319 +       [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
 320 +       [CE5_A_CLK] = &ce5_a_clk.clkr,
 321 +       [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
 322 +       [CE5_H_CLK] = &ce5_h_clk.clkr,
 323 +       [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
 324 +       [CE5_CORE_CLK] = &ce5_core_clk.clkr,
 325  };
 326
 327  static const struct qcom_reset_map gcc_ipq806x_resets[] = {
 328 @@ -3011,6 +3256,11 @@ static const struct qcom_reset_map gcc_i
 329         [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
 330         [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
 331         [GMAC_AHB_RESET] = { 0x3e24, 0 },
 332 +       [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
 333 +       [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
 334 +       [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
 335 +       [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
 336 +       [CRYPTO_AHB_RESET] = { 0x3e10, 0},
 337         [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
 338         [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
 339         [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
 340 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 341 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
 342 @@ -240,7 +240,7 @@
 343  #define PLL14                                  232
 344  #define PLL14_VOTE                             233
 345  #define PLL18                                  234
 346 -#define CE5_SRC                                        235
 347 +#define CE5_A_CLK                              235
 348  #define CE5_H_CLK                              236
 349  #define CE5_CORE_CLK                           237
 350  #define CE3_SLEEP_CLK                          238
 351 @@ -283,5 +283,8 @@
 352  #define EBI2_AON_CLK                           281
 353  #define NSSTCM_CLK_SRC                         282
 354  #define NSSTCM_CLK                             283
 355 +#define CE5_A_CLK_SRC                          285
 356 +#define CE5_H_CLK_SRC                          286
 357 +#define CE5_CORE_CLK_SRC                       287
 358
 359  #endif
 360 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 361 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
 362 @@ -163,5 +163,10 @@
 363  #define NSS_CAL_PRBS_RST_N_RESET                       154
 364  #define NSS_LCKDT_RST_N_RESET                          155
 365  #define NSS_SRDS_N_RESET                               156
 366 +#define CRYPTO_ENG1_RESET                              157
 367 +#define CRYPTO_ENG2_RESET                              158
 368 +#define CRYPTO_ENG3_RESET                              159
 369 +#define CRYPTO_ENG4_RESET                              160
 370 +#define CRYPTO_AHB_RESET                               161
 371
 372  #endif