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gemini: remove obsolete Kernel 5.4
[openwrt/openwrt.git] / target / linux / ipq806x / patches-5.4 / 083-ipq8064-dtsi-additions.patch
1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
3 @@ -8,6 +8,8 @@
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
9
10 / {
11 #address-cells = <1>;
12 @@ -28,6 +30,16 @@
13 next-level-cache = <&L2>;
14 qcom,acc = <&acc0>;
15 qcom,saw = <&saw0>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
26 };
27
28 cpu1: cpu@1 {
29 @@ -38,11 +50,476 @@
30 next-level-cache = <&L2>;
31 qcom,acc = <&acc1>;
32 qcom,saw = <&saw1>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
43 };
44
45 - L2: l2-cache {
46 - compatible = "cache";
47 - cache-level = <2>;
48 + idle-states {
49 + CPU_SPC: spc {
50 + compatible = "qcom,idle-state-spc", "arm,idle-state";
51 + status = "disabled";
52 + entry-latency-us = <400>;
53 + exit-latency-us = <900>;
54 + min-residency-us = <3000>;
55 + };
56 + };
57 + };
58 +
59 + opp_table_l2: opp_table_l2 {
60 + compatible = "operating-points-v2";
61 +
62 + opp-384000000 {
63 + opp-hz = /bits/ 64 <384000000>;
64 + opp-microvolt = <1100000>;
65 + clock-latency-ns = <100000>;
66 + opp-level = <0>;
67 + };
68 +
69 + opp-1000000000 {
70 + opp-hz = /bits/ 64 <1000000000>;
71 + opp-microvolt = <1100000>;
72 + clock-latency-ns = <100000>;
73 + opp-level = <1>;
74 + };
75 +
76 + opp-1200000000 {
77 + opp-hz = /bits/ 64 <1200000000>;
78 + opp-microvolt = <1150000>;
79 + clock-latency-ns = <100000>;
80 + opp-level = <2>;
81 + };
82 + };
83 +
84 + opp_table0: opp_table0 {
85 + compatible = "operating-points-v2-kryo-cpu";
86 + nvmem-cells = <&speedbin_efuse>;
87 +
88 + opp-384000000 {
89 + opp-hz = /bits/ 64 <384000000>;
90 + opp-microvolt-speed0-pvs0-v0 = <1000000>;
91 + opp-microvolt-speed0-pvs1-v0 = <925000>;
92 + opp-microvolt-speed0-pvs2-v0 = <875000>;
93 + opp-microvolt-speed0-pvs3-v0 = <800000>;
94 + opp-supported-hw = <0x1>;
95 + clock-latency-ns = <100000>;
96 + opp-level = <0>;
97 + };
98 +
99 + opp-600000000 {
100 + opp-hz = /bits/ 64 <600000000>;
101 + opp-microvolt-speed0-pvs0-v0 = <1050000>;
102 + opp-microvolt-speed0-pvs1-v0 = <975000>;
103 + opp-microvolt-speed0-pvs2-v0 = <925000>;
104 + opp-microvolt-speed0-pvs3-v0 = <850000>;
105 + opp-supported-hw = <0x1>;
106 + clock-latency-ns = <100000>;
107 + opp-level = <1>;
108 + };
109 +
110 + opp-800000000 {
111 + opp-hz = /bits/ 64 <800000000>;
112 + opp-microvolt-speed0-pvs0-v0 = <1100000>;
113 + opp-microvolt-speed0-pvs1-v0 = <1025000>;
114 + opp-microvolt-speed0-pvs2-v0 = <995000>;
115 + opp-microvolt-speed0-pvs3-v0 = <900000>;
116 + opp-supported-hw = <0x1>;
117 + clock-latency-ns = <100000>;
118 + opp-level = <1>;
119 + };
120 +
121 + opp-1000000000 {
122 + opp-hz = /bits/ 64 <1000000000>;
123 + opp-microvolt-speed0-pvs0-v0 = <1150000>;
124 + opp-microvolt-speed0-pvs1-v0 = <1075000>;
125 + opp-microvolt-speed0-pvs2-v0 = <1025000>;
126 + opp-microvolt-speed0-pvs3-v0 = <950000>;
127 + opp-supported-hw = <0x1>;
128 + clock-latency-ns = <100000>;
129 + opp-level = <1>;
130 + };
131 +
132 + opp-1200000000 {
133 + opp-hz = /bits/ 64 <1200000000>;
134 + opp-microvolt-speed0-pvs0-v0 = <1200000>;
135 + opp-microvolt-speed0-pvs1-v0 = <1125000>;
136 + opp-microvolt-speed0-pvs2-v0 = <1075000>;
137 + opp-microvolt-speed0-pvs3-v0 = <1000000>;
138 + opp-supported-hw = <0x1>;
139 + clock-latency-ns = <100000>;
140 + opp-level = <1>;
141 + };
142 +
143 + opp-1400000000 {
144 + opp-hz = /bits/ 64 <1400000000>;
145 + opp-microvolt-speed0-pvs0-v0 = <1250000>;
146 + opp-microvolt-speed0-pvs1-v0 = <1175000>;
147 + opp-microvolt-speed0-pvs2-v0 = <1125000>;
148 + opp-microvolt-speed0-pvs3-v0 = <1050000>;
149 + opp-supported-hw = <0x1>;
150 + clock-latency-ns = <100000>;
151 + opp-level = <2>;
152 + };
153 + };
154 +
155 + thermal-zones {
156 + tsens_tz_sensor0 {
157 + polling-delay-passive = <0>;
158 + polling-delay = <0>;
159 + thermal-sensors = <&tsens 0>;
160 +
161 + trips {
162 + cpu-critical-hi {
163 + temperature = <125000>;
164 + hysteresis = <2000>;
165 + type = "critical_high";
166 + };
167 +
168 + cpu-config-hi {
169 + temperature = <105000>;
170 + hysteresis = <2000>;
171 + type = "configurable_hi";
172 + };
173 +
174 + cpu-config-lo {
175 + temperature = <95000>;
176 + hysteresis = <2000>;
177 + type = "configurable_lo";
178 + };
179 +
180 + cpu-critical-low {
181 + temperature = <0>;
182 + hysteresis = <2000>;
183 + type = "critical_low";
184 + };
185 + };
186 + };
187 +
188 + tsens_tz_sensor1 {
189 + polling-delay-passive = <0>;
190 + polling-delay = <0>;
191 + thermal-sensors = <&tsens 1>;
192 +
193 + trips {
194 + cpu-critical-hi {
195 + temperature = <125000>;
196 + hysteresis = <2000>;
197 + type = "critical_high";
198 + };
199 +
200 + cpu-config-hi {
201 + temperature = <105000>;
202 + hysteresis = <2000>;
203 + type = "configurable_hi";
204 + };
205 +
206 + cpu-config-lo {
207 + temperature = <95000>;
208 + hysteresis = <2000>;
209 + type = "configurable_lo";
210 + };
211 +
212 + cpu-critical-low {
213 + temperature = <0>;
214 + hysteresis = <2000>;
215 + type = "critical_low";
216 + };
217 + };
218 + };
219 +
220 + tsens_tz_sensor2 {
221 + polling-delay-passive = <0>;
222 + polling-delay = <0>;
223 + thermal-sensors = <&tsens 2>;
224 +
225 + trips {
226 + cpu-critical-hi {
227 + temperature = <125000>;
228 + hysteresis = <2000>;
229 + type = "critical_high";
230 + };
231 +
232 + cpu-config-hi {
233 + temperature = <105000>;
234 + hysteresis = <2000>;
235 + type = "configurable_hi";
236 + };
237 +
238 + cpu-config-lo {
239 + temperature = <95000>;
240 + hysteresis = <2000>;
241 + type = "configurable_lo";
242 + };
243 +
244 + cpu-critical-low {
245 + temperature = <0>;
246 + hysteresis = <2000>;
247 + type = "critical_low";
248 + };
249 + };
250 + };
251 +
252 + tsens_tz_sensor3 {
253 + polling-delay-passive = <0>;
254 + polling-delay = <0>;
255 + thermal-sensors = <&tsens 3>;
256 +
257 + trips {
258 + cpu-critical-hi {
259 + temperature = <125000>;
260 + hysteresis = <2000>;
261 + type = "critical_high";
262 + };
263 +
264 + cpu-config-hi {
265 + temperature = <105000>;
266 + hysteresis = <2000>;
267 + type = "configurable_hi";
268 + };
269 +
270 + cpu-config-lo {
271 + temperature = <95000>;
272 + hysteresis = <2000>;
273 + type = "configurable_lo";
274 + };
275 +
276 + cpu-critical-low {
277 + temperature = <0>;
278 + hysteresis = <2000>;
279 + type = "critical_low";
280 + };
281 + };
282 + };
283 +
284 + tsens_tz_sensor4 {
285 + polling-delay-passive = <0>;
286 + polling-delay = <0>;
287 + thermal-sensors = <&tsens 4>;
288 +
289 + trips {
290 + cpu-critical-hi {
291 + temperature = <125000>;
292 + hysteresis = <2000>;
293 + type = "critical_high";
294 + };
295 +
296 + cpu-config-hi {
297 + temperature = <105000>;
298 + hysteresis = <2000>;
299 + type = "configurable_hi";
300 + };
301 +
302 + cpu-config-lo {
303 + temperature = <95000>;
304 + hysteresis = <2000>;
305 + type = "configurable_lo";
306 + };
307 +
308 + cpu-critical-low {
309 + temperature = <0>;
310 + hysteresis = <2000>;
311 + type = "critical_low";
312 + };
313 + };
314 + };
315 +
316 + tsens_tz_sensor5 {
317 + polling-delay-passive = <0>;
318 + polling-delay = <0>;
319 + thermal-sensors = <&tsens 5>;
320 +
321 + trips {
322 + cpu-critical-hi {
323 + temperature = <125000>;
324 + hysteresis = <2000>;
325 + type = "critical_high";
326 + };
327 +
328 + cpu-config-hi {
329 + temperature = <105000>;
330 + hysteresis = <2000>;
331 + type = "configurable_hi";
332 + };
333 +
334 + cpu-config-lo {
335 + temperature = <95000>;
336 + hysteresis = <2000>;
337 + type = "configurable_lo";
338 + };
339 +
340 + cpu-critical-low {
341 + temperature = <0>;
342 + hysteresis = <2000>;
343 + type = "critical_low";
344 + };
345 + };
346 + };
347 +
348 + tsens_tz_sensor6 {
349 + polling-delay-passive = <0>;
350 + polling-delay = <0>;
351 + thermal-sensors = <&tsens 6>;
352 +
353 + trips {
354 + cpu-critical-hi {
355 + temperature = <125000>;
356 + hysteresis = <2000>;
357 + type = "critical_high";
358 + };
359 +
360 + cpu-config-hi {
361 + temperature = <105000>;
362 + hysteresis = <2000>;
363 + type = "configurable_hi";
364 + };
365 +
366 + cpu-config-lo {
367 + temperature = <95000>;
368 + hysteresis = <2000>;
369 + type = "configurable_lo";
370 + };
371 +
372 + cpu-critical-low {
373 + temperature = <0>;
374 + hysteresis = <2000>;
375 + type = "critical_low";
376 + };
377 + };
378 + };
379 +
380 + tsens_tz_sensor7 {
381 + polling-delay-passive = <0>;
382 + polling-delay = <0>;
383 + thermal-sensors = <&tsens 7>;
384 +
385 + trips {
386 + cpu-critical-hi {
387 + temperature = <125000>;
388 + hysteresis = <2000>;
389 + type = "critical_high";
390 + };
391 +
392 + cpu-config-hi {
393 + temperature = <105000>;
394 + hysteresis = <2000>;
395 + type = "configurable_hi";
396 + };
397 +
398 + cpu-config-lo {
399 + temperature = <95000>;
400 + hysteresis = <2000>;
401 + type = "configurable_lo";
402 + };
403 +
404 + cpu-critical-low {
405 + temperature = <0>;
406 + hysteresis = <2000>;
407 + type = "critical_low";
408 + };
409 + };
410 + };
411 +
412 + tsens_tz_sensor8 {
413 + polling-delay-passive = <0>;
414 + polling-delay = <0>;
415 + thermal-sensors = <&tsens 8>;
416 +
417 + trips {
418 + cpu-critical-hi {
419 + temperature = <125000>;
420 + hysteresis = <2000>;
421 + type = "critical_high";
422 + };
423 +
424 + cpu-config-hi {
425 + temperature = <105000>;
426 + hysteresis = <2000>;
427 + type = "configurable_hi";
428 + };
429 +
430 + cpu-config-lo {
431 + temperature = <95000>;
432 + hysteresis = <2000>;
433 + type = "configurable_lo";
434 + };
435 +
436 + cpu-critical-low {
437 + temperature = <0>;
438 + hysteresis = <2000>;
439 + type = "critical_low";
440 + };
441 + };
442 + };
443 +
444 + tsens_tz_sensor9 {
445 + polling-delay-passive = <0>;
446 + polling-delay = <0>;
447 + thermal-sensors = <&tsens 9>;
448 +
449 + trips {
450 + cpu-critical-hi {
451 + temperature = <125000>;
452 + hysteresis = <2000>;
453 + type = "critical_high";
454 + };
455 +
456 + cpu-config-hi {
457 + temperature = <105000>;
458 + hysteresis = <2000>;
459 + type = "configurable_hi";
460 + };
461 +
462 + cpu-config-lo {
463 + temperature = <95000>;
464 + hysteresis = <2000>;
465 + type = "configurable_lo";
466 + };
467 +
468 + cpu-critical-low {
469 + temperature = <0>;
470 + hysteresis = <2000>;
471 + type = "critical_low";
472 + };
473 + };
474 + };
475 +
476 + tsens_tz_sensor10 {
477 + polling-delay-passive = <0>;
478 + polling-delay = <0>;
479 + thermal-sensors = <&tsens 10>;
480 +
481 + trips {
482 + cpu-critical-hi {
483 + temperature = <125000>;
484 + hysteresis = <2000>;
485 + type = "critical_high";
486 + };
487 +
488 + cpu-config-hi {
489 + temperature = <105000>;
490 + hysteresis = <2000>;
491 + type = "configurable_hi";
492 + };
493 +
494 + cpu-config-lo {
495 + temperature = <95000>;
496 + hysteresis = <2000>;
497 + type = "configurable_lo";
498 + };
499 +
500 + cpu-critical-low {
501 + temperature = <0>;
502 + hysteresis = <2000>;
503 + type = "critical_low";
504 + };
505 + };
506 };
507 };
508
509 @@ -93,6 +570,15 @@
510 };
511 };
512
513 + fab-scaling {
514 + compatible = "qcom,fab-scaling";
515 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
516 + clock-names = "apps-fab-clk", "ddr-fab-clk";
517 + fab_freq_high = <533000000>;
518 + fab_freq_nominal = <400000000>;
519 + cpu_freq_threshold = <1000000000>;
520 + };
521 +
522 firmware {
523 scm {
524 compatible = "qcom,scm-ipq806x", "qcom,scm";
525 @@ -120,6 +606,95 @@
526 reg-names = "lpass-lpaif";
527 };
528
529 + L2: l2-cache {
530 + compatible = "qcom,krait-cache", "cache";
531 + cache-level = <2>;
532 + qcom,saw = <&saw_l2>;
533 +
534 + clocks = <&kraitcc 4>;
535 + clock-names = "l2";
536 + l2-supply = <&smb208_s1a>;
537 + operating-points-v2 = <&opp_table_l2>;
538 + };
539 +
540 + qfprom: qfprom@700000 {
541 + compatible = "qcom,qfprom", "syscon";
542 + reg = <0x700000 0x1000>;
543 + #address-cells = <1>;
544 + #size-cells = <1>;
545 + status = "okay";
546 + tsens_calib: calib@400 {
547 + reg = <0x400 0xb>;
548 + };
549 + tsens_backup: backup@410 {
550 + reg = <0x410 0xb>;
551 + };
552 + speedbin_efuse: speedbin@0c0 {
553 + reg = <0x0c0 0x4>;
554 + };
555 + };
556 +
557 + rpm: rpm@108000 {
558 + compatible = "qcom,rpm-ipq8064";
559 + reg = <0x108000 0x1000>;
560 + qcom,ipc = <&l2cc 0x8 2>;
561 +
562 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
563 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
564 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
565 + interrupt-names = "ack", "err", "wakeup";
566 +
567 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
568 + clock-names = "ram";
569 +
570 + #address-cells = <1>;
571 + #size-cells = <0>;
572 +
573 + rpmcc: clock-controller {
574 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
575 + #clock-cells = <1>;
576 + };
577 +
578 + regulators {
579 + compatible = "qcom,rpm-smb208-regulators";
580 +
581 + smb208_s1a: s1a {
582 + regulator-min-microvolt = <1050000>;
583 + regulator-max-microvolt = <1150000>;
584 +
585 + qcom,switch-mode-frequency = <1200000>;
586 + };
587 +
588 + smb208_s1b: s1b {
589 + regulator-min-microvolt = <1050000>;
590 + regulator-max-microvolt = <1150000>;
591 +
592 + qcom,switch-mode-frequency = <1200000>;
593 + };
594 +
595 + smb208_s2a: s2a {
596 + regulator-min-microvolt = < 800000>;
597 + regulator-max-microvolt = <1250000>;
598 +
599 + qcom,switch-mode-frequency = <1200000>;
600 + };
601 +
602 + smb208_s2b: s2b {
603 + regulator-min-microvolt = < 800000>;
604 + regulator-max-microvolt = <1250000>;
605 +
606 + qcom,switch-mode-frequency = <1200000>;
607 + };
608 + };
609 + };
610 +
611 + rng@1a500000 {
612 + compatible = "qcom,prng";
613 + reg = <0x1a500000 0x200>;
614 + clocks = <&gcc PRNG_CLK>;
615 + clock-names = "core";
616 + };
617 +
618 qcom_pinmux: pinmux@800000 {
619 compatible = "qcom,ipq8064-pinctrl";
620 reg = <0x800000 0x4000>;
621 @@ -159,6 +734,15 @@
622 };
623 };
624
625 + i2c4_pins: i2c4_pinmux {
626 + mux {
627 + pins = "gpio12", "gpio13";
628 + function = "gsbi4";
629 + drive-strength = <12>;
630 + bias-disable;
631 + };
632 + };
633 +
634 spi_pins: spi_pins {
635 mux {
636 pins = "gpio18", "gpio19", "gpio21";
637 @@ -168,6 +752,53 @@
638 };
639 };
640
641 + nand_pins: nand_pins {
642 + disable {
643 + pins = "gpio34", "gpio35", "gpio36",
644 + "gpio37", "gpio38";
645 + function = "nand";
646 + drive-strength = <10>;
647 + bias-disable;
648 + };
649 +
650 + pullups {
651 + pins = "gpio39";
652 + function = "nand";
653 + drive-strength = <10>;
654 + bias-pull-up;
655 + };
656 +
657 + hold {
658 + pins = "gpio40", "gpio41", "gpio42",
659 + "gpio43", "gpio44", "gpio45",
660 + "gpio46", "gpio47";
661 + function = "nand";
662 + drive-strength = <10>;
663 + bias-bus-hold;
664 + };
665 + };
666 +
667 + mdio0_pins: mdio0_pins {
668 + mux {
669 + pins = "gpio0", "gpio1";
670 + function = "mdio";
671 + drive-strength = <8>;
672 + bias-disable;
673 + };
674 + };
675 +
676 + rgmii2_pins: rgmii2_pins {
677 + mux {
678 + pins = "gpio27", "gpio28", "gpio29",
679 + "gpio30", "gpio31", "gpio32",
680 + "gpio51", "gpio52", "gpio59",
681 + "gpio60", "gpio61", "gpio62";
682 + function = "rgmii2";
683 + drive-strength = <8>;
684 + bias-disable;
685 + };
686 + };
687 +
688 leds_pins: leds_pins {
689 mux {
690 pins = "gpio7", "gpio8", "gpio9",
691 @@ -229,6 +860,17 @@
692 clock-output-names = "acpu1_aux";
693 };
694
695 + l2cc: clock-controller@2011000 {
696 + compatible = "qcom,kpss-gcc", "syscon";
697 + reg = <0x2011000 0x1000>;
698 + clock-output-names = "acpu_l2_aux";
699 + };
700 +
701 + kraitcc: clock-controller {
702 + compatible = "qcom,krait-cc-v1";
703 + #clock-cells = <1>;
704 + };
705 +
706 saw0: regulator@2089000 {
707 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
708 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
709 @@ -241,6 +883,17 @@
710 regulator;
711 };
712
713 + saw_l2: regulator@02012000 {
714 + compatible = "qcom,saw2", "syscon";
715 + reg = <0x02012000 0x1000>;
716 + regulator;
717 + };
718 +
719 + sic_non_secure: sic-non-secure@12100000 {
720 + compatible = "syscon";
721 + reg = <0x12100000 0x10000>;
722 + };
723 +
724 gsbi2: gsbi@12480000 {
725 compatible = "qcom,gsbi-v1.0.0";
726 cell-index = <2>;
727 @@ -436,6 +1089,15 @@
728 #power-domain-cells = <1>;
729 };
730
731 + tsens: thermal-sensor@900000 {
732 + compatible = "qcom,ipq8064-tsens";
733 + reg = <0x900000 0x3680>;
734 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
735 + nvmem-cell-names = "calib", "calib_backup";
736 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
737 + #thermal-sensor-cells = <1>;
738 + };
739 +
740 tcsr: syscon@1a400000 {
741 compatible = "qcom,tcsr-ipq8064", "syscon";
742 reg = <0x1a400000 0x100>;
743 @@ -448,6 +1110,95 @@
744 #reset-cells = <1>;
745 };
746
747 + sfpb_mutex_block: syscon@1200600 {
748 + compatible = "syscon";
749 + reg = <0x01200600 0x100>;
750 + };
751 +
752 + hs_phy_0: hs_phy_0 {
753 + compatible = "qcom,ipq806x-usb-phy-hs";
754 + reg = <0x110f8800 0x30>;
755 + clocks = <&gcc USB30_0_UTMI_CLK>;
756 + clock-names = "ref";
757 + #phy-cells = <0>;
758 + };
759 +
760 + ss_phy_0: ss_phy_0 {
761 + compatible = "qcom,ipq806x-usb-phy-ss";
762 + reg = <0x110f8830 0x30>;
763 + clocks = <&gcc USB30_0_MASTER_CLK>;
764 + clock-names = "ref";
765 + #phy-cells = <0>;
766 + };
767 +
768 + usb3_0: usb3@110f8800 {
769 + compatible = "qcom,dwc3", "syscon";
770 + #address-cells = <1>;
771 + #size-cells = <1>;
772 + reg = <0x110f8800 0x8000>;
773 + clocks = <&gcc USB30_0_MASTER_CLK>;
774 + clock-names = "core";
775 +
776 + ranges;
777 +
778 + resets = <&gcc USB30_0_MASTER_RESET>;
779 + reset-names = "master";
780 +
781 + status = "disabled";
782 +
783 + dwc3_0: dwc3@11000000 {
784 + compatible = "snps,dwc3";
785 + reg = <0x11000000 0xcd00>;
786 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
787 + phys = <&hs_phy_0>, <&ss_phy_0>;
788 + phy-names = "usb2-phy", "usb3-phy";
789 + dr_mode = "host";
790 + snps,dis_u3_susphy_quirk;
791 + };
792 + };
793 +
794 + hs_phy_1: hs_phy_1 {
795 + compatible = "qcom,ipq806x-usb-phy-hs";
796 + reg = <0x100f8800 0x30>;
797 + clocks = <&gcc USB30_1_UTMI_CLK>;
798 + clock-names = "ref";
799 + #phy-cells = <0>;
800 + };
801 +
802 + ss_phy_1: ss_phy_1 {
803 + compatible = "qcom,ipq806x-usb-phy-ss";
804 + reg = <0x100f8830 0x30>;
805 + clocks = <&gcc USB30_1_MASTER_CLK>;
806 + clock-names = "ref";
807 + #phy-cells = <0>;
808 + };
809 +
810 + usb3_1: usb3@100f8800 {
811 + compatible = "qcom,dwc3", "syscon";
812 + #address-cells = <1>;
813 + #size-cells = <1>;
814 + reg = <0x100f8800 0x8000>;
815 + clocks = <&gcc USB30_1_MASTER_CLK>;
816 + clock-names = "core";
817 +
818 + ranges;
819 +
820 + resets = <&gcc USB30_1_MASTER_RESET>;
821 + reset-names = "master";
822 +
823 + status = "disabled";
824 +
825 + dwc3_1: dwc3@10000000 {
826 + compatible = "snps,dwc3";
827 + reg = <0x10000000 0xcd00>;
828 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
829 + phys = <&hs_phy_1>, <&ss_phy_1>;
830 + phy-names = "usb2-phy", "usb3-phy";
831 + dr_mode = "host";
832 + snps,dis_u3_susphy_quirk;
833 + };
834 + };
835 +
836 pcie0: pci@1b500000 {
837 compatible = "qcom,pcie-ipq8064";
838 reg = <0x1b500000 0x1000
839 @@ -601,6 +1352,167 @@
840 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
841 };
842
843 + adm_dma: dma@18300000 {
844 + compatible = "qcom,adm";
845 + reg = <0x18300000 0x100000>;
846 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
847 + #dma-cells = <1>;
848 +
849 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
850 + clock-names = "core", "iface";
851 +
852 + resets = <&gcc ADM0_RESET>,
853 + <&gcc ADM0_PBUS_RESET>,
854 + <&gcc ADM0_C0_RESET>,
855 + <&gcc ADM0_C1_RESET>,
856 + <&gcc ADM0_C2_RESET>;
857 + reset-names = "clk", "pbus", "c0", "c1", "c2";
858 + qcom,ee = <0>;
859 +
860 + status = "disabled";
861 + };
862 +
863 + nand_controller: nand-controller@1ac00000 {
864 + compatible = "qcom,ipq806x-nand";
865 + reg = <0x1ac00000 0x800>;
866 +
867 + clocks = <&gcc EBI2_CLK>,
868 + <&gcc EBI2_AON_CLK>;
869 + clock-names = "core", "aon";
870 +
871 + dmas = <&adm_dma 3>;
872 + dma-names = "rxtx";
873 + qcom,cmd-crci = <15>;
874 + qcom,data-crci = <3>;
875 +
876 + status = "disabled";
877 +
878 + #address-cells = <1>;
879 + #size-cells = <0>;
880 + };
881 +
882 + nss_common: syscon@03000000 {
883 + compatible = "syscon";
884 + reg = <0x03000000 0x0000FFFF>;
885 + };
886 +
887 + qsgmii_csr: syscon@1bb00000 {
888 + compatible = "syscon";
889 + reg = <0x1bb00000 0x000001FF>;
890 + };
891 +
892 + stmmac_axi_setup: stmmac-axi-config {
893 + snps,wr_osr_lmt = <7>;
894 + snps,rd_osr_lmt = <7>;
895 + snps,blen = <16 0 0 0 0 0 0>;
896 + };
897 +
898 + mdio0: mdio@37000000 {
899 + #address-cells = <1>;
900 + #size-cells = <0>;
901 +
902 + compatible = "qcom,ipq8064-mdio", "syscon";
903 + reg = <0x37000000 0x200000>;
904 + resets = <&gcc GMAC_CORE1_RESET>;
905 + reset-names = "stmmaceth";
906 + clocks = <&gcc GMAC_CORE1_CLK>;
907 + clock-names = "stmmaceth";
908 +
909 + status = "disabled";
910 + };
911 +
912 + gmac0: ethernet@37000000 {
913 + device_type = "network";
914 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
915 + reg = <0x37000000 0x200000>;
916 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
917 + interrupt-names = "macirq";
918 +
919 + snps,axi-config = <&stmmac_axi_setup>;
920 + snps,pbl = <32>;
921 + snps,aal = <1>;
922 +
923 + qcom,nss-common = <&nss_common>;
924 + qcom,qsgmii-csr = <&qsgmii_csr>;
925 +
926 + clocks = <&gcc GMAC_CORE1_CLK>;
927 + clock-names = "stmmaceth";
928 +
929 + resets = <&gcc GMAC_CORE1_RESET>;
930 + reset-names = "stmmaceth";
931 +
932 + status = "disabled";
933 + };
934 +
935 + gmac1: ethernet@37200000 {
936 + device_type = "network";
937 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
938 + reg = <0x37200000 0x200000>;
939 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
940 + interrupt-names = "macirq";
941 +
942 + snps,axi-config = <&stmmac_axi_setup>;
943 + snps,pbl = <32>;
944 + snps,aal = <1>;
945 +
946 + qcom,nss-common = <&nss_common>;
947 + qcom,qsgmii-csr = <&qsgmii_csr>;
948 +
949 + clocks = <&gcc GMAC_CORE2_CLK>;
950 + clock-names = "stmmaceth";
951 +
952 + resets = <&gcc GMAC_CORE2_RESET>;
953 + reset-names = "stmmaceth";
954 +
955 + status = "disabled";
956 + };
957 +
958 + gmac2: ethernet@37400000 {
959 + device_type = "network";
960 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
961 + reg = <0x37400000 0x200000>;
962 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
963 + interrupt-names = "macirq";
964 +
965 + snps,axi-config = <&stmmac_axi_setup>;
966 + snps,pbl = <32>;
967 + snps,aal = <1>;
968 +
969 + qcom,nss-common = <&nss_common>;
970 + qcom,qsgmii-csr = <&qsgmii_csr>;
971 +
972 + clocks = <&gcc GMAC_CORE3_CLK>;
973 + clock-names = "stmmaceth";
974 +
975 + resets = <&gcc GMAC_CORE3_RESET>;
976 + reset-names = "stmmaceth";
977 +
978 + status = "disabled";
979 + };
980 +
981 + gmac3: ethernet@37600000 {
982 + device_type = "network";
983 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
984 + reg = <0x37600000 0x200000>;
985 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
986 + interrupt-names = "macirq";
987 +
988 + snps,axi-config = <&stmmac_axi_setup>;
989 + snps,pbl = <32>;
990 + snps,aal = <1>;
991 +
992 + qcom,nss-common = <&nss_common>;
993 + qcom,qsgmii-csr = <&qsgmii_csr>;
994 +
995 + clocks = <&gcc GMAC_CORE4_CLK>;
996 + clock-names = "stmmaceth";
997 +
998 + resets = <&gcc GMAC_CORE4_RESET>;
999 + reset-names = "stmmaceth";
1000 +
1001 + status = "disabled";
1002 + };
1003 +
1004 vsdcc_fixed: vsdcc-regulator {
1005 compatible = "regulator-fixed";
1006 regulator-name = "SDCC Power";
1007 @@ -676,4 +1588,17 @@
1008 };
1009 };
1010 };
1011 +
1012 + sfpb_mutex: sfpb-mutex {
1013 + compatible = "qcom,sfpb-mutex";
1014 + syscon = <&sfpb_mutex_block 4 4>;
1015 +
1016 + #hwlock-cells = <1>;
1017 + };
1018 +
1019 + smem {
1020 + compatible = "qcom,smem";
1021 + memory-region = <&smem>;
1022 + hwlocks = <&sfpb_mutex 3>;
1023 + };
1024 };
OpenWrt Source Repository