dnsmasq: add config option for connmark DNS filtering
[openwrt/staging/mkresin.git] / target / linux / lantiq / files / arch / mips / boot / dts / lantiq / vr9_tplink_vr200.dtsi
1 #include "vr9.dtsi"
2
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
5
6 / {
7 aliases {
8 led-boot = &led_power;
9 led-failsafe = &led_power;
10 led-running = &led_power;
11 led-upgrade = &led_power;
12
13 led-dsl = &led_dsl;
14 led-internet = &led_internet;
15 led-wifi = &led_wlan5g;
16 };
17
18 memory@0 {
19 device_type = "memory";
20 reg = <0x0 0x7f00000>;
21 };
22
23 keys: keys {
24 compatible = "gpio-keys-polled";
25 poll-interval = <100>;
26
27 reset {
28 label = "reset";
29 gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
30 linux,code = <KEY_RESTART>;
31 };
32
33 wifi {
34 label = "wifi";
35 gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
36 linux,code = <KEY_RFKILL>;
37 linux,input-type = <EV_SW>;
38 };
39
40 wps {
41 label = "wps";
42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
43 linux,code = <KEY_WPS_BUTTON>;
44 };
45 };
46
47 leds: leds {
48 compatible = "gpio-leds";
49
50 led_power: power {
51 label = "blue:power";
52 gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
53 default-state = "keep";
54 };
55
56 led_dsl: dsl {
57 label = "blue:dsl";
58 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
59 };
60
61 led_internet: internet {
62 label = "blue:internet";
63 gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
64 };
65
66 usb {
67 label = "blue:usb";
68 gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
69 trigger-sources = <&ehci_port1>, <&ehci_port2>;
70 linux,default-trigger = "usbport";
71 };
72
73 eth {
74 label = "blue:lan";
75 gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
76 };
77
78 wlan {
79 label = "blue:wlan";
80 gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
81 };
82
83 led_wlan5g: wifi {
84 label = "blue:wlan5g";
85 gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
86 };
87 };
88
89 usb_vbus: regulator-usb-vbus {
90 compatible = "regulator-fixed";
91
92 regulator-name = "USB_VBUS";
93
94 regulator-min-microvolt = <5000000>;
95 regulator-max-microvolt = <5000000>;
96
97 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
98 enable-active-high;
99 };
100 };
101
102 &eth0 {
103 pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
104 pinctrl-names = "default";
105
106 lan: interface@0 {
107 compatible = "lantiq,xrx200-pdi";
108 #address-cells = <1>;
109 #size-cells = <0>;
110 reg = <0>;
111 mtd-mac-address = <&romfile 0xf100>;
112 lantiq,switch;
113
114 ethernet@0 {
115 compatible = "lantiq,xrx200-pdi-port";
116 reg = <0>;
117 phy-mode = "rgmii";
118 phy-handle = <&phy0>;
119 // gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
120 };
121 ethernet@2 {
122 compatible = "lantiq,xrx200-pdi-port";
123 reg = <2>;
124 phy-mode = "gmii";
125 phy-handle = <&phy11>;
126 };
127 ethernet@4 {
128 compatible = "lantiq,xrx200-pdi-port";
129 reg = <4>;
130 phy-mode = "gmii";
131 phy-handle = <&phy13>;
132 };
133 ethernet@5 {
134 compatible = "lantiq,xrx200-pdi-port";
135 reg = <5>;
136 phy-mode = "rgmii";
137 phy-handle = <&phy5>;
138 };
139 };
140
141 mdio {
142 #address-cells = <1>;
143 #size-cells = <0>;
144 compatible = "lantiq,xrx200-mdio";
145
146 phy0: ethernet-phy@0 {
147 reg = <0x0>;
148 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
149 };
150 phy5: ethernet-phy@5 {
151 reg = <0x5>;
152 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
153 };
154 phy11: ethernet-phy@11 {
155 reg = <0x11>;
156 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
157 };
158 phy13: ethernet-phy@13 {
159 reg = <0x13>;
160 compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
161 };
162 };
163 };
164
165 &gphy0 {
166 lantiq,gphy-mode = <GPHY_MODE_GE>;
167 };
168
169 &gphy1 {
170 lantiq,gphy-mode = <GPHY_MODE_GE>;
171 };
172
173 &gpio {
174 pinctrl-names = "default";
175 pinctrl-0 = <&state_default>;
176
177 state_default: pinmux {
178 phy-rst {
179 lantiq,pins = "io42";
180 lantiq,pull = <0>;
181 lantiq,open-drain = <0>;
182 lantiq,output = <1>;
183 };
184 pcie-rst {
185 lantiq,pins = "io38";
186 lantiq,pull = <0>;
187 lantiq,output = <1>;
188 };
189 };
190 };
191
192 &pcie0 {
193 pcie@0 {
194 reg = <0 0 0 0 0>;
195 #interrupt-cells = <1>;
196 #size-cells = <2>;
197 #address-cells = <3>;
198 device_type = "pci";
199
200 wifi@0,0 {
201 reg = <0 0 0 0 0>;
202 mediatek,mtd-eeprom = <&radio 0x0000>;
203 big-endian;
204 ieee80211-freq-limit = <5000000 6000000>;
205 mtd-mac-address = <&romfile 0xf100>;
206 mtd-mac-address-increment = <2>;
207 };
208 };
209 };
210
211 &pci0 {
212 status = "okay";
213 gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
214 };
215
216 &spi {
217 status = "okay";
218
219 flash@4 {
220 compatible = "jedec,spi-nor";
221 reg = <4>;
222 spi-max-frequency = <33250000>;
223 m25p,fast-read;
224
225 partitions {
226 compatible = "fixed-partitions";
227 #address-cells = <1>;
228 #size-cells = <1>;
229
230 partition@0 {
231 reg = <0x0 0x20000>;
232 label = "u-boot";
233 read-only;
234 };
235
236 partition@20000 {
237 reg = <0x20000 0xf90000>;
238 label = "firmware";
239 };
240
241 partition@fb0000 {
242 reg = <0xfb0000 0x10000>;
243 label = "radioDECT";
244 read-only;
245 };
246
247 partition@fc0000 {
248 reg = <0xfc0000 0x10000>;
249 label = "config";
250 read-only;
251 };
252
253 romfile: partition@fd0000 {
254 reg = <0xfd0000 0x10000>;
255 label = "romfile";
256 read-only;
257 };
258
259 partition@fe0000 {
260 reg = <0xfe0000 0x10000>;
261 label = "rom";
262 read-only;
263 };
264
265 radio: partition@ff0000 {
266 reg = <0xff0000 0x10000>;
267 label = "radio";
268 read-only;
269 };
270 };
271 };
272 };
273
274 &usb_phy0 {
275 status = "okay";
276 };
277
278 &usb_phy1 {
279 status = "okay";
280 };
281
282 &usb0 {
283 status = "okay";
284 vbus-supply = <&usb_vbus>;
285 };
286
287 &usb1 {
288 status = "okay";
289 vbus-supply = <&usb_vbus>;
290 };