target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         aliases {
   8                 led-boot = &led_power;
   9                 led-failsafe = &led_power;
  10                 led-running = &led_power;
  11                 led-upgrade = &led_power;
  12
  13                 led-dsl = &led_dsl;
  14                 led-internet = &led_internet;
  15                 led-wifi = &led_wlan5g;
  16         };
  17
  18         memory@0 {
  19                 device_type = "memory";
  20                 reg = <0x0 0x7f00000>;
  21         };
  22
  23         keys: keys {
  24                 compatible = "gpio-keys-polled";
  25                 poll-interval = <100>;
  26
  27                 reset {
  28                         label = "reset";
  29                         gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
  30                         linux,code = <KEY_RESTART>;
  31                 };
  32
  33                 wifi {
  34                         label = "wifi";
  35                         gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
  36                         linux,code = <KEY_RFKILL>;
  37                         linux,input-type = <EV_SW>;
  38                 };
  39
  40                 wps {
  41                         label = "wps";
  42                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  43                         linux,code = <KEY_WPS_BUTTON>;
  44                 };
  45         };
  46
  47         leds: leds {
  48                 compatible = "gpio-leds";
  49
  50                 led_power: power {
  51                         label = "blue:power";
  52                         gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
  53                         default-state = "keep";
  54                 };
  55
  56                 led_dsl: dsl {
  57                         label = "blue:dsl";
  58                         gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
  59                 };
  60
  61                 led_internet: internet {
  62                         label = "blue:internet";
  63                         gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
  64                 };
  65
  66                 usb {
  67                         label = "blue:usb";
  68                         gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
  69                         trigger-sources = <&ehci_port1>, <&ehci_port2>;
  70                         linux,default-trigger = "usbport";
  71                 };
  72
  73                 eth {
  74                         label = "blue:lan";
  75                         gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
  76                 };
  77
  78                 wlan {
  79                         label = "blue:wlan";
  80                         gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
  81                 };
  82
  83                 led_wlan5g: wifi {
  84                         label = "blue:wlan5g";
  85                         gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
  86                 };
  87         };
  88
  89         usb_vbus: regulator-usb-vbus {
  90                 compatible = "regulator-fixed";
  91
  92                 regulator-name = "USB_VBUS";
  93
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96
  97                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  98                 enable-active-high;
  99         };
 100 };
 101
 102 &eth0 {
 103         nvmem-cells = <&macaddr_romfile_f100 0>;
 104         nvmem-cell-names = "mac-address";
 105 };
 106
 107 &gphy0 {
 108         lantiq,gphy-mode = <GPHY_MODE_GE>;
 109 };
 110
 111 &gphy1 {
 112         lantiq,gphy-mode = <GPHY_MODE_GE>;
 113 };
 114
 115 &gpio {
 116         pinctrl-names = "default";
 117         pinctrl-0 = <&state_default>;
 118
 119         state_default: pinmux {
 120                 phy-rst {
 121                         lantiq,pins = "io42";
 122                         lantiq,pull = <0>;
 123                         lantiq,open-drain = <0>;
 124                         lantiq,output = <1>;
 125                 };
 126                 pcie-rst {
 127                         lantiq,pins = "io38";
 128                         lantiq,pull = <0>;
 129                         lantiq,output = <1>;
 130                 };
 131         };
 132 };
 133
 134 &gswip {
 135         pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
 136         pinctrl-names = "default";
 137 };
 138
 139 &gswip_mdio {
 140         phy0: ethernet-phy@0 {
 141                 reg = <0x0>;
 142                 // reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 143         };
 144         phy5: ethernet-phy@5 {
 145                 reg = <0x5>;
 146         };
 147         phy11: ethernet-phy@11 {
 148                 reg = <0x11>;
 149         };
 150         phy13: ethernet-phy@13 {
 151                 reg = <0x13>;
 152         };
 153 };
 154
 155 &gswip_ports {
 156         port@0 {
 157                 reg = <0>;
 158                 label = "lan3";
 159                 phy-mode = "rgmii";
 160                 phy-handle = <&phy0>;
 161         };
 162         port@2 {
 163                 reg = <2>;
 164                 label = "lan2";
 165                 phy-mode = "internal";
 166                 phy-handle = <&phy11>;
 167         };
 168         port@4 {
 169                 reg = <4>;
 170                 label = "lan1";
 171                 phy-mode = "internal";
 172                 phy-handle = <&phy13>;
 173         };
 174         port@5 {
 175                 reg = <5>;
 176                 label = "lan4";
 177                 phy-mode = "rgmii";
 178                 phy-handle = <&phy5>;
 179         };
 180 };
 181
 182 &pcie0 {
 183         pcie@0 {
 184                 reg = <0 0 0 0 0>;
 185                 #interrupt-cells = <1>;
 186                 #size-cells = <2>;
 187                 #address-cells = <3>;
 188                 device_type = "pci";
 189
 190                 wifi@0,0 {
 191                         reg = <0 0 0 0 0>;
 192                         mediatek,mtd-eeprom = <&radio 0x0000>;
 193                         big-endian;
 194                         ieee80211-freq-limit = <5000000 6000000>;
 195                         nvmem-cells = <&macaddr_romfile_f100 2>;
 196                         nvmem-cell-names = "mac-address";
 197                 };
 198         };
 199 };
 200
 201 &pci0 {
 202         status = "okay";
 203         gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 204 };
 205
 206 &spi {
 207         status = "okay";
 208
 209         flash@4 {
 210                 compatible = "jedec,spi-nor";
 211                 reg = <4>;
 212                 spi-max-frequency = <33250000>;
 213                 m25p,fast-read;
 214
 215                 partitions {
 216                         compatible = "fixed-partitions";
 217                         #address-cells = <1>;
 218                         #size-cells = <1>;
 219
 220                         partition@0 {
 221                                 reg = <0x0 0x20000>;
 222                                 label = "u-boot";
 223                                 read-only;
 224                         };
 225
 226                         partition@20000 {
 227                                 reg = <0x20000 0xf90000>;
 228                                 label = "firmware";
 229                         };
 230
 231                         partition@fb0000 {
 232                                 reg = <0xfb0000 0x10000>;
 233                                 label = "radioDECT";
 234                                 read-only;
 235                         };
 236
 237                         partition@fc0000 {
 238                                 reg = <0xfc0000 0x10000>;
 239                                 label = "config";
 240                                 read-only;
 241                         };
 242
 243                         romfile: partition@fd0000 {
 244                                 reg = <0xfd0000 0x10000>;
 245                                 label = "romfile";
 246                                 read-only;
 247
 248                                 nvmem-layout {
 249                                         compatible = "fixed-layout";
 250                                         #address-cells = <1>;
 251                                         #size-cells = <1>;
 252
 253                                         macaddr_romfile_f100: macaddr@f100 {
 254                                                 compatible = "mac-base";
 255                                                 reg = <0xf100 0x6>;
 256                                                 #nvmem-cell-cells = <1>;
 257                                         };
 258                                 };
 259                         };
 260
 261                         partition@fe0000 {
 262                                 reg = <0xfe0000 0x10000>;
 263                                 label = "rom";
 264                                 read-only;
 265                         };
 266
 267                         radio: partition@ff0000 {
 268                                 reg = <0xff0000 0x10000>;
 269                                 label = "radio";
 270                                 read-only;
 271                         };
 272                 };
 273         };
 274 };
 275
 276 &usb_phy0 {
 277         status = "okay";
 278 };
 279
 280 &usb_phy1 {
 281         status = "okay";
 282 };
 283
 284 &usb0 {
 285         status = "okay";
 286         vbus-supply = <&usb_vbus>;
 287 };
 288
 289 &usb1 {
 290         status = "okay";
 291         vbus-supply = <&usb_vbus>;
 292 };