target/linux/lantiq/files/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/leds/common.h>
   5 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   6
   7 / {
   8         aliases {
   9                 led-boot = &led_power;
  10                 led-failsafe = &led_power;
  11                 led-running = &led_power;
  12                 led-upgrade = &led_power;
  13
  14                 led-dsl = &led_dsl;
  15                 led-internet = &led_internet;
  16                 led-wifi = &led_wlan5g;
  17         };
  18
  19         memory@0 {
  20                 device_type = "memory";
  21                 reg = <0x0 0x7f00000>;
  22         };
  23
  24         keys: keys {
  25                 compatible = "gpio-keys-polled";
  26                 poll-interval = <100>;
  27
  28                 reset {
  29                         label = "reset";
  30                         gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
  31                         linux,code = <KEY_RESTART>;
  32                 };
  33
  34                 wifi {
  35                         label = "wifi";
  36                         gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
  37                         linux,code = <KEY_RFKILL>;
  38                         linux,input-type = <EV_SW>;
  39                 };
  40
  41                 wps {
  42                         label = "wps";
  43                         gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
  44                         linux,code = <KEY_WPS_BUTTON>;
  45                 };
  46         };
  47
  48         leds: leds {
  49                 compatible = "gpio-leds";
  50
  51                 led_power: power {
  52                         function = LED_FUNCTION_POWER;
  53                         color = <LED_COLOR_ID_BLUE>;
  54                         gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
  55                         default-state = "keep";
  56                 };
  57
  58                 led_dsl: dsl {
  59                         label = "blue:dsl";
  60                         gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
  61                 };
  62
  63                 led_internet: internet {
  64                         label = "blue:internet";
  65                         gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
  66                 };
  67
  68                 usb {
  69                         function = LED_FUNCTION_USB;
  70                         color = <LED_COLOR_ID_BLUE>;
  71                         gpios = <&gpio 25 GPIO_ACTIVE_LOW>;
  72                         trigger-sources = <&ehci_port1>, <&ehci_port2>;
  73                         linux,default-trigger = "usbport";
  74                 };
  75
  76                 eth {
  77                         function = LED_FUNCTION_LAN;
  78                         color = <LED_COLOR_ID_BLUE>;
  79                         gpios = <&gpio 40 GPIO_ACTIVE_LOW>;
  80                 };
  81
  82                 wlan {
  83                         function = LED_FUNCTION_WLAN;
  84                         color = <LED_COLOR_ID_BLUE>;
  85                         gpios = <&gpio 24 GPIO_ACTIVE_LOW>;
  86                 };
  87
  88                 led_wlan5g: wifi {
  89                         label = "blue:wlan5g";
  90                         gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
  91                 };
  92         };
  93
  94         usb_vbus: regulator-usb-vbus {
  95                 compatible = "regulator-fixed";
  96
  97                 regulator-name = "USB_VBUS";
  98
  99                 regulator-min-microvolt = <5000000>;
 100                 regulator-max-microvolt = <5000000>;
 101
 102                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
 103                 enable-active-high;
 104         };
 105 };
 106
 107 &eth0 {
 108         nvmem-cells = <&macaddr_romfile_f100 0>;
 109         nvmem-cell-names = "mac-address";
 110 };
 111
 112 &gphy0 {
 113         lantiq,gphy-mode = <GPHY_MODE_GE>;
 114 };
 115
 116 &gphy1 {
 117         lantiq,gphy-mode = <GPHY_MODE_GE>;
 118 };
 119
 120 &gpio {
 121         pinctrl-names = "default";
 122         pinctrl-0 = <&state_default>;
 123
 124         state_default: pinmux {
 125                 phy-rst {
 126                         lantiq,pins = "io42";
 127                         lantiq,pull = <0>;
 128                         lantiq,open-drain = <0>;
 129                         lantiq,output = <1>;
 130                 };
 131                 pcie-rst {
 132                         lantiq,pins = "io38";
 133                         lantiq,pull = <0>;
 134                         lantiq,output = <1>;
 135                 };
 136         };
 137 };
 138
 139 &gswip {
 140         pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
 141         pinctrl-names = "default";
 142 };
 143
 144 &gswip_mdio {
 145         phy0: ethernet-phy@0 {
 146                 reg = <0x0>;
 147                 // reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
 148         };
 149         phy5: ethernet-phy@5 {
 150                 reg = <0x5>;
 151         };
 152         phy11: ethernet-phy@11 {
 153                 reg = <0x11>;
 154         };
 155         phy13: ethernet-phy@13 {
 156                 reg = <0x13>;
 157         };
 158 };
 159
 160 &gswip_ports {
 161         port@0 {
 162                 reg = <0>;
 163                 label = "lan3";
 164                 phy-mode = "rgmii";
 165                 phy-handle = <&phy0>;
 166         };
 167         port@2 {
 168                 reg = <2>;
 169                 label = "lan2";
 170                 phy-mode = "internal";
 171                 phy-handle = <&phy11>;
 172         };
 173         port@4 {
 174                 reg = <4>;
 175                 label = "lan1";
 176                 phy-mode = "internal";
 177                 phy-handle = <&phy13>;
 178         };
 179         port@5 {
 180                 reg = <5>;
 181                 label = "lan4";
 182                 phy-mode = "rgmii";
 183                 phy-handle = <&phy5>;
 184         };
 185 };
 186
 187 &pcie0 {
 188         pcie@0 {
 189                 reg = <0 0 0 0 0>;
 190                 #interrupt-cells = <1>;
 191                 #size-cells = <2>;
 192                 #address-cells = <3>;
 193                 device_type = "pci";
 194
 195                 wifi@0,0 {
 196                         reg = <0 0 0 0 0>;
 197                         mediatek,mtd-eeprom = <&radio 0x0000>;
 198                         big-endian;
 199                         ieee80211-freq-limit = <5000000 6000000>;
 200                         nvmem-cells = <&macaddr_romfile_f100 2>;
 201                         nvmem-cell-names = "mac-address";
 202                 };
 203         };
 204 };
 205
 206 &pci0 {
 207         status = "okay";
 208         gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 209 };
 210
 211 &spi {
 212         status = "okay";
 213
 214         flash@4 {
 215                 compatible = "jedec,spi-nor";
 216                 reg = <4>;
 217                 spi-max-frequency = <33250000>;
 218                 m25p,fast-read;
 219
 220                 partitions {
 221                         compatible = "fixed-partitions";
 222                         #address-cells = <1>;
 223                         #size-cells = <1>;
 224
 225                         partition@0 {
 226                                 reg = <0x0 0x20000>;
 227                                 label = "u-boot";
 228                                 read-only;
 229                         };
 230
 231                         partition@20000 {
 232                                 reg = <0x20000 0xf90000>;
 233                                 label = "firmware";
 234                         };
 235
 236                         partition@fb0000 {
 237                                 reg = <0xfb0000 0x10000>;
 238                                 label = "radioDECT";
 239                                 read-only;
 240                         };
 241
 242                         partition@fc0000 {
 243                                 reg = <0xfc0000 0x10000>;
 244                                 label = "config";
 245                                 read-only;
 246                         };
 247
 248                         romfile: partition@fd0000 {
 249                                 reg = <0xfd0000 0x10000>;
 250                                 label = "romfile";
 251                                 read-only;
 252
 253                                 nvmem-layout {
 254                                         compatible = "fixed-layout";
 255                                         #address-cells = <1>;
 256                                         #size-cells = <1>;
 257
 258                                         macaddr_romfile_f100: macaddr@f100 {
 259                                                 compatible = "mac-base";
 260                                                 reg = <0xf100 0x6>;
 261                                                 #nvmem-cell-cells = <1>;
 262                                         };
 263                                 };
 264                         };
 265
 266                         partition@fe0000 {
 267                                 reg = <0xfe0000 0x10000>;
 268                                 label = "rom";
 269                                 read-only;
 270                         };
 271
 272                         radio: partition@ff0000 {
 273                                 reg = <0xff0000 0x10000>;
 274                                 label = "radio";
 275                                 read-only;
 276                         };
 277                 };
 278         };
 279 };
 280
 281 &usb_phy0 {
 282         status = "okay";
 283 };
 284
 285 &usb_phy1 {
 286         status = "okay";
 287 };
 288
 289 &usb0 {
 290         status = "okay";
 291         vbus-supply = <&usb_vbus>;
 292 };
 293
 294 &usb1 {
 295         status = "okay";
 296         vbus-supply = <&usb_vbus>;
 297 };