target/linux/lantiq/patches/100-board.patch

   1 --- a/arch/mips/Kconfig
   2 +++ b/arch/mips/Kconfig
   3 @@ -139,6 +139,9 @@ config MACH_DECSTATION
   4
   5           otherwise choose R3000.
   6
   7 +config LANTIQ
   8 +       bool "Lantiq MIPS"
   9 +
  10  config MACH_JAZZ
  11         bool "Jazz family of machines"
  12         select ARC
  13 @@ -693,6 +696,7 @@ source "arch/mips/txx9/Kconfig"
  14  source "arch/mips/vr41xx/Kconfig"
  15  source "arch/mips/cavium-octeon/Kconfig"
  16  source "arch/mips/loongson/Kconfig"
  17 +source "arch/mips/lantiq/Kconfig"
  18
  19  endmenu
  20
  21 --- a/arch/mips/Makefile
  22 +++ b/arch/mips/Makefile
  23 @@ -317,6 +317,17 @@ cflags-$(CONFIG_MIPS_COBALT)       += -I$(srct
  24  load-$(CONFIG_MIPS_COBALT)     += 0xffffffff80080000
  25
  26  #
  27 +# Lantiq
  28 +#
  29 +load-$(CONFIG_LANTIQ) += 0xffffffff80002000
  30 +core-$(CONFIG_LANTIQ) += arch/mips/lantiq/
  31 +cflags-$(CONFIG_LANTIQ)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq
  32 +core-$(CONFIG_SOC_LANTIQ_FALCON) += arch/mips/lantiq/falcon/
  33 +cflags-$(CONFIG_SOC_LANTIQ_FALCON)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon
  34 +core-$(CONFIG_SOC_LANTIQ_XWAY) += arch/mips/lantiq/xway/
  35 +cflags-$(CONFIG_SOC_LANTIQ_XWAY)   += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway
  36 +
  37 +#
  38  # DECstation family
  39  #
  40  core-$(CONFIG_MACH_DECSTATION) += arch/mips/dec/
  41 --- /dev/null
  42 +++ b/arch/mips/lantiq/Kconfig
  43 @@ -0,0 +1,36 @@
  44 +if LANTIQ
  45 +
  46 +config SOC_LANTIQ
  47 +       bool
  48 +       select DMA_NONCOHERENT
  49 +       select IRQ_CPU
  50 +       select CEVT_R4K
  51 +       select CSRC_R4K
  52 +       select SYS_HAS_CPU_MIPS32_R1
  53 +       select SYS_HAS_CPU_MIPS32_R2
  54 +       select SYS_SUPPORTS_BIG_ENDIAN
  55 +       select SYS_SUPPORTS_32BIT_KERNEL
  56 +       select SYS_SUPPORTS_MULTITHREADING
  57 +       select SYS_HAS_EARLY_PRINTK
  58 +       select HW_HAS_PCI
  59 +       select ARCH_REQUIRE_GPIOLIB
  60 +       select SWAP_IO_SPACE
  61 +       select MIPS_MACHINE
  62 +
  63 +choice
  64 +       prompt "SoC Type"
  65 +       default SOC_LANTIQ_XWAY
  66 +
  67 +#config SOC_LANTIQ_FALCON
  68 +#      bool "FALCON"
  69 +#      select SOC_LANTIQ
  70 +
  71 +config SOC_LANTIQ_XWAY
  72 +       bool "XWAY"
  73 +       select SOC_LANTIQ
  74 +endchoice
  75 +
  76 +#source "arch/mips/lantiq/falcon/Kconfig"
  77 +source "arch/mips/lantiq/xway/Kconfig"
  78 +
  79 +endif
  80 --- /dev/null
  81 +++ b/arch/mips/lantiq/Makefile
  82 @@ -0,0 +1,2 @@
  83 +obj-y := irq.o setup.o clk.o prom.o
  84 +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
  85 --- /dev/null
  86 +++ b/arch/mips/lantiq/irq.c
  87 @@ -0,0 +1,212 @@
  88 +/*
  89 + *  This program is free software; you can redistribute it and/or modify it
  90 + *  under the terms of the GNU General Public License version 2 as published
  91 + *  by the Free Software Foundation.
  92 + *
  93 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  94 + */
  95 +
  96 +#include <linux/module.h>
  97 +#include <linux/interrupt.h>
  98 +
  99 +#include <asm/bootinfo.h>
 100 +#include <asm/irq_cpu.h>
 101 +
 102 +#include <lantiq.h>
 103 +#include <irq.h>
 104 +
 105 +#define LQ_ICU_BASE_ADDR       (KSEG1 | 0x1F880200)
 106 +
 107 +#define LQ_ICU_IM0_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0000))
 108 +#define LQ_ICU_IM0_IER         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0008))
 109 +#define LQ_ICU_IM0_IOSR                ((u32 *)(LQ_ICU_BASE_ADDR + 0x0010))
 110 +#define LQ_ICU_IM0_IRSR                ((u32 *)(LQ_ICU_BASE_ADDR + 0x0018))
 111 +#define LQ_ICU_IM0_IMR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0020))
 112 +
 113 +#define LQ_ICU_IM1_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0028))
 114 +#define LQ_ICU_IM2_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0050))
 115 +#define LQ_ICU_IM3_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x0078))
 116 +#define LQ_ICU_IM4_ISR         ((u32 *)(LQ_ICU_BASE_ADDR + 0x00A0))
 117 +
 118 +#define LQ_ICU_OFFSET          (LQ_ICU_IM1_ISR - LQ_ICU_IM0_ISR)
 119 +
 120 +void
 121 +lq_disable_irq(unsigned int irq_nr)
 122 +{
 123 +       u32 *ier = LQ_ICU_IM0_IER;
 124 +       irq_nr -= INT_NUM_IRQ0;
 125 +       ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 126 +       irq_nr %= INT_NUM_IM_OFFSET;
 127 +       lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
 128 +}
 129 +EXPORT_SYMBOL(lq_disable_irq);
 130 +
 131 +void
 132 +lq_mask_and_ack_irq(unsigned int irq_nr)
 133 +{
 134 +       u32 *ier = LQ_ICU_IM0_IER;
 135 +       u32 *isr = LQ_ICU_IM0_ISR;
 136 +       irq_nr -= INT_NUM_IRQ0;
 137 +       ier += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 138 +       isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 139 +       irq_nr %= INT_NUM_IM_OFFSET;
 140 +       lq_w32(lq_r32(ier) & ~(1 << irq_nr), ier);
 141 +       lq_w32((1 << irq_nr), isr);
 142 +}
 143 +EXPORT_SYMBOL(lq_mask_and_ack_irq);
 144 +
 145 +static void
 146 +lq_ack_irq(unsigned int irq_nr)
 147 +{
 148 +       u32 *isr = LQ_ICU_IM0_ISR;
 149 +       irq_nr -= INT_NUM_IRQ0;
 150 +       isr += LQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET);
 151 +       irq_nr %= INT_NUM_IM_OFFSET;
 152 +       lq_w32((1 << irq_nr), isr);
 153 +}
 154 +
 155 +void
 156 +lq_enable_irq(unsigned int irq_nr)
 157 +{
 158 +       u32 *ier = LQ_ICU_IM0_IER;
 159 +       irq_nr -= INT_NUM_IRQ0;
 160 +       ier += LQ_ICU_OFFSET  * (irq_nr / INT_NUM_IM_OFFSET);
 161 +       irq_nr %= INT_NUM_IM_OFFSET;
 162 +       lq_w32(lq_r32(ier) | (1 << irq_nr), ier);
 163 +}
 164 +EXPORT_SYMBOL(lq_enable_irq);
 165 +
 166 +static unsigned int
 167 +lq_startup_irq(unsigned int irq)
 168 +{
 169 +       lq_enable_irq(irq);
 170 +       return 0;
 171 +}
 172 +
 173 +static void
 174 +lq_end_irq(unsigned int irq)
 175 +{
 176 +       if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 177 +               lq_enable_irq(irq);
 178 +}
 179 +
 180 +static struct irq_chip
 181 +lq_irq_type = {
 182 +       "lq_irq",
 183 +       .startup = lq_startup_irq,
 184 +       .enable = lq_enable_irq,
 185 +       .disable = lq_disable_irq,
 186 +       .unmask = lq_enable_irq,
 187 +       .ack = lq_ack_irq,
 188 +       .mask = lq_disable_irq,
 189 +       .mask_ack = lq_mask_and_ack_irq,
 190 +       .end = lq_end_irq,
 191 +};
 192 +
 193 +static void
 194 +lq_hw_irqdispatch(int module)
 195 +{
 196 +       u32 irq;
 197 +
 198 +       irq = lq_r32(LQ_ICU_IM0_IOSR + (module * LQ_ICU_OFFSET));
 199 +       if (irq == 0)
 200 +               return;
 201 +
 202 +       /* silicon bug causes only the msb set to 1 to be valid. all
 203 +          other bits might be bogus */
 204 +       irq = __fls(irq);
 205 +       do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module));
 206 +}
 207 +
 208 +#define DEFINE_HWx_IRQDISPATCH(x) \
 209 +static void lq_hw ## x ## _irqdispatch(void)\
 210 +{\
 211 +       lq_hw_irqdispatch(x); \
 212 +}
 213 +static void lq_hw5_irqdispatch(void)
 214 +{
 215 +       do_IRQ(MIPS_CPU_TIMER_IRQ);
 216 +}
 217 +DEFINE_HWx_IRQDISPATCH(0)
 218 +DEFINE_HWx_IRQDISPATCH(1)
 219 +DEFINE_HWx_IRQDISPATCH(2)
 220 +DEFINE_HWx_IRQDISPATCH(3)
 221 +DEFINE_HWx_IRQDISPATCH(4)
 222 +/*DEFINE_HWx_IRQDISPATCH(5)*/
 223 +
 224 +asmlinkage void
 225 +plat_irq_dispatch(void)
 226 +{
 227 +       unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 228 +       unsigned int i;
 229 +
 230 +       if (pending & CAUSEF_IP7)
 231 +       {
 232 +               do_IRQ(MIPS_CPU_TIMER_IRQ);
 233 +               goto out;
 234 +       } else {
 235 +               for (i = 0; i < 5; i++)
 236 +               {
 237 +                       if (pending & (CAUSEF_IP2 << i))
 238 +                       {
 239 +                               lq_hw_irqdispatch(i);
 240 +                               goto out;
 241 +                       }
 242 +               }
 243 +       }
 244 +       printk(KERN_ALERT "Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 245 +
 246 +out:
 247 +       return;
 248 +}
 249 +
 250 +static struct irqaction
 251 +cascade = {
 252 +       .handler = no_action,
 253 +       .flags = IRQF_DISABLED,
 254 +       .name = "cascade",
 255 +};
 256 +
 257 +void __init
 258 +arch_init_irq(void)
 259 +{
 260 +       int i;
 261 +
 262 +       for (i = 0; i < 5; i++)
 263 +               lq_w32(0, LQ_ICU_IM0_IER + (i * LQ_ICU_OFFSET));
 264 +
 265 +       mips_cpu_irq_init();
 266 +
 267 +       for (i = 2; i <= 6; i++)
 268 +               setup_irq(i, &cascade);
 269 +
 270 +       if (cpu_has_vint) {
 271 +               printk(KERN_INFO "Setting up vectored interrupts\n");
 272 +               set_vi_handler(2, lq_hw0_irqdispatch);
 273 +               set_vi_handler(3, lq_hw1_irqdispatch);
 274 +               set_vi_handler(4, lq_hw2_irqdispatch);
 275 +               set_vi_handler(5, lq_hw3_irqdispatch);
 276 +               set_vi_handler(6, lq_hw4_irqdispatch);
 277 +               set_vi_handler(7, lq_hw5_irqdispatch);
 278 +       }
 279 +
 280 +       for (i = INT_NUM_IRQ0; i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++)
 281 +               set_irq_chip_and_handler(i, &lq_irq_type,
 282 +                       handle_level_irq);
 283 +
 284 +       #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
 285 +       set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 |
 286 +               IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 287 +       #else
 288 +       set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 |
 289 +               IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 290 +       #endif
 291 +}
 292 +
 293 +void __cpuinit
 294 +arch_fixup_c0_irqs(void)
 295 +{
 296 +       /* FIXME: check for CPUID and only do fix for specific chips/versions */
 297 +       cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 298 +       cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 299 +}
 300 --- /dev/null
 301 +++ b/arch/mips/lantiq/setup.c
 302 @@ -0,0 +1,47 @@
 303 +/*
 304 + *  This program is free software; you can redistribute it and/or modify it
 305 + *  under the terms of the GNU General Public License version 2 as published
 306 + *  by the Free Software Foundation.
 307 + *
 308 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 309 + */
 310 +
 311 +#include <linux/kernel.h>
 312 +#include <linux/module.h>
 313 +#include <linux/io.h>
 314 +#include <linux/ioport.h>
 315 +
 316 +#include <lantiq.h>
 317 +#include <lantiq_regs.h>
 318 +
 319 +void __init
 320 +plat_mem_setup(void)
 321 +{
 322 +       /* assume 16M as default */
 323 +       int memsize = 16;
 324 +       char **envp = (char **) KSEG1ADDR(fw_arg2);
 325 +       u32 status;
 326 +
 327 +       /* make sure to have no "reverse endian" for user mode! */
 328 +       status = read_c0_status();
 329 +       status &= (~(1<<25));
 330 +       write_c0_status(status);
 331 +
 332 +       ioport_resource.start = IOPORT_RESOURCE_START;
 333 +       ioport_resource.end = IOPORT_RESOURCE_END;
 334 +       iomem_resource.start = IOMEM_RESOURCE_START;
 335 +       iomem_resource.end = IOMEM_RESOURCE_END;
 336 +
 337 +       while (*envp)
 338 +       {
 339 +               char *e = (char *)KSEG1ADDR(*envp);
 340 +               if (!strncmp(e, "memsize=", 8))
 341 +               {
 342 +                       e += 8;
 343 +                       memsize = simple_strtoul(e, NULL, 10);
 344 +               }
 345 +               envp++;
 346 +       }
 347 +       memsize *= 1024 * 1024;
 348 +       add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
 349 +}
 350 --- /dev/null
 351 +++ b/arch/mips/lantiq/clk.c
 352 @@ -0,0 +1,141 @@
 353 +/*
 354 + *  This program is free software; you can redistribute it and/or modify it
 355 + *  under the terms of the GNU General Public License version 2 as published
 356 + *  by the Free Software Foundation.
 357 + *
 358 + * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland
 359 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 360 + */
 361 +
 362 +#include <linux/io.h>
 363 +#include <linux/module.h>
 364 +#include <linux/init.h>
 365 +#include <linux/kernel.h>
 366 +#include <linux/types.h>
 367 +#include <linux/clk.h>
 368 +#include <linux/err.h>
 369 +#include <linux/list.h>
 370 +
 371 +#include <asm/time.h>
 372 +#include <asm/irq.h>
 373 +#include <asm/div64.h>
 374 +
 375 +#include <lantiq.h>
 376 +#ifdef CONFIG_SOC_LANTIQ_XWAY
 377 +#include <xway.h>
 378 +#endif
 379 +
 380 +extern unsigned long lq_get_cpu_hz(void);
 381 +extern unsigned long lq_get_fpi_hz(void);
 382 +extern unsigned long lq_get_io_region_clock(void);
 383 +
 384 +struct clk {
 385 +       const char *name;
 386 +       unsigned long rate;
 387 +       unsigned long (*get_rate) (void);
 388 +};
 389 +
 390 +static struct clk *cpu_clk = 0;
 391 +static int cpu_clk_cnt = 0;
 392 +
 393 +static unsigned int r4k_offset;
 394 +static unsigned int r4k_cur;
 395 +
 396 +static struct clk cpu_clk_generic[] = {
 397 +       {
 398 +               .name = "cpu",
 399 +               .get_rate = lq_get_cpu_hz,
 400 +       }, {
 401 +               .name = "fpi",
 402 +               .get_rate = lq_get_fpi_hz,
 403 +       }, {
 404 +               .name = "io",
 405 +               .get_rate = lq_get_io_region_clock,
 406 +       },
 407 +};
 408 +
 409 +void
 410 +clk_init(void)
 411 +{
 412 +       int i;
 413 +       cpu_clk = cpu_clk_generic;
 414 +       cpu_clk_cnt = ARRAY_SIZE(cpu_clk_generic);
 415 +       for(i = 0; i < cpu_clk_cnt; i++)
 416 +               printk("%s: %ld\n", cpu_clk[i].name, clk_get_rate(&cpu_clk[i]));
 417 +}
 418 +
 419 +static inline int
 420 +clk_good(struct clk *clk)
 421 +{
 422 +       return clk && !IS_ERR(clk);
 423 +}
 424 +
 425 +unsigned long
 426 +clk_get_rate(struct clk *clk)
 427 +{
 428 +       if (unlikely(!clk_good(clk)))
 429 +               return 0;
 430 +
 431 +       if (clk->rate != 0)
 432 +               return clk->rate;
 433 +
 434 +       if (clk->get_rate != NULL)
 435 +               return clk->get_rate();
 436 +
 437 +       return 0;
 438 +}
 439 +EXPORT_SYMBOL(clk_get_rate);
 440 +
 441 +struct clk*
 442 +clk_get(struct device *dev, const char *id)
 443 +{
 444 +       int i;
 445 +       for(i = 0; i < cpu_clk_cnt; i++)
 446 +               if (!strcmp(id, cpu_clk[i].name))
 447 +                       return &cpu_clk[i];
 448 +       BUG();
 449 +       return ERR_PTR(-ENOENT);
 450 +}
 451 +EXPORT_SYMBOL(clk_get);
 452 +
 453 +void
 454 +clk_put(struct clk *clk)
 455 +{
 456 +       /* not used */
 457 +}
 458 +EXPORT_SYMBOL(clk_put);
 459 +
 460 +static inline u32
 461 +lq_get_counter_resolution(void)
 462 +{
 463 +       u32 res;
 464 +       __asm__ __volatile__(
 465 +               ".set   push\n"
 466 +               ".set   mips32r2\n"
 467 +               ".set   noreorder\n"
 468 +               "rdhwr  %0, $3\n"
 469 +               "ehb\n"
 470 +               ".set pop\n"
 471 +               : "=&r" (res)
 472 +               : /* no input */
 473 +               : "memory");
 474 +       instruction_hazard();
 475 +       return res;
 476 +}
 477 +
 478 +void __init
 479 +plat_time_init(void)
 480 +{
 481 +       struct clk *clk = clk_get(0, "cpu");
 482 +       mips_hpt_frequency = clk_get_rate(clk) / lq_get_counter_resolution();
 483 +       r4k_cur = (read_c0_count() + r4k_offset);
 484 +       write_c0_compare(r4k_cur);
 485 +
 486 +#ifdef CONFIG_SOC_LANTIQ_XWAY
 487 +#define LQ_GPTU_GPT_CLC                        ((u32 *)(LQ_GPTU_BASE_ADDR + 0x0000))
 488 +       lq_pmu_enable(PMU_GPT);
 489 +       lq_pmu_enable(PMU_FPI);
 490 +
 491 +       lq_w32(0x100, LQ_GPTU_GPT_CLC);
 492 +#endif
 493 +}
 494 --- /dev/null
 495 +++ b/arch/mips/lantiq/prom.c
 496 @@ -0,0 +1,118 @@
 497 +/*
 498 + *  This program is free software; you can redistribute it and/or modify it
 499 + *  under the terms of the GNU General Public License version 2 as published
 500 + *  by the Free Software Foundation.
 501 + *
 502 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 503 + */
 504 +
 505 +#include <linux/module.h>
 506 +#include <linux/clk.h>
 507 +#include <asm/bootinfo.h>
 508 +#include <asm/time.h>
 509 +
 510 +#include <lantiq.h>
 511 +
 512 +#include "prom.h"
 513 +
 514 +static struct lq_soc_info soc_info;
 515 +
 516 +/* for Multithreading (APRP) on MIPS34K */
 517 +unsigned long physical_memsize;
 518 +
 519 +/* all access to the ebu must be locked */
 520 +DEFINE_SPINLOCK(ebu_lock);
 521 +EXPORT_SYMBOL_GPL(ebu_lock);
 522 +
 523 +extern void clk_init(void);
 524 +
 525 +unsigned int
 526 +lq_get_cpu_ver(void)
 527 +{
 528 +       return soc_info.rev;
 529 +}
 530 +EXPORT_SYMBOL(lq_get_cpu_ver);
 531 +
 532 +unsigned int
 533 +lq_get_soc_type(void)
 534 +{
 535 +       return soc_info.type;
 536 +}
 537 +EXPORT_SYMBOL(lq_get_soc_type);
 538 +
 539 +const char*
 540 +get_system_type(void)
 541 +{
 542 +       return soc_info.sys_type;
 543 +}
 544 +
 545 +void
 546 +prom_free_prom_memory(void)
 547 +{
 548 +}
 549 +
 550 +#ifdef CONFIG_IMAGE_CMDLINE_HACK
 551 +extern char __image_cmdline[];
 552 +
 553 +static void __init
 554 +prom_init_image_cmdline(void)
 555 +{
 556 +       char *p = __image_cmdline;
 557 +       int replace = 0;
 558 +
 559 +       if (*p == '-') {
 560 +               replace = 1;
 561 +               p++;
 562 +       }
 563 +
 564 +       if (*p == '\0')
 565 +               return;
 566 +
 567 +       if (replace) {
 568 +               strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline));
 569 +       } else {
 570 +               strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
 571 +               strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
 572 +       }
 573 +}
 574 +#else
 575 +static void __init prom_init_image_cmdline(void) { return; }
 576 +#endif
 577 +
 578 +static void __init
 579 +prom_init_cmdline(void)
 580 +{
 581 +       int argc = fw_arg0;
 582 +       char **argv = (char**)KSEG1ADDR(fw_arg1);
 583 +       int i;
 584 +
 585 +       arcs_cmdline[0] = '\0';
 586 +       if(argc)
 587 +               for (i = 1; i < argc; i++)
 588 +               {
 589 +                       strlcat(arcs_cmdline, (char*)KSEG1ADDR(argv[i]), COMMAND_LINE_SIZE);
 590 +                       if(i + 1 != argc)
 591 +                               strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
 592 +               }
 593 +
 594 +       if (!*arcs_cmdline)
 595 +               strcpy(&(arcs_cmdline[0]),
 596 +                       "console=ttyS1,115200 rootfstype=squashfs,jffs2");
 597 +       prom_init_image_cmdline();
 598 +}
 599 +
 600 +void __init
 601 +prom_init(void)
 602 +{
 603 +       struct clk *clk;
 604 +       lq_soc_detect(&soc_info);
 605 +
 606 +       clk_init();
 607 +       clk = clk_get(0, "cpu");
 608 +       snprintf(soc_info.sys_type, LQ_SYS_TYPE_LEN - 1, "%s rev1.%d %ldMhz",
 609 +               soc_info.name, soc_info.rev, clk_get_rate(clk) / 1000000);
 610 +       soc_info.sys_type[LQ_SYS_TYPE_LEN - 1] = '\0';
 611 +       printk("SoC: %s\n", soc_info.sys_type);
 612 +
 613 +       prom_init_cmdline();
 614 +}
 615 --- /dev/null
 616 +++ b/arch/mips/lantiq/prom.h
 617 @@ -0,0 +1,24 @@
 618 +/*
 619 + *  This program is free software; you can redistribute it and/or modify it
 620 + *  under the terms of the GNU General Public License version 2 as published
 621 + *  by the Free Software Foundation.
 622 + *
 623 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
 624 + */
 625 +
 626 +#ifndef _LQ_PROM_H__
 627 +#define _LQ_PROM_H__
 628 +
 629 +#define LQ_SYS_TYPE_LEN        0x100
 630 +
 631 +struct lq_soc_info {
 632 +       unsigned char *name;
 633 +       unsigned int rev;
 634 +       unsigned int partnum;
 635 +       unsigned int type;
 636 +       unsigned char sys_type[LQ_SYS_TYPE_LEN];
 637 +};
 638 +
 639 +void lq_soc_detect(struct lq_soc_info *i);
 640 +
 641 +#endif