lantiq: add wifi eep to a803 dts file
[openwrt/staging/mkresin.git] / target / linux / lantiq / patches-3.8 / 0043-PINCTRL-lantiq-add_gphy_led.patch
1 Index: linux-3.8.13/drivers/pinctrl/pinctrl-xway.c
2 ===================================================================
3 --- linux-3.8.13.orig/drivers/pinctrl/pinctrl-xway.c 2013-07-27 15:05:47.693196681 +0200
4 +++ linux-3.8.13/drivers/pinctrl/pinctrl-xway.c 2013-07-29 14:43:05.237674357 +0200
5 @@ -101,6 +101,7 @@
6 XWAY_MUX_EPHY,
7 XWAY_MUX_DFE,
8 XWAY_MUX_SDIO,
9 + XWAY_MUX_GPHY,
10 XWAY_MUX_NONE = 0xffff,
11 };
12
13 @@ -108,12 +109,12 @@
14 /* pin f0 f1 f2 f3 */
15 MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
16 MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
17 - MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
18 + MFP_XWAY(GPIO2, GPIO, CGU, EXIN, GPHY),
19 MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
20 MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
21 - MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE),
22 + MFP_XWAY(GPIO5, GPIO, STP, NONE, GPHY),
23 MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
24 - MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE),
25 + MFP_XWAY(GPIO7, GPIO, CGU, PCI, GPHY),
26 MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
27 MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
28 MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
29 @@ -150,10 +151,10 @@
30 MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
31 MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
32 MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
33 - MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN),
34 - MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN),
35 + MFP_XWAY(GPIO44, GPIO, NONE, GPHY, SIN),
36 + MFP_XWAY(GPIO45, GPIO, NONE, GPHY, SIN),
37 MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
38 - MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN),
39 + MFP_XWAY(GPIO47, GPIO, NONE, GPHY, SIN),
40 MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
41 MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
42 MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
43 @@ -207,6 +208,13 @@
44 static const unsigned pins_nmi[] = {GPIO8};
45 static const unsigned pins_mdio[] = {GPIO42, GPIO43};
46
47 +static const unsigned pins_gphy0_led0[] = {GPIO5};
48 +static const unsigned pins_gphy0_led1[] = {GPIO7};
49 +static const unsigned pins_gphy0_led2[] = {GPIO2};
50 +static const unsigned pins_gphy1_led0[] = {GPIO44};
51 +static const unsigned pins_gphy1_led1[] = {GPIO45};
52 +static const unsigned pins_gphy1_led2[] = {GPIO47};
53 +
54 static const unsigned pins_ebu_a24[] = {GPIO13};
55 static const unsigned pins_ebu_clk[] = {GPIO21};
56 static const unsigned pins_ebu_cs1[] = {GPIO23};
57 @@ -321,6 +329,12 @@
58 GRP_MUX("gnt4", PCI, pins_pci_gnt4),
59 GRP_MUX("req4", PCI, pins_pci_gnt4),
60 GRP_MUX("mdio", MDIO, pins_mdio),
61 + GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
62 + GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
63 + GRP_MUX("gphy0 lde2", GPHY, pins_gphy0_led2),
64 + GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
65 + GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
66 + GRP_MUX("gphy1 lde2", GPHY, pins_gphy1_led2),
67 };
68
69 static const struct ltq_pin_group ase_grps[] = {
70 @@ -364,6 +378,9 @@
71
72 /* ar9/vr9/gr9 */
73 static const char * const xrx_mdio_grps[] = {"mdio"};
74 +static const char * const xrx_gphy_grps[] = {"gphy0 led0", "gphy0 led1",
75 + "gphy0 led2", "gphy1 led0",
76 + "gphy1 led1", "gphy1 led2"};
77 static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
78 "ebu a25", "ebu cs1",
79 "ebu wait", "ebu clk",
80 @@ -413,6 +430,7 @@
81 {"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
82 {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
83 {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
84 + {"gphy", ARRAY_AND_SIZE(xrx_gphy_grps)},
85 };
86
87 static const struct ltq_pmx_func ase_funcs[] = {
88