target/linux/layerscape/patches-4.14/823-pm-support-layerscape.patch

   1 From aded309f403c4202b9c6f61ea6a635e0c736eb77 Mon Sep 17 00:00:00 2001
   2 From: Biwen Li <biwen.li@nxp.com>
   3 Date: Tue, 30 Oct 2018 18:27:07 +0800
   4 Subject: [PATCH 40/40] pm: support layerscape
   5 This is an integrated patch of pm for layerscape
   6
   7 Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com>
   8 Signed-off-by: Hongbo Zhang <hongbo.zhang@freescale.com>
   9 Signed-off-by: Li Yang <leoyang.li@nxp.com>
  10 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  11 Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
  12 Signed-off-by: Zhao Chenhui <chenhui.zhao@nxp.com>
  13 Signed-off-by: Biwen Li <biwen.li@nxp.com>
  14 ---
  15  .../devicetree/bindings/powerpc/fsl/pmc.txt   |  59 ++--
  16  drivers/firmware/psci.c                       |  16 +-
  17  drivers/soc/fsl/rcpm.c                        | 158 ++++++++++
  18  drivers/soc/fsl/sleep_fsm.c                   | 279 ++++++++++++++++++
  19  drivers/soc/fsl/sleep_fsm.h                   | 130 ++++++++
  20  5 files changed, 615 insertions(+), 27 deletions(-)
  21  create mode 100644 drivers/soc/fsl/rcpm.c
  22  create mode 100644 drivers/soc/fsl/sleep_fsm.c
  23  create mode 100644 drivers/soc/fsl/sleep_fsm.h
  24
  25 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
  26 +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt
  27 @@ -9,15 +9,20 @@ Properties:
  28
  29    "fsl,mpc8548-pmc" should be listed for any chip whose PMC is
  30    compatible.  "fsl,mpc8536-pmc" should also be listed for any chip
  31 -  whose PMC is compatible, and implies deep-sleep capability.
  32 +  whose PMC is compatible, and implies deep-sleep capability and
  33 +  wake on user defined packet(wakeup on ARP).
  34 +
  35 +  "fsl,p1022-pmc" should be listed for any chip whose PMC is
  36 +  compatible, and implies lossless Ethernet capability during sleep.
  37
  38    "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is
  39    compatible; all statements below that apply to "fsl,mpc8548-pmc" also
  40    apply to "fsl,mpc8641d-pmc".
  41
  42    Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these
  43 -  bit assignments are indicated via the sleep specifier in each device's
  44 -  sleep property.
  45 +  bit assignments are indicated via the clock nodes.  Device which has a
  46 +  controllable clock source should have a "fsl,pmc-handle" property pointing
  47 +  to the clock node.
  48
  49  - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource
  50    is the PMC block, and the second resource is the Clock Configuration
  51 @@ -33,31 +38,35 @@ Properties:
  52    this is a phandle to an "fsl,gtm" node on which timer 4 can be used as
  53    a wakeup source from deep sleep.
  54
  55 -Sleep specifiers:
  56 -
  57 -  fsl,mpc8349-pmc: Sleep specifiers consist of one cell.  For each bit
  58 -  that is set in the cell, the corresponding bit in SCCR will be saved
  59 -  and cleared on suspend, and restored on resume.  This sleep controller
  60 -  supports disabling and resuming devices at any time.
  61 -
  62 -  fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of
  63 -  which will be ORed into PMCDR upon suspend, and cleared from PMCDR
  64 -  upon resume.  The first two cells are as described for fsl,mpc8578-pmc.
  65 -  This sleep controller only supports disabling devices during system
  66 -  sleep, or permanently.
  67 -
  68 -  fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the
  69 -  first of which will be ORed into DEVDISR (and the second into
  70 -  DEVDISR2, if present -- this cell should be zero or absent if the
  71 -  hardware does not have DEVDISR2) upon a request for permanent device
  72 -  disabling.  This sleep controller does not support configuring devices
  73 -  to disable during system sleep (unless supported by another compatible
  74 -  match), or dynamically.
  75 +Clock nodes:
  76 +The clock nodes are to describe the masks in PM controller registers for each
  77 +soc clock.
  78 +- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be
  79 +  ORed into PMCDR before suspend if the device using this clock is the wake-up
  80 +  source and need to be running during low power mode; clear the mask if
  81 +  otherwise.
  82 +
  83 +- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding
  84 +  bit specified by the mask in SCCR will be saved and cleared on suspend, and
  85 +  restored on resume.
  86 +
  87 +- fsl,devdisr-mask: Contain one or two cells, depending on the availability of
  88 +  DEVDISR2 register.  For compatible devices, the mask will be ORed into DEVDISR
  89 +  or DEVDISR2 when the clock should be permenently disabled.
  90
  91  Example:
  92
  93 -       power@b00 {
  94 -               compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc";
  95 -               reg = <0xb00 0x100 0xa00 0x100>;
  96 -               interrupts = <80 8>;
  97 +       power@e0070 {
  98 +               compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc";
  99 +               reg = <0xe0070 0x20>;
 100 +
 101 +               etsec1_clk: soc-clk@24 {
 102 +                       fsl,pmcdr-mask = <0x00000080>;
 103 +               };
 104 +               etsec2_clk: soc-clk@25 {
 105 +                       fsl,pmcdr-mask = <0x00000040>;
 106 +               };
 107 +               etsec3_clk: soc-clk@26 {
 108 +                       fsl,pmcdr-mask = <0x00000020>;
 109 +               };
 110         };
 111 --- a/drivers/firmware/psci.c
 112 +++ b/drivers/firmware/psci.c
 113 @@ -437,8 +437,18 @@ CPUIDLE_METHOD_OF_DECLARE(psci, "psci",
 114
 115  static int psci_system_suspend(unsigned long unused)
 116  {
 117 -       return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
 118 -                             __pa_symbol(cpu_resume), 0, 0);
 119 +       u32 state;
 120 +       u32 ver = psci_get_version();
 121 +
 122 +       if (PSCI_VERSION_MAJOR(ver) >= 1) {
 123 +               return invoke_psci_fn(PSCI_FN_NATIVE(1_0, SYSTEM_SUSPEND),
 124 +                               virt_to_phys(cpu_resume), 0, 0);
 125 +       } else {
 126 +               state = ( 2 << PSCI_0_2_POWER_STATE_AFFL_SHIFT) |
 127 +                       (1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT);
 128 +
 129 +               return psci_cpu_suspend(state, virt_to_phys(cpu_resume));
 130 +       }
 131  }
 132
 133  static int psci_system_suspend_enter(suspend_state_t state)
 134 @@ -562,6 +572,8 @@ static void __init psci_0_2_set_function
 135         arm_pm_restart = psci_sys_reset;
 136
 137         pm_power_off = psci_sys_poweroff;
 138 +
 139 +       suspend_set_ops(&psci_suspend_ops);
 140  }
 141
 142  /*
 143 --- /dev/null
 144 +++ b/drivers/soc/fsl/rcpm.c
 145 @@ -0,0 +1,158 @@
 146 +/*
 147 + * Run Control and Power Management (RCPM) driver
 148 + *
 149 + * Copyright 2016 NXP
 150 + *
 151 + * This program is free software; you can redistribute it and/or modify
 152 + * it under the terms of the GNU General Public License as published by
 153 + * the Free Software Foundation; either version 2 of the License, or
 154 + * (at your option) any later version.
 155 + *
 156 + * This program is distributed in the hope that it will be useful,
 157 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 158 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 159 + * GNU General Public License for more details.
 160 + *
 161 + */
 162 +#define pr_fmt(fmt) "RCPM: %s: " fmt, __func__
 163 +
 164 +#include <linux/kernel.h>
 165 +#include <linux/io.h>
 166 +#include <linux/of_platform.h>
 167 +#include <linux/of_address.h>
 168 +#include <linux/suspend.h>
 169 +
 170 +/* RCPM register offset */
 171 +#define RCPM_IPPDEXPCR0                        0x140
 172 +
 173 +#define RCPM_WAKEUP_CELL_SIZE  2
 174 +
 175 +struct rcpm_config {
 176 +       int ipp_num;
 177 +       int ippdexpcr_offset;
 178 +       u32 ippdexpcr[2];
 179 +       void *rcpm_reg_base;
 180 +};
 181 +
 182 +static struct rcpm_config *rcpm;
 183 +
 184 +static inline void rcpm_reg_write(u32 offset, u32 value)
 185 +{
 186 +       iowrite32be(value, rcpm->rcpm_reg_base + offset);
 187 +}
 188 +
 189 +static inline u32 rcpm_reg_read(u32 offset)
 190 +{
 191 +       return ioread32be(rcpm->rcpm_reg_base + offset);
 192 +}
 193 +
 194 +static void rcpm_wakeup_fixup(struct device *dev, void *data)
 195 +{
 196 +       struct device_node *node = dev ? dev->of_node : NULL;
 197 +       u32 value[RCPM_WAKEUP_CELL_SIZE];
 198 +       int ret, i;
 199 +
 200 +       if (!dev || !node || !device_may_wakeup(dev))
 201 +               return;
 202 +
 203 +       /*
 204 +        * Get the values in the "rcpm-wakeup" property.
 205 +        * Three values are:
 206 +        * The first is a pointer to the RCPM node.
 207 +        * The second is the value of the ippdexpcr0 register.
 208 +        * The third is the value of the ippdexpcr1 register.
 209 +        */
 210 +       ret = of_property_read_u32_array(node, "fsl,rcpm-wakeup",
 211 +                                        value, RCPM_WAKEUP_CELL_SIZE);
 212 +       if (ret)
 213 +               return;
 214 +
 215 +       pr_debug("wakeup source: the device %s\n", node->full_name);
 216 +
 217 +       for (i = 0; i < rcpm->ipp_num; i++)
 218 +               rcpm->ippdexpcr[i] |= value[i + 1];
 219 +}
 220 +
 221 +static int rcpm_suspend_prepare(void)
 222 +{
 223 +       int i;
 224 +       u32 val;
 225 +
 226 +       BUG_ON(!rcpm);
 227 +
 228 +       for (i = 0; i < rcpm->ipp_num; i++)
 229 +               rcpm->ippdexpcr[i] = 0;
 230 +
 231 +       dpm_for_each_dev(NULL, rcpm_wakeup_fixup);
 232 +
 233 +       for (i = 0; i < rcpm->ipp_num; i++) {
 234 +               if (rcpm->ippdexpcr[i]) {
 235 +                       val = rcpm_reg_read(rcpm->ippdexpcr_offset + 4 * i);
 236 +                       rcpm_reg_write(rcpm->ippdexpcr_offset + 4 * i,
 237 +                                              val | rcpm->ippdexpcr[i]);
 238 +                       pr_debug("ippdexpcr%d = 0x%x\n", i, rcpm->ippdexpcr[i]);
 239 +               }
 240 +       }
 241 +
 242 +       return 0;
 243 +}
 244 +
 245 +static int rcpm_suspend_notifier_call(struct notifier_block *bl,
 246 +                                     unsigned long state,
 247 +                                     void *unused)
 248 +{
 249 +       switch (state) {
 250 +       case PM_SUSPEND_PREPARE:
 251 +               rcpm_suspend_prepare();
 252 +               break;
 253 +       }
 254 +
 255 +       return NOTIFY_DONE;
 256 +}
 257 +
 258 +static struct rcpm_config rcpm_default_config = {
 259 +       .ipp_num = 1,
 260 +       .ippdexpcr_offset = RCPM_IPPDEXPCR0,
 261 +};
 262 +
 263 +static const struct of_device_id rcpm_matches[] = {
 264 +       {
 265 +               .compatible = "fsl,qoriq-rcpm-2.1",
 266 +               .data = &rcpm_default_config,
 267 +       },
 268 +       {}
 269 +};
 270 +
 271 +static struct notifier_block rcpm_suspend_notifier = {
 272 +       .notifier_call = rcpm_suspend_notifier_call,
 273 +};
 274 +
 275 +static int __init layerscape_rcpm_init(void)
 276 +{
 277 +       const struct of_device_id *match;
 278 +       struct device_node *np;
 279 +
 280 +       np = of_find_matching_node_and_match(NULL, rcpm_matches, &match);
 281 +       if (!np) {
 282 +               pr_err("Can't find the RCPM node.\n");
 283 +               return -EINVAL;
 284 +       }
 285 +
 286 +       if (match->data)
 287 +               rcpm = (struct rcpm_config *)match->data;
 288 +       else
 289 +               return -EINVAL;
 290 +
 291 +       rcpm->rcpm_reg_base = of_iomap(np, 0);
 292 +       of_node_put(np);
 293 +       if (!rcpm->rcpm_reg_base)
 294 +               return -ENOMEM;
 295 +
 296 +       register_pm_notifier(&rcpm_suspend_notifier);
 297 +
 298 +       pr_info("The RCPM driver initialized.\n");
 299 +
 300 +       return 0;
 301 +}
 302 +
 303 +subsys_initcall(layerscape_rcpm_init);
 304 --- /dev/null
 305 +++ b/drivers/soc/fsl/sleep_fsm.c
 306 @@ -0,0 +1,279 @@
 307 +/*
 308 + * deep sleep FSM (finite-state machine) configuration
 309 + *
 310 + * Copyright 2018 NXP
 311 + *
 312 + * Author: Hongbo Zhang <hongbo.zhang@freescale.com>
 313 + *         Chenhui Zhao <chenhui.zhao@freescale.com>
 314 + *
 315 + * Redistribution and use in source and binary forms, with or without
 316 + * modification, are permitted provided that the following conditions are met:
 317 + *     * Redistributions of source code must retain the above copyright
 318 + *      notice, this list of conditions and the following disclaimer.
 319 + *     * Redistributions in binary form must reproduce the above copyright
 320 + *      notice, this list of conditions and the following disclaimer in the
 321 + *      documentation and/or other materials provided with the distribution.
 322 + *     * Neither the name of the above-listed copyright holders nor the
 323 + *      names of any contributors may be used to endorse or promote products
 324 + *      derived from this software without specific prior written permission.
 325 + *
 326 + * ALTERNATIVELY, this software may be distributed under the terms of the
 327 + * GNU General Public License ("GPL") as published by the Free Software
 328 + * Foundation, either version 2 of that License or (at your option) any
 329 + * later version.
 330 + *
 331 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 332 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 333 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 334 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
 335 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 336 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 337 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 338 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 339 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 340 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 341 + * POSSIBILITY OF SUCH DAMAGE.
 342 + */
 343 +
 344 +#include <linux/kernel.h>
 345 +#include <linux/io.h>
 346 +#include <linux/types.h>
 347 +
 348 +#include "sleep_fsm.h"
 349 +/*
 350 + * These values are from chip's reference manual. For example,
 351 + * the values for T1040 can be found in "8.4.3.8 Programming
 352 + * supporting deep sleep mode" of Chapter 8 "Run Control and
 353 + * Power Management (RCPM)".
 354 + * The default value can be applied to T104x, LS1021.
 355 + */
 356 +struct fsm_reg_vals epu_default_val[] = {
 357 +       /* EPGCR (Event Processor Global Control Register) */
 358 +       {EPGCR, 0},
 359 +       /* EPECR (Event Processor Event Control Registers) */
 360 +       {EPECR0 + EPECR_STRIDE * 0, 0},
 361 +       {EPECR0 + EPECR_STRIDE * 1, 0},
 362 +       {EPECR0 + EPECR_STRIDE * 2, 0xF0004004},
 363 +       {EPECR0 + EPECR_STRIDE * 3, 0x80000084},
 364 +       {EPECR0 + EPECR_STRIDE * 4, 0x20000084},
 365 +       {EPECR0 + EPECR_STRIDE * 5, 0x08000004},
 366 +       {EPECR0 + EPECR_STRIDE * 6, 0x80000084},
 367 +       {EPECR0 + EPECR_STRIDE * 7, 0x80000084},
 368 +       {EPECR0 + EPECR_STRIDE * 8, 0x60000084},
 369 +       {EPECR0 + EPECR_STRIDE * 9, 0x08000084},
 370 +       {EPECR0 + EPECR_STRIDE * 10, 0x42000084},
 371 +       {EPECR0 + EPECR_STRIDE * 11, 0x90000084},
 372 +       {EPECR0 + EPECR_STRIDE * 12, 0x80000084},
 373 +       {EPECR0 + EPECR_STRIDE * 13, 0x08000084},
 374 +       {EPECR0 + EPECR_STRIDE * 14, 0x02000084},
 375 +       {EPECR0 + EPECR_STRIDE * 15, 0x00000004},
 376 +       /*
 377 +        * EPEVTCR (Event Processor EVT Pin Control Registers)
 378 +        * SCU8 triger EVT2, and SCU11 triger EVT9
 379 +        */
 380 +       {EPEVTCR0 + EPEVTCR_STRIDE * 0, 0},
 381 +       {EPEVTCR0 + EPEVTCR_STRIDE * 1, 0},
 382 +       {EPEVTCR0 + EPEVTCR_STRIDE * 2, 0x80000001},
 383 +       {EPEVTCR0 + EPEVTCR_STRIDE * 3, 0},
 384 +       {EPEVTCR0 + EPEVTCR_STRIDE * 4, 0},
 385 +       {EPEVTCR0 + EPEVTCR_STRIDE * 5, 0},
 386 +       {EPEVTCR0 + EPEVTCR_STRIDE * 6, 0},
 387 +       {EPEVTCR0 + EPEVTCR_STRIDE * 7, 0},
 388 +       {EPEVTCR0 + EPEVTCR_STRIDE * 8, 0},
 389 +       {EPEVTCR0 + EPEVTCR_STRIDE * 9, 0xB0000001},
 390 +       /* EPCMPR (Event Processor Counter Compare Registers) */
 391 +       {EPCMPR0 + EPCMPR_STRIDE * 0, 0},
 392 +       {EPCMPR0 + EPCMPR_STRIDE * 1, 0},
 393 +       {EPCMPR0 + EPCMPR_STRIDE * 2, 0x000000FF},
 394 +       {EPCMPR0 + EPCMPR_STRIDE * 3, 0},
 395 +       {EPCMPR0 + EPCMPR_STRIDE * 4, 0x000000FF},
 396 +       {EPCMPR0 + EPCMPR_STRIDE * 5, 0x00000020},
 397 +       {EPCMPR0 + EPCMPR_STRIDE * 6, 0},
 398 +       {EPCMPR0 + EPCMPR_STRIDE * 7, 0},
 399 +       {EPCMPR0 + EPCMPR_STRIDE * 8, 0x000000FF},
 400 +       {EPCMPR0 + EPCMPR_STRIDE * 9, 0x000000FF},
 401 +       {EPCMPR0 + EPCMPR_STRIDE * 10, 0x000000FF},
 402 +       {EPCMPR0 + EPCMPR_STRIDE * 11, 0x000000FF},
 403 +       {EPCMPR0 + EPCMPR_STRIDE * 12, 0x000000FF},
 404 +       {EPCMPR0 + EPCMPR_STRIDE * 13, 0},
 405 +       {EPCMPR0 + EPCMPR_STRIDE * 14, 0x000000FF},
 406 +       {EPCMPR0 + EPCMPR_STRIDE * 15, 0x000000FF},
 407 +       /* EPCCR (Event Processor Counter Control Registers) */
 408 +       {EPCCR0 + EPCCR_STRIDE * 0, 0},
 409 +       {EPCCR0 + EPCCR_STRIDE * 1, 0},
 410 +       {EPCCR0 + EPCCR_STRIDE * 2, 0x92840000},
 411 +       {EPCCR0 + EPCCR_STRIDE * 3, 0},
 412 +       {EPCCR0 + EPCCR_STRIDE * 4, 0x92840000},
 413 +       {EPCCR0 + EPCCR_STRIDE * 5, 0x92840000},
 414 +       {EPCCR0 + EPCCR_STRIDE * 6, 0},
 415 +       {EPCCR0 + EPCCR_STRIDE * 7, 0},
 416 +       {EPCCR0 + EPCCR_STRIDE * 8, 0x92840000},
 417 +       {EPCCR0 + EPCCR_STRIDE * 9, 0x92840000},
 418 +       {EPCCR0 + EPCCR_STRIDE * 10, 0x92840000},
 419 +       {EPCCR0 + EPCCR_STRIDE * 11, 0x92840000},
 420 +       {EPCCR0 + EPCCR_STRIDE * 12, 0x92840000},
 421 +       {EPCCR0 + EPCCR_STRIDE * 13, 0},
 422 +       {EPCCR0 + EPCCR_STRIDE * 14, 0x92840000},
 423 +       {EPCCR0 + EPCCR_STRIDE * 15, 0x92840000},
 424 +       /* EPSMCR (Event Processor SCU Mux Control Registers) */
 425 +       {EPSMCR0 + EPSMCR_STRIDE * 0, 0},
 426 +       {EPSMCR0 + EPSMCR_STRIDE * 1, 0},
 427 +       {EPSMCR0 + EPSMCR_STRIDE * 2, 0x6C700000},
 428 +       {EPSMCR0 + EPSMCR_STRIDE * 3, 0x2F000000},
 429 +       {EPSMCR0 + EPSMCR_STRIDE * 4, 0x002F0000},
 430 +       {EPSMCR0 + EPSMCR_STRIDE * 5, 0x00002E00},
 431 +       {EPSMCR0 + EPSMCR_STRIDE * 6, 0x7C000000},
 432 +       {EPSMCR0 + EPSMCR_STRIDE * 7, 0x30000000},
 433 +       {EPSMCR0 + EPSMCR_STRIDE * 8, 0x64300000},
 434 +       {EPSMCR0 + EPSMCR_STRIDE * 9, 0x00003000},
 435 +       {EPSMCR0 + EPSMCR_STRIDE * 10, 0x65000030},
 436 +       {EPSMCR0 + EPSMCR_STRIDE * 11, 0x31740000},
 437 +       {EPSMCR0 + EPSMCR_STRIDE * 12, 0x7F000000},
 438 +       {EPSMCR0 + EPSMCR_STRIDE * 13, 0x00003100},
 439 +       {EPSMCR0 + EPSMCR_STRIDE * 14, 0x00000031},
 440 +       {EPSMCR0 + EPSMCR_STRIDE * 15, 0x76000000},
 441 +       /* EPACR (Event Processor Action Control Registers) */
 442 +       {EPACR0 + EPACR_STRIDE * 0, 0},
 443 +       {EPACR0 + EPACR_STRIDE * 1, 0},
 444 +       {EPACR0 + EPACR_STRIDE * 2, 0},
 445 +       {EPACR0 + EPACR_STRIDE * 3, 0x00000080},
 446 +       {EPACR0 + EPACR_STRIDE * 4, 0},
 447 +       {EPACR0 + EPACR_STRIDE * 5, 0x00000040},
 448 +       {EPACR0 + EPACR_STRIDE * 6, 0},
 449 +       {EPACR0 + EPACR_STRIDE * 7, 0},
 450 +       {EPACR0 + EPACR_STRIDE * 8, 0},
 451 +       {EPACR0 + EPACR_STRIDE * 9, 0x0000001C},
 452 +       {EPACR0 + EPACR_STRIDE * 10, 0x00000020},
 453 +       {EPACR0 + EPACR_STRIDE * 11, 0},
 454 +       {EPACR0 + EPACR_STRIDE * 12, 0x00000003},
 455 +       {EPACR0 + EPACR_STRIDE * 13, 0x06000000},
 456 +       {EPACR0 + EPACR_STRIDE * 14, 0x04000000},
 457 +       {EPACR0 + EPACR_STRIDE * 15, 0x02000000},
 458 +       /* EPIMCR (Event Processor Input Mux Control Registers) */
 459 +       {EPIMCR0 + EPIMCR_STRIDE * 0, 0},
 460 +       {EPIMCR0 + EPIMCR_STRIDE * 1, 0},
 461 +       {EPIMCR0 + EPIMCR_STRIDE * 2, 0},
 462 +       {EPIMCR0 + EPIMCR_STRIDE * 3, 0},
 463 +       {EPIMCR0 + EPIMCR_STRIDE * 4, 0x44000000},
 464 +       {EPIMCR0 + EPIMCR_STRIDE * 5, 0x40000000},
 465 +       {EPIMCR0 + EPIMCR_STRIDE * 6, 0},
 466 +       {EPIMCR0 + EPIMCR_STRIDE * 7, 0},
 467 +       {EPIMCR0 + EPIMCR_STRIDE * 8, 0},
 468 +       {EPIMCR0 + EPIMCR_STRIDE * 9, 0},
 469 +       {EPIMCR0 + EPIMCR_STRIDE * 10, 0},
 470 +       {EPIMCR0 + EPIMCR_STRIDE * 11, 0},
 471 +       {EPIMCR0 + EPIMCR_STRIDE * 12, 0x44000000},
 472 +       {EPIMCR0 + EPIMCR_STRIDE * 13, 0},
 473 +       {EPIMCR0 + EPIMCR_STRIDE * 14, 0},
 474 +       {EPIMCR0 + EPIMCR_STRIDE * 15, 0},
 475 +       {EPIMCR0 + EPIMCR_STRIDE * 16, 0x6A000000},
 476 +       {EPIMCR0 + EPIMCR_STRIDE * 17, 0},
 477 +       {EPIMCR0 + EPIMCR_STRIDE * 18, 0},
 478 +       {EPIMCR0 + EPIMCR_STRIDE * 19, 0},
 479 +       {EPIMCR0 + EPIMCR_STRIDE * 20, 0x48000000},
 480 +       {EPIMCR0 + EPIMCR_STRIDE * 21, 0},
 481 +       {EPIMCR0 + EPIMCR_STRIDE * 22, 0x6C000000},
 482 +       {EPIMCR0 + EPIMCR_STRIDE * 23, 0},
 483 +       {EPIMCR0 + EPIMCR_STRIDE * 24, 0},
 484 +       {EPIMCR0 + EPIMCR_STRIDE * 25, 0},
 485 +       {EPIMCR0 + EPIMCR_STRIDE * 26, 0},
 486 +       {EPIMCR0 + EPIMCR_STRIDE * 27, 0},
 487 +       {EPIMCR0 + EPIMCR_STRIDE * 28, 0x76000000},
 488 +       {EPIMCR0 + EPIMCR_STRIDE * 29, 0},
 489 +       {EPIMCR0 + EPIMCR_STRIDE * 30, 0},
 490 +       {EPIMCR0 + EPIMCR_STRIDE * 31, 0x76000000},
 491 +       /* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
 492 +       {EPXTRIGCR, 0x0000FFDF},
 493 +       /* end */
 494 +       {FSM_END_FLAG, 0},
 495 +};
 496 +
 497 +struct fsm_reg_vals npc_default_val[] = {
 498 +       /* NPC triggered Memory-Mapped Access Registers */
 499 +       {NCR, 0x80000000},
 500 +       {MCCR1, 0},
 501 +       {MCSR1, 0},
 502 +       {MMAR1LO, 0},
 503 +       {MMAR1HI, 0},
 504 +       {MMDR1, 0},
 505 +       {MCSR2, 0},
 506 +       {MMAR2LO, 0},
 507 +       {MMAR2HI, 0},
 508 +       {MMDR2, 0},
 509 +       {MCSR3, 0x80000000},
 510 +       {MMAR3LO, 0x000E2130},
 511 +       {MMAR3HI, 0x00030000},
 512 +       {MMDR3, 0x00020000},
 513 +       /* end */
 514 +       {FSM_END_FLAG, 0},
 515 +};
 516 +
 517 +/**
 518 + * fsl_fsm_setup - Configure EPU's FSM registers
 519 + * @base: the base address of registers
 520 + * @val: Pointer to address-value pairs for FSM registers
 521 + */
 522 +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val)
 523 +{
 524 +       struct fsm_reg_vals *data = val;
 525 +
 526 +       WARN_ON(!base || !data);
 527 +       while (data->offset != FSM_END_FLAG) {
 528 +               iowrite32be(data->value, base + data->offset);
 529 +               data++;
 530 +       }
 531 +}
 532 +
 533 +void fsl_epu_setup_default(void __iomem *epu_base)
 534 +{
 535 +       fsl_fsm_setup(epu_base, epu_default_val);
 536 +}
 537 +
 538 +void fsl_npc_setup_default(void __iomem *npc_base)
 539 +{
 540 +       fsl_fsm_setup(npc_base, npc_default_val);
 541 +}
 542 +
 543 +void fsl_epu_clean_default(void __iomem *epu_base)
 544 +{
 545 +       u32 offset;
 546 +
 547 +       /* follow the exact sequence to clear the registers */
 548 +       /* Clear EPACRn */
 549 +       for (offset = EPACR0; offset <= EPACR15; offset += EPACR_STRIDE)
 550 +               iowrite32be(0, epu_base + offset);
 551 +
 552 +       /* Clear EPEVTCRn */
 553 +       for (offset = EPEVTCR0; offset <= EPEVTCR9; offset += EPEVTCR_STRIDE)
 554 +               iowrite32be(0, epu_base + offset);
 555 +
 556 +       /* Clear EPGCR */
 557 +       iowrite32be(0, epu_base + EPGCR);
 558 +
 559 +       /* Clear EPSMCRn */
 560 +       for (offset = EPSMCR0; offset <= EPSMCR15; offset += EPSMCR_STRIDE)
 561 +               iowrite32be(0, epu_base + offset);
 562 +
 563 +       /* Clear EPCCRn */
 564 +       for (offset = EPCCR0; offset <= EPCCR31; offset += EPCCR_STRIDE)
 565 +               iowrite32be(0, epu_base + offset);
 566 +
 567 +       /* Clear EPCMPRn */
 568 +       for (offset = EPCMPR0; offset <= EPCMPR31; offset += EPCMPR_STRIDE)
 569 +               iowrite32be(0, epu_base + offset);
 570 +
 571 +       /* Clear EPCTRn */
 572 +       for (offset = EPCTR0; offset <= EPCTR31; offset += EPCTR_STRIDE)
 573 +               iowrite32be(0, epu_base + offset);
 574 +
 575 +       /* Clear EPIMCRn */
 576 +       for (offset = EPIMCR0; offset <= EPIMCR31; offset += EPIMCR_STRIDE)
 577 +               iowrite32be(0, epu_base + offset);
 578 +
 579 +       /* Clear EPXTRIGCRn */
 580 +       iowrite32be(0, epu_base + EPXTRIGCR);
 581 +
 582 +       /* Clear EPECRn */
 583 +       for (offset = EPECR0; offset <= EPECR15; offset += EPECR_STRIDE)
 584 +               iowrite32be(0, epu_base + offset);
 585 +}
 586 --- /dev/null
 587 +++ b/drivers/soc/fsl/sleep_fsm.h
 588 @@ -0,0 +1,130 @@
 589 +/*
 590 + * deep sleep FSM (finite-state machine) configuration
 591 + *
 592 + * Copyright 2018 NXP
 593 + *
 594 + * Redistribution and use in source and binary forms, with or without
 595 + * modification, are permitted provided that the following conditions are met:
 596 + *     * Redistributions of source code must retain the above copyright
 597 + *      notice, this list of conditions and the following disclaimer.
 598 + *     * Redistributions in binary form must reproduce the above copyright
 599 + *      notice, this list of conditions and the following disclaimer in the
 600 + *      documentation and/or other materials provided with the distribution.
 601 + *     * Neither the name of the above-listed copyright holders nor the
 602 + *      names of any contributors may be used to endorse or promote products
 603 + *      derived from this software without specific prior written permission.
 604 + *
 605 + *
 606 + * ALTERNATIVELY, this software may be distributed under the terms of the
 607 + * GNU General Public License ("GPL") as published by the Free Software
 608 + * Foundation, either version 2 of that License or (at your option) any
 609 + * later version.
 610 + *
 611 + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 612 + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 613 + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
 614 + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE
 615 + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 616 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 617 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 618 + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 619 + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 620 + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 621 + * POSSIBILITY OF SUCH DAMAGE.
 622 + */
 623 +
 624 +#ifndef _FSL_SLEEP_FSM_H
 625 +#define _FSL_SLEEP_FSM_H
 626 +
 627 +#define FSL_STRIDE_4B  4
 628 +#define FSL_STRIDE_8B  8
 629 +
 630 +/* End flag */
 631 +#define FSM_END_FLAG           0xFFFFFFFFUL
 632 +
 633 +/* Block offsets */
 634 +#define RCPM_BLOCK_OFFSET      0x00022000
 635 +#define EPU_BLOCK_OFFSET       0x00000000
 636 +#define NPC_BLOCK_OFFSET       0x00001000
 637 +
 638 +/* EPGCR (Event Processor Global Control Register) */
 639 +#define EPGCR          0x000
 640 +
 641 +/* EPEVTCR0-9 (Event Processor EVT Pin Control Registers) */
 642 +#define EPEVTCR0       0x050
 643 +#define EPEVTCR9       0x074
 644 +#define EPEVTCR_STRIDE FSL_STRIDE_4B
 645 +
 646 +/* EPXTRIGCR (Event Processor Crosstrigger Control Register) */
 647 +#define EPXTRIGCR      0x090
 648 +
 649 +/* EPIMCR0-31 (Event Processor Input Mux Control Registers) */
 650 +#define EPIMCR0                0x100
 651 +#define EPIMCR31       0x17C
 652 +#define EPIMCR_STRIDE  FSL_STRIDE_4B
 653 +
 654 +/* EPSMCR0-15 (Event Processor SCU Mux Control Registers) */
 655 +#define EPSMCR0                0x200
 656 +#define EPSMCR15       0x278
 657 +#define EPSMCR_STRIDE  FSL_STRIDE_8B
 658 +
 659 +/* EPECR0-15 (Event Processor Event Control Registers) */
 660 +#define EPECR0         0x300
 661 +#define EPECR15                0x33C
 662 +#define EPECR_STRIDE   FSL_STRIDE_4B
 663 +
 664 +/* EPACR0-15 (Event Processor Action Control Registers) */
 665 +#define EPACR0         0x400
 666 +#define EPACR15                0x43C
 667 +#define EPACR_STRIDE   FSL_STRIDE_4B
 668 +
 669 +/* EPCCRi0-15 (Event Processor Counter Control Registers) */
 670 +#define EPCCR0         0x800
 671 +#define EPCCR15                0x83C
 672 +#define EPCCR31                0x87C
 673 +#define EPCCR_STRIDE   FSL_STRIDE_4B
 674 +
 675 +/* EPCMPR0-15 (Event Processor Counter Compare Registers) */
 676 +#define EPCMPR0                0x900
 677 +#define EPCMPR15       0x93C
 678 +#define EPCMPR31       0x97C
 679 +#define EPCMPR_STRIDE  FSL_STRIDE_4B
 680 +
 681 +/* EPCTR0-31 (Event Processor Counter Register) */
 682 +#define EPCTR0         0xA00
 683 +#define EPCTR31                0xA7C
 684 +#define EPCTR_STRIDE   FSL_STRIDE_4B
 685 +
 686 +/* NPC triggered Memory-Mapped Access Registers */
 687 +#define NCR            0x000
 688 +#define MCCR1          0x0CC
 689 +#define MCSR1          0x0D0
 690 +#define MMAR1LO                0x0D4
 691 +#define MMAR1HI                0x0D8
 692 +#define MMDR1          0x0DC
 693 +#define MCSR2          0x0E0
 694 +#define MMAR2LO                0x0E4
 695 +#define MMAR2HI                0x0E8
 696 +#define MMDR2          0x0EC
 697 +#define MCSR3          0x0F0
 698 +#define MMAR3LO                0x0F4
 699 +#define MMAR3HI                0x0F8
 700 +#define MMDR3          0x0FC
 701 +
 702 +/* RCPM Core State Action Control Register 0 */
 703 +#define CSTTACR0       0xB00
 704 +
 705 +/* RCPM Core Group 1 Configuration Register 0 */
 706 +#define CG1CR0         0x31C
 707 +
 708 +struct fsm_reg_vals {
 709 +       u32 offset;
 710 +       u32 value;
 711 +};
 712 +
 713 +void fsl_fsm_setup(void __iomem *base, struct fsm_reg_vals *val);
 714 +void fsl_epu_setup_default(void __iomem *epu_base);
 715 +void fsl_npc_setup_default(void __iomem *npc_base);
 716 +void fsl_epu_clean_default(void __iomem *epu_base);
 717 +
 718 +#endif /* _FSL_SLEEP_FSM_H */