target/linux/layerscape/patches-5.4/302-dts-0004-arm64-dts-ls1012a-Add-more-nodes-to-LS1012A-FRWY-boa.patch

   1 From 9ba5a56b7241c46aa47544f8414ad1f3d445f3c1 Mon Sep 17 00:00:00 2001
   2 From: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
   3 Date: Mon, 7 May 2018 11:52:04 +0530
   4 Subject: [PATCH] arm64: dts: ls1012a: Add more nodes to LS1012A-FRWY board
   5  support
   6
   7 LS1012A-FRWY is a different design from LS1012A-FRDM,
   8 but has some common SoC features. Key feature on this
   9 board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
  10 QuadSPI, Audio, UART.
  11
  12 Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
  13 Signed-off-by: Li Yang <leoyang.li@nxp.com>
  14 ---
  15  arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts | 118 +++++++++++++++++++++
  16  1 file changed, 118 insertions(+)
  17
  18 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
  19 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts
  20 @@ -14,6 +14,58 @@
  21  / {
  22         model = "LS1012A FRWY Board";
  23         compatible = "fsl,ls1012a-frwy", "fsl,ls1012a";
  24 +
  25 +       aliases {
  26 +               ethernet0 = &pfe_mac0;
  27 +               ethernet1 = &pfe_mac1;
  28 +       };
  29 +
  30 +       sys_mclk: clock-mclk {
  31 +               compatible = "fixed-clock";
  32 +               #clock-cells = <0>;
  33 +               clock-frequency = <25000000>;
  34 +       };
  35 +
  36 +       reg_1p8v: regulator-1p8v {
  37 +               compatible = "regulator-fixed";
  38 +               regulator-name = "1P8V";
  39 +               regulator-min-microvolt = <1800000>;
  40 +               regulator-max-microvolt = <1800000>;
  41 +               regulator-always-on;
  42 +       };
  43 +
  44 +       sound {
  45 +               compatible = "simple-audio-card";
  46 +               simple-audio-card,format = "i2s";
  47 +               simple-audio-card,widgets =
  48 +                       "Microphone", "Microphone Jack",
  49 +                       "Headphone", "Headphone Jack",
  50 +                       "Speaker", "Speaker Ext",
  51 +                       "Line", "Line In Jack";
  52 +               simple-audio-card,routing =
  53 +                       "MIC_IN", "Microphone Jack",
  54 +                       "Microphone Jack", "Mic Bias",
  55 +                       "LINE_IN", "Line In Jack",
  56 +                       "Headphone Jack", "HP_OUT",
  57 +                       "Speaker Ext", "LINE_OUT";
  58 +
  59 +               simple-audio-card,cpu {
  60 +                       sound-dai = <&sai2>;
  61 +                       frame-master;
  62 +                       bitclock-master;
  63 +               };
  64 +
  65 +               simple-audio-card,codec {
  66 +                       sound-dai = <&codec>;
  67 +                       frame-master;
  68 +                       bitclock-master;
  69 +                       system-clock-frequency = <25000000>;
  70 +               };
  71 +       };
  72 +};
  73 +
  74 +&pcie {
  75 +       status = "okay";
  76  };
  77
  78  &duart0 {
  79 @@ -22,4 +74,70 @@
  80
  81  &i2c0 {
  82         status = "okay";
  83 +
  84 +       codec: sgtl5000@a {
  85 +               compatible = "fsl,sgtl5000";
  86 +               #sound-dai-cells = <0>;
  87 +               reg = <0xa>;
  88 +               VDDA-supply = <&reg_1p8v>;
  89 +               VDDIO-supply = <&reg_1p8v>;
  90 +               clocks = <&sys_mclk>;
  91 +       };
  92 +};
  93 +
  94 +&qspi {
  95 +       num-cs = <1>;
  96 +       bus-num = <0>;
  97 +       status = "okay";
  98 +
  99 +       qflash0: w25q16dw@0 {
 100 +               compatible = "spansion,m25p80";
 101 +               #address-cells = <1>;
 102 +               #size-cells = <1>;
 103 +               m25p,fast-read;
 104 +               spi-max-frequency = <20000000>;
 105 +               reg = <0>;
 106 +       };
 107 +};
 108 +
 109 +&pfe {
 110 +       status = "okay";
 111 +       #address-cells = <1>;
 112 +       #size-cells = <0>;
 113 +
 114 +       ethernet@0 {
 115 +               compatible = "fsl,pfe-gemac-port";
 116 +               #address-cells = <1>;
 117 +               #size-cells = <0>;
 118 +               reg = <0x0>;    /* GEM_ID */
 119 +               fsl,gemac-bus-id = <0x0>;       /* BUS_ID */
 120 +               fsl,gemac-phy-id = <0x2>;       /* PHY_ID */
 121 +               fsl,mdio-mux-val = <0x0>;
 122 +               phy-mode = "sgmii";
 123 +               fsl,pfe-phy-if-flags = <0x0>;
 124 +
 125 +               mdio@0 {
 126 +                       reg = <0x1>; /* enabled/disabled */
 127 +               };
 128 +       };
 129 +
 130 +       ethernet@1 {
 131 +               compatible = "fsl,pfe-gemac-port";
 132 +               #address-cells = <1>;
 133 +               #size-cells = <0>;
 134 +               reg = <0x1>;    /* GEM_ID */
 135 +               fsl,gemac-bus-id = <0x1>;       /* BUS_ID */
 136 +               fsl,gemac-phy-id = <0x1>;       /* PHY_ID */
 137 +               fsl,mdio-mux-val = <0x0>;
 138 +               phy-mode = "sgmii";
 139 +               fsl,pfe-phy-if-flags = <0x0>;
 140 +
 141 +               mdio@0 {
 142 +                       reg = <0x0>; /* enabled/disabled */
 143 +               };
 144 +       };
 145 +};
 146 +
 147 +&sai2 {
 148 +       status = "okay";
 149  };