target/linux/layerscape/patches-5.4/302-dts-0075-arm64-dts-fsl-ls1028a-Enable-switch-PHYs-on-RDB.patch

   1 From aafb63a926b790b64a5ed83377f07b90ec7ba7c0 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Manoil <claudiu.manoil@nxp.com>
   3 Date: Thu, 20 Jun 2019 19:53:55 +0300
   4 Subject: [PATCH] arm64: dts: fsl: ls1028a: Enable switch PHYs on RDB
   5
   6 Just link the switch PHY nodes to the central MDIO
   7 controller PCIe endpoint node on ls1028 (implemented
   8 as PF3) so that PHYs are configurable via MDIO.
   9
  10 Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
  11 ---
  12  arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 39 +++++++++++++++++++++++
  13  1 file changed, 39 insertions(+)
  14
  15 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
  16 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
  17 @@ -208,6 +208,45 @@
  18         status = "disabled";
  19  };
  20
  21 +&enetc_mdio_pf3 {
  22 +       qsgmii_phy1: ethernet-phy@4 {
  23 +               reg = <0x10>;
  24 +       };
  25 +
  26 +       qsgmii_phy2: ethernet-phy@5 {
  27 +               reg = <0x11>;
  28 +       };
  29 +
  30 +       qsgmii_phy3: ethernet-phy@6 {
  31 +               reg = <0x12>;
  32 +       };
  33 +
  34 +       qsgmii_phy4: ethernet-phy@7 {
  35 +               reg = <0x13>;
  36 +       };
  37 +};
  38 +
  39 +/* l2switch ports */
  40 +&switch_port0 {
  41 +       phy-handle = <&qsgmii_phy1>;
  42 +       phy-connection-type = "qsgmii";
  43 +};
  44 +
  45 +&switch_port1 {
  46 +       phy-handle = <&qsgmii_phy2>;
  47 +       phy-connection-type = "qsgmii";
  48 +};
  49 +
  50 +&switch_port2 {
  51 +       phy-handle = <&qsgmii_phy3>;
  52 +       phy-connection-type = "qsgmii";
  53 +};
  54 +
  55 +&switch_port3 {
  56 +       phy-handle = <&qsgmii_phy4>;
  57 +       phy-connection-type = "qsgmii";
  58 +};
  59 +
  60  &sai4 {
  61         status = "okay";
  62  };