target/linux/layerscape/patches-5.4/701-net-0228-enetc-Make-mdio-accessors-more-generic.patch

   1 From 141fc778365ac0f1584ade0fd419af871e681646 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Manoil <claudiu.manoil@nxp.com>
   3 Date: Mon, 12 Aug 2019 20:26:42 +0300
   4 Subject: [PATCH] enetc: Make mdio accessors more generic
   5
   6 Refactoring needed to support multiple MDIO buses.
   7 'mdio_base' - MDIO registers base address - is being parameterized.
   8 The MDIO accessors are made more generic to be able to work with
   9 different MDIO register bases.
  10 Some includes get cleaned up in the process.
  11
  12 Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com>
  13 ---
  14  drivers/net/ethernet/freescale/enetc/enetc_hw.h    |  1 +
  15  drivers/net/ethernet/freescale/enetc/enetc_mdio.c  | 60 +++++++++++++---------
  16  drivers/net/ethernet/freescale/enetc/enetc_mdio.h  |  2 +-
  17  .../net/ethernet/freescale/enetc/enetc_pci_mdio.c  |  2 +
  18  4 files changed, 39 insertions(+), 26 deletions(-)
  19
  20 --- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
  21 +++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
  22 @@ -198,6 +198,7 @@ enum enetc_bdr_type {TX, RX};
  23  #define ENETC_PFPMR            0x1900
  24  #define ENETC_PFPMR_PMACE      BIT(1)
  25  #define ENETC_PFPMR_MWLM       BIT(0)
  26 +#define ENETC_EMDIO_BASE       0x1c00
  27  #define ENETC_PSIUMHFR0(n, err)        (((err) ? 0x1d08 : 0x1d00) + (n) * 0x10)
  28  #define ENETC_PSIUMHFR1(n)     (0x1d04 + (n) * 0x10)
  29  #define ENETC_PSIMMHFR0(n, err)        (((err) ? 0x1d00 : 0x1d08) + (n) * 0x10)
  30 --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
  31 +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.c
  32 @@ -6,19 +6,30 @@
  33  #include <linux/iopoll.h>
  34  #include <linux/of.h>
  35
  36 +#include "enetc_pf.h"
  37  #include "enetc_mdio.h"
  38
  39 -#define        ENETC_MDIO_REG_OFFSET   0x1c00
  40  #define        ENETC_MDIO_CFG  0x0     /* MDIO configuration and status */
  41  #define        ENETC_MDIO_CTL  0x4     /* MDIO control */
  42  #define        ENETC_MDIO_DATA 0x8     /* MDIO data */
  43  #define        ENETC_MDIO_ADDR 0xc     /* MDIO address */
  44
  45 -#define enetc_mdio_rd(hw, off) \
  46 -       enetc_port_rd(hw, ENETC_##off + ENETC_MDIO_REG_OFFSET)
  47 -#define enetc_mdio_wr(hw, off, val) \
  48 -       enetc_port_wr(hw, ENETC_##off + ENETC_MDIO_REG_OFFSET, val)
  49 -#define enetc_mdio_rd_reg(off) enetc_mdio_rd(hw, off)
  50 +static inline u32 _enetc_mdio_rd(struct enetc_mdio_priv *mdio_priv, int off)
  51 +{
  52 +       return enetc_port_rd(mdio_priv->hw, mdio_priv->mdio_base + off);
  53 +}
  54 +
  55 +static inline void _enetc_mdio_wr(struct enetc_mdio_priv *mdio_priv, int off,
  56 +                                 u32 val)
  57 +{
  58 +       enetc_port_wr(mdio_priv->hw, mdio_priv->mdio_base + off, val);
  59 +}
  60 +
  61 +#define enetc_mdio_rd(mdio_priv, off) \
  62 +       _enetc_mdio_rd(mdio_priv, ENETC_##off)
  63 +#define enetc_mdio_wr(mdio_priv, off, val) \
  64 +       _enetc_mdio_wr(mdio_priv, ENETC_##off, val)
  65 +#define enetc_mdio_rd_reg(off) enetc_mdio_rd(mdio_priv, off)
  66
  67  #define ENETC_MDC_DIV          258
  68
  69 @@ -35,7 +46,7 @@
  70  #define MDIO_DATA(x)           ((x) & 0xffff)
  71
  72  #define TIMEOUT        1000
  73 -static int enetc_mdio_wait_complete(struct enetc_hw *hw)
  74 +static int enetc_mdio_wait_complete(struct enetc_mdio_priv *mdio_priv)
  75  {
  76         u32 val;
  77
  78 @@ -46,7 +57,6 @@ static int enetc_mdio_wait_complete(stru
  79  int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value)
  80  {
  81         struct enetc_mdio_priv *mdio_priv = bus->priv;
  82 -       struct enetc_hw *hw = mdio_priv->hw;
  83         u32 mdio_ctl, mdio_cfg;
  84         u16 dev_addr;
  85         int ret;
  86 @@ -61,29 +71,29 @@ int enetc_mdio_write(struct mii_bus *bus
  87                 mdio_cfg &= ~MDIO_CFG_ENC45;
  88         }
  89
  90 -       enetc_mdio_wr(hw, MDIO_CFG, mdio_cfg);
  91 +       enetc_mdio_wr(mdio_priv, MDIO_CFG, mdio_cfg);
  92
  93 -       ret = enetc_mdio_wait_complete(hw);
  94 +       ret = enetc_mdio_wait_complete(mdio_priv);
  95         if (ret)
  96                 return ret;
  97
  98         /* set port and dev addr */
  99         mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
 100 -       enetc_mdio_wr(hw, MDIO_CTL, mdio_ctl);
 101 +       enetc_mdio_wr(mdio_priv, MDIO_CTL, mdio_ctl);
 102
 103         /* set the register address */
 104         if (regnum & MII_ADDR_C45) {
 105 -               enetc_mdio_wr(hw, MDIO_ADDR, regnum & 0xffff);
 106 +               enetc_mdio_wr(mdio_priv, MDIO_ADDR, regnum & 0xffff);
 107
 108 -               ret = enetc_mdio_wait_complete(hw);
 109 +               ret = enetc_mdio_wait_complete(mdio_priv);
 110                 if (ret)
 111                         return ret;
 112         }
 113
 114         /* write the value */
 115 -       enetc_mdio_wr(hw, MDIO_DATA, MDIO_DATA(value));
 116 +       enetc_mdio_wr(mdio_priv, MDIO_DATA, MDIO_DATA(value));
 117
 118 -       ret = enetc_mdio_wait_complete(hw);
 119 +       ret = enetc_mdio_wait_complete(mdio_priv);
 120         if (ret)
 121                 return ret;
 122
 123 @@ -93,7 +103,6 @@ int enetc_mdio_write(struct mii_bus *bus
 124  int enetc_mdio_read(struct mii_bus *bus, int phy_id, int regnum)
 125  {
 126         struct enetc_mdio_priv *mdio_priv = bus->priv;
 127 -       struct enetc_hw *hw = mdio_priv->hw;
 128         u32 mdio_ctl, mdio_cfg;
 129         u16 dev_addr, value;
 130         int ret;
 131 @@ -107,41 +116,41 @@ int enetc_mdio_read(struct mii_bus *bus,
 132                 mdio_cfg &= ~MDIO_CFG_ENC45;
 133         }
 134
 135 -       enetc_mdio_wr(hw, MDIO_CFG, mdio_cfg);
 136 +       enetc_mdio_wr(mdio_priv, MDIO_CFG, mdio_cfg);
 137
 138 -       ret = enetc_mdio_wait_complete(hw);
 139 +       ret = enetc_mdio_wait_complete(mdio_priv);
 140         if (ret)
 141                 return ret;
 142
 143         /* set port and device addr */
 144         mdio_ctl = MDIO_CTL_PORT_ADDR(phy_id) | MDIO_CTL_DEV_ADDR(dev_addr);
 145 -       enetc_mdio_wr(hw, MDIO_CTL, mdio_ctl);
 146 +       enetc_mdio_wr(mdio_priv, MDIO_CTL, mdio_ctl);
 147
 148         /* set the register address */
 149         if (regnum & MII_ADDR_C45) {
 150 -               enetc_mdio_wr(hw, MDIO_ADDR, regnum & 0xffff);
 151 +               enetc_mdio_wr(mdio_priv, MDIO_ADDR, regnum & 0xffff);
 152
 153 -               ret = enetc_mdio_wait_complete(hw);
 154 +               ret = enetc_mdio_wait_complete(mdio_priv);
 155                 if (ret)
 156                         return ret;
 157         }
 158
 159         /* initiate the read */
 160 -       enetc_mdio_wr(hw, MDIO_CTL, mdio_ctl | MDIO_CTL_READ);
 161 +       enetc_mdio_wr(mdio_priv, MDIO_CTL, mdio_ctl | MDIO_CTL_READ);
 162
 163 -       ret = enetc_mdio_wait_complete(hw);
 164 +       ret = enetc_mdio_wait_complete(mdio_priv);
 165         if (ret)
 166                 return ret;
 167
 168         /* return all Fs if nothing was there */
 169 -       if (enetc_mdio_rd(hw, MDIO_CFG) & MDIO_CFG_RD_ER) {
 170 +       if (enetc_mdio_rd(mdio_priv, MDIO_CFG) & MDIO_CFG_RD_ER) {
 171                 dev_dbg(&bus->dev,
 172                         "Error while reading PHY%d reg at %d.%hhu\n",
 173                         phy_id, dev_addr, regnum);
 174                 return 0xffff;
 175         }
 176
 177 -       value = enetc_mdio_rd(hw, MDIO_DATA) & 0xffff;
 178 +       value = enetc_mdio_rd(mdio_priv, MDIO_DATA) & 0xffff;
 179
 180         return value;
 181  }
 182 @@ -164,6 +173,7 @@ int enetc_mdio_probe(struct enetc_pf *pf
 183         bus->parent = dev;
 184         mdio_priv = bus->priv;
 185         mdio_priv->hw = &pf->si->hw;
 186 +       mdio_priv->mdio_base = ENETC_EMDIO_BASE;
 187         snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
 188
 189         np = of_get_child_by_name(dev->of_node, "mdio");
 190 --- a/drivers/net/ethernet/freescale/enetc/enetc_mdio.h
 191 +++ b/drivers/net/ethernet/freescale/enetc/enetc_mdio.h
 192 @@ -2,10 +2,10 @@
 193  /* Copyright 2019 NXP */
 194
 195  #include <linux/phy.h>
 196 -#include "enetc_pf.h"
 197
 198  struct enetc_mdio_priv {
 199         struct enetc_hw *hw;
 200 +       int mdio_base;
 201  };
 202
 203  int enetc_mdio_write(struct mii_bus *bus, int phy_id, int regnum, u16 value);
 204 --- a/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c
 205 +++ b/drivers/net/ethernet/freescale/enetc/enetc_pci_mdio.c
 206 @@ -1,6 +1,7 @@
 207  // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
 208  /* Copyright 2019 NXP */
 209  #include <linux/of_mdio.h>
 210 +#include "enetc_pf.h"
 211  #include "enetc_mdio.h"
 212
 213  #define ENETC_MDIO_DEV_ID      0xee01
 214 @@ -31,6 +32,7 @@ static int enetc_pci_mdio_probe(struct p
 215         bus->parent = dev;
 216         mdio_priv = bus->priv;
 217         mdio_priv->hw = hw;
 218 +       mdio_priv->mdio_base = ENETC_EMDIO_BASE;
 219         snprintf(bus->id, MII_BUS_ID_SIZE, "%s", dev_name(dev));
 220
 221         pcie_flr(pdev);