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layerscape: add patches-5.4
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 701-net-0285-staging-fsl_ppfe-eth-header-files-for-pfe-driver.patch
1 From d9bd3a5f795f45fd6847f080231e1e760004dca9 Mon Sep 17 00:00:00 2001
2 From: Calvin Johnson <calvin.johnson@nxp.com>
3 Date: Sat, 16 Sep 2017 14:21:37 +0530
4 Subject: [PATCH] staging: fsl_ppfe/eth: header files for pfe driver
5
6 This patch has all pfe header files.
7
8 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
9 Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
10 ---
11 drivers/staging/fsl_ppfe/include/pfe/cbus.h | 78 +++++
12 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h | 55 +++
13 .../staging/fsl_ppfe/include/pfe/cbus/class_csr.h | 289 ++++++++++++++++
14 .../staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h | 242 ++++++++++++++
15 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h | 86 +++++
16 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h | 100 ++++++
17 .../staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h | 50 +++
18 .../staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h | 168 ++++++++++
19 .../staging/fsl_ppfe/include/pfe/cbus/util_csr.h | 61 ++++
20 drivers/staging/fsl_ppfe/include/pfe/pfe.h | 372 +++++++++++++++++++++
21 drivers/staging/fsl_ppfe/pfe_ctrl.h | 112 +++++++
22 drivers/staging/fsl_ppfe/pfe_debugfs.h | 25 ++
23 drivers/staging/fsl_ppfe/pfe_eth.h | 184 ++++++++++
24 drivers/staging/fsl_ppfe/pfe_firmware.h | 32 ++
25 drivers/staging/fsl_ppfe/pfe_hif.h | 211 ++++++++++++
26 drivers/staging/fsl_ppfe/pfe_hif_lib.h | 239 +++++++++++++
27 drivers/staging/fsl_ppfe/pfe_hw.h | 27 ++
28 drivers/staging/fsl_ppfe/pfe_mod.h | 112 +++++++
29 drivers/staging/fsl_ppfe/pfe_perfmon.h | 38 +++
30 drivers/staging/fsl_ppfe/pfe_sysfs.h | 29 ++
31 20 files changed, 2510 insertions(+)
32 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus.h
33 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
34 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
35 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
36 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
37 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
38 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
39 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
40 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
41 create mode 100644 drivers/staging/fsl_ppfe/include/pfe/pfe.h
42 create mode 100644 drivers/staging/fsl_ppfe/pfe_ctrl.h
43 create mode 100644 drivers/staging/fsl_ppfe/pfe_debugfs.h
44 create mode 100644 drivers/staging/fsl_ppfe/pfe_eth.h
45 create mode 100644 drivers/staging/fsl_ppfe/pfe_firmware.h
46 create mode 100644 drivers/staging/fsl_ppfe/pfe_hif.h
47 create mode 100644 drivers/staging/fsl_ppfe/pfe_hif_lib.h
48 create mode 100644 drivers/staging/fsl_ppfe/pfe_hw.h
49 create mode 100644 drivers/staging/fsl_ppfe/pfe_mod.h
50 create mode 100644 drivers/staging/fsl_ppfe/pfe_perfmon.h
51 create mode 100644 drivers/staging/fsl_ppfe/pfe_sysfs.h
52
53 --- /dev/null
54 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus.h
55 @@ -0,0 +1,78 @@
56 +/*
57 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
58 + * Copyright 2017 NXP
59 + *
60 + * This program is free software; you can redistribute it and/or modify
61 + * it under the terms of the GNU General Public License as published by
62 + * the Free Software Foundation; either version 2 of the License, or
63 + * (at your option) any later version.
64 + *
65 + * This program is distributed in the hope that it will be useful,
66 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
67 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
68 + * GNU General Public License for more details.
69 + *
70 + * You should have received a copy of the GNU General Public License
71 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
72 + */
73 +
74 +#ifndef _CBUS_H_
75 +#define _CBUS_H_
76 +
77 +#define EMAC1_BASE_ADDR (CBUS_BASE_ADDR + 0x200000)
78 +#define EGPI1_BASE_ADDR (CBUS_BASE_ADDR + 0x210000)
79 +#define EMAC2_BASE_ADDR (CBUS_BASE_ADDR + 0x220000)
80 +#define EGPI2_BASE_ADDR (CBUS_BASE_ADDR + 0x230000)
81 +#define BMU1_BASE_ADDR (CBUS_BASE_ADDR + 0x240000)
82 +#define BMU2_BASE_ADDR (CBUS_BASE_ADDR + 0x250000)
83 +#define ARB_BASE_ADDR (CBUS_BASE_ADDR + 0x260000)
84 +#define DDR_CONFIG_BASE_ADDR (CBUS_BASE_ADDR + 0x270000)
85 +#define HIF_BASE_ADDR (CBUS_BASE_ADDR + 0x280000)
86 +#define HGPI_BASE_ADDR (CBUS_BASE_ADDR + 0x290000)
87 +#define LMEM_BASE_ADDR (CBUS_BASE_ADDR + 0x300000)
88 +#define LMEM_SIZE 0x10000
89 +#define LMEM_END (LMEM_BASE_ADDR + LMEM_SIZE)
90 +#define TMU_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x310000)
91 +#define CLASS_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x320000)
92 +#define HIF_NOCPY_BASE_ADDR (CBUS_BASE_ADDR + 0x350000)
93 +#define UTIL_CSR_BASE_ADDR (CBUS_BASE_ADDR + 0x360000)
94 +#define CBUS_GPT_BASE_ADDR (CBUS_BASE_ADDR + 0x370000)
95 +
96 +/*
97 + * defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
98 + * XXX_MEM_ACCESS_ADDR register bit definitions.
99 + */
100 +#define PE_MEM_ACCESS_WRITE BIT(31) /* Internal Memory Write. */
101 +#define PE_MEM_ACCESS_IMEM BIT(15)
102 +#define PE_MEM_ACCESS_DMEM BIT(16)
103 +
104 +/* Byte Enables of the Internal memory access. These are interpred in BE */
105 +#define PE_MEM_ACCESS_BYTE_ENABLE(offset, size) \
106 + ({ typeof(size) size_ = (size); \
107 + (((BIT(size_) - 1) << (4 - (offset) - (size_))) & 0xf) << 24; })
108 +
109 +#include "cbus/emac_mtip.h"
110 +#include "cbus/gpi.h"
111 +#include "cbus/bmu.h"
112 +#include "cbus/hif.h"
113 +#include "cbus/tmu_csr.h"
114 +#include "cbus/class_csr.h"
115 +#include "cbus/hif_nocpy.h"
116 +#include "cbus/util_csr.h"
117 +
118 +/* PFE cores states */
119 +#define CORE_DISABLE 0x00000000
120 +#define CORE_ENABLE 0x00000001
121 +#define CORE_SW_RESET 0x00000002
122 +
123 +/* LMEM defines */
124 +#define LMEM_HDR_SIZE 0x0010
125 +#define LMEM_BUF_SIZE_LN2 0x7
126 +#define LMEM_BUF_SIZE BIT(LMEM_BUF_SIZE_LN2)
127 +
128 +/* DDR defines */
129 +#define DDR_HDR_SIZE 0x0100
130 +#define DDR_BUF_SIZE_LN2 0xb
131 +#define DDR_BUF_SIZE BIT(DDR_BUF_SIZE_LN2)
132 +
133 +#endif /* _CBUS_H_ */
134 --- /dev/null
135 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/bmu.h
136 @@ -0,0 +1,55 @@
137 +/*
138 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
139 + * Copyright 2017 NXP
140 + *
141 + * This program is free software; you can redistribute it and/or modify
142 + * it under the terms of the GNU General Public License as published by
143 + * the Free Software Foundation; either version 2 of the License, or
144 + * (at your option) any later version.
145 + *
146 + * This program is distributed in the hope that it will be useful,
147 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
148 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
149 + * GNU General Public License for more details.
150 + *
151 + * You should have received a copy of the GNU General Public License
152 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
153 + */
154 +
155 +#ifndef _BMU_H_
156 +#define _BMU_H_
157 +
158 +#define BMU_VERSION 0x000
159 +#define BMU_CTRL 0x004
160 +#define BMU_UCAST_CONFIG 0x008
161 +#define BMU_UCAST_BASE_ADDR 0x00c
162 +#define BMU_BUF_SIZE 0x010
163 +#define BMU_BUF_CNT 0x014
164 +#define BMU_THRES 0x018
165 +#define BMU_INT_SRC 0x020
166 +#define BMU_INT_ENABLE 0x024
167 +#define BMU_ALLOC_CTRL 0x030
168 +#define BMU_FREE_CTRL 0x034
169 +#define BMU_FREE_ERR_ADDR 0x038
170 +#define BMU_CURR_BUF_CNT 0x03c
171 +#define BMU_MCAST_CNT 0x040
172 +#define BMU_MCAST_ALLOC_CTRL 0x044
173 +#define BMU_REM_BUF_CNT 0x048
174 +#define BMU_LOW_WATERMARK 0x050
175 +#define BMU_HIGH_WATERMARK 0x054
176 +#define BMU_INT_MEM_ACCESS 0x100
177 +
178 +struct BMU_CFG {
179 + unsigned long baseaddr;
180 + u32 count;
181 + u32 size;
182 + u32 low_watermark;
183 + u32 high_watermark;
184 +};
185 +
186 +#define BMU1_BUF_SIZE LMEM_BUF_SIZE_LN2
187 +#define BMU2_BUF_SIZE DDR_BUF_SIZE_LN2
188 +
189 +#define BMU2_MCAST_ALLOC_CTRL (BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL)
190 +
191 +#endif /* _BMU_H_ */
192 --- /dev/null
193 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/class_csr.h
194 @@ -0,0 +1,289 @@
195 +/*
196 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
197 + * Copyright 2017 NXP
198 + *
199 + * This program is free software; you can redistribute it and/or modify
200 + * it under the terms of the GNU General Public License as published by
201 + * the Free Software Foundation; either version 2 of the License, or
202 + * (at your option) any later version.
203 + *
204 + * This program is distributed in the hope that it will be useful,
205 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
206 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
207 + * GNU General Public License for more details.
208 + *
209 + * You should have received a copy of the GNU General Public License
210 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
211 + */
212 +
213 +#ifndef _CLASS_CSR_H_
214 +#define _CLASS_CSR_H_
215 +
216 +/* @file class_csr.h.
217 + * class_csr - block containing all the classifier control and status register.
218 + * Mapped on CBUS and accessible from all PE's and ARM.
219 + */
220 +#define CLASS_VERSION (CLASS_CSR_BASE_ADDR + 0x000)
221 +#define CLASS_TX_CTRL (CLASS_CSR_BASE_ADDR + 0x004)
222 +#define CLASS_INQ_PKTPTR (CLASS_CSR_BASE_ADDR + 0x010)
223 +
224 +/* (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
225 +#define CLASS_HDR_SIZE (CLASS_CSR_BASE_ADDR + 0x014)
226 +
227 +/* LMEM header size for the Classifier block.\ Data in the LMEM
228 + * is written from this offset.
229 + */
230 +#define CLASS_HDR_SIZE_LMEM(off) ((off) & 0x3f)
231 +
232 +/* DDR header size for the Classifier block.\ Data in the DDR
233 + * is written from this offset.
234 + */
235 +#define CLASS_HDR_SIZE_DDR(off) (((off) & 0x1ff) << 16)
236 +
237 +#define CLASS_PE0_QB_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x020)
238 +
239 +/* DMEM address of first [15:0] and second [31:16] buffers on QB side. */
240 +#define CLASS_PE0_QB_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x024)
241 +
242 +/* DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
243 +#define CLASS_PE0_RO_DM_ADDR0 (CLASS_CSR_BASE_ADDR + 0x060)
244 +
245 +/* DMEM address of first [15:0] and second [31:16] buffers on RO side. */
246 +#define CLASS_PE0_RO_DM_ADDR1 (CLASS_CSR_BASE_ADDR + 0x064)
247 +
248 +/* DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
249 +
250 +/* @name Class PE memory access. Allows external PE's and HOST to
251 + * read/write PMEM/DMEM memory ranges for each classifier PE.
252 + */
253 +/* {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]},
254 + * See \ref XXX_MEM_ACCESS_ADDR for details.
255 + */
256 +#define CLASS_MEM_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x100)
257 +
258 +/* Internal Memory Access Write Data [31:0] */
259 +#define CLASS_MEM_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x104)
260 +
261 +/* Internal Memory Access Read Data [31:0] */
262 +#define CLASS_MEM_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x108)
263 +#define CLASS_TM_INQ_ADDR (CLASS_CSR_BASE_ADDR + 0x114)
264 +#define CLASS_PE_STATUS (CLASS_CSR_BASE_ADDR + 0x118)
265 +
266 +#define CLASS_PHY1_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x11c)
267 +#define CLASS_PHY1_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x120)
268 +#define CLASS_PHY1_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x124)
269 +#define CLASS_PHY1_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x128)
270 +#define CLASS_PHY1_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x12c)
271 +#define CLASS_PHY1_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x130)
272 +#define CLASS_PHY1_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x134)
273 +#define CLASS_PHY1_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x138)
274 +#define CLASS_PHY1_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x13c)
275 +#define CLASS_PHY1_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x140)
276 +#define CLASS_PHY2_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x144)
277 +#define CLASS_PHY2_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x148)
278 +#define CLASS_PHY2_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x14c)
279 +#define CLASS_PHY2_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x150)
280 +#define CLASS_PHY2_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x154)
281 +#define CLASS_PHY2_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x158)
282 +#define CLASS_PHY2_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x15c)
283 +#define CLASS_PHY2_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x160)
284 +#define CLASS_PHY2_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x164)
285 +#define CLASS_PHY2_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x168)
286 +#define CLASS_PHY3_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x16c)
287 +#define CLASS_PHY3_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x170)
288 +#define CLASS_PHY3_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x174)
289 +#define CLASS_PHY3_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x178)
290 +#define CLASS_PHY3_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x17c)
291 +#define CLASS_PHY3_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x180)
292 +#define CLASS_PHY3_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x184)
293 +#define CLASS_PHY3_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x188)
294 +#define CLASS_PHY3_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x18c)
295 +#define CLASS_PHY3_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x190)
296 +#define CLASS_PHY1_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x194)
297 +#define CLASS_PHY1_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x198)
298 +#define CLASS_PHY1_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x19c)
299 +#define CLASS_PHY1_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a0)
300 +#define CLASS_PHY2_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a4)
301 +#define CLASS_PHY2_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1a8)
302 +#define CLASS_PHY2_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1ac)
303 +#define CLASS_PHY2_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b0)
304 +#define CLASS_PHY3_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b4)
305 +#define CLASS_PHY3_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1b8)
306 +#define CLASS_PHY3_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1bc)
307 +#define CLASS_PHY3_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c0)
308 +#define CLASS_PHY4_ICMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c4)
309 +#define CLASS_PHY4_IGMP_PKTS (CLASS_CSR_BASE_ADDR + 0x1c8)
310 +#define CLASS_PHY4_TCP_PKTS (CLASS_CSR_BASE_ADDR + 0x1cc)
311 +#define CLASS_PHY4_UDP_PKTS (CLASS_CSR_BASE_ADDR + 0x1d0)
312 +#define CLASS_PHY4_RX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d4)
313 +#define CLASS_PHY4_TX_PKTS (CLASS_CSR_BASE_ADDR + 0x1d8)
314 +#define CLASS_PHY4_LP_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1dc)
315 +#define CLASS_PHY4_INTF_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e0)
316 +#define CLASS_PHY4_INTF_MATCH_PKTS (CLASS_CSR_BASE_ADDR + 0x1e4)
317 +#define CLASS_PHY4_L3_FAIL_PKTS (CLASS_CSR_BASE_ADDR + 0x1e8)
318 +#define CLASS_PHY4_V4_PKTS (CLASS_CSR_BASE_ADDR + 0x1ec)
319 +#define CLASS_PHY4_V6_PKTS (CLASS_CSR_BASE_ADDR + 0x1f0)
320 +#define CLASS_PHY4_CHKSUM_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f4)
321 +#define CLASS_PHY4_TTL_ERR_PKTS (CLASS_CSR_BASE_ADDR + 0x1f8)
322 +
323 +#define CLASS_PE_SYS_CLK_RATIO (CLASS_CSR_BASE_ADDR + 0x200)
324 +#define CLASS_AFULL_THRES (CLASS_CSR_BASE_ADDR + 0x204)
325 +#define CLASS_GAP_BETWEEN_READS (CLASS_CSR_BASE_ADDR + 0x208)
326 +#define CLASS_MAX_BUF_CNT (CLASS_CSR_BASE_ADDR + 0x20c)
327 +#define CLASS_TSQ_FIFO_THRES (CLASS_CSR_BASE_ADDR + 0x210)
328 +#define CLASS_TSQ_MAX_CNT (CLASS_CSR_BASE_ADDR + 0x214)
329 +#define CLASS_IRAM_DATA_0 (CLASS_CSR_BASE_ADDR + 0x218)
330 +#define CLASS_IRAM_DATA_1 (CLASS_CSR_BASE_ADDR + 0x21c)
331 +#define CLASS_IRAM_DATA_2 (CLASS_CSR_BASE_ADDR + 0x220)
332 +#define CLASS_IRAM_DATA_3 (CLASS_CSR_BASE_ADDR + 0x224)
333 +
334 +#define CLASS_BUS_ACCESS_ADDR (CLASS_CSR_BASE_ADDR + 0x228)
335 +
336 +#define CLASS_BUS_ACCESS_WDATA (CLASS_CSR_BASE_ADDR + 0x22c)
337 +#define CLASS_BUS_ACCESS_RDATA (CLASS_CSR_BASE_ADDR + 0x230)
338 +
339 +/* (route_entry_size[9:0], route_hash_size[23:16]
340 + * (this is actually ln2(size)))
341 + */
342 +#define CLASS_ROUTE_HASH_ENTRY_SIZE (CLASS_CSR_BASE_ADDR + 0x234)
343 +
344 +#define CLASS_ROUTE_ENTRY_SIZE(size) ((size) & 0x1ff)
345 +#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
346 +
347 +#define CLASS_ROUTE_TABLE_BASE (CLASS_CSR_BASE_ADDR + 0x238)
348 +
349 +#define CLASS_ROUTE_MULTI (CLASS_CSR_BASE_ADDR + 0x23c)
350 +#define CLASS_SMEM_OFFSET (CLASS_CSR_BASE_ADDR + 0x240)
351 +#define CLASS_LMEM_BUF_SIZE (CLASS_CSR_BASE_ADDR + 0x244)
352 +#define CLASS_VLAN_ID (CLASS_CSR_BASE_ADDR + 0x248)
353 +#define CLASS_BMU1_BUF_FREE (CLASS_CSR_BASE_ADDR + 0x24c)
354 +#define CLASS_USE_TMU_INQ (CLASS_CSR_BASE_ADDR + 0x250)
355 +#define CLASS_VLAN_ID1 (CLASS_CSR_BASE_ADDR + 0x254)
356 +
357 +#define CLASS_BUS_ACCESS_BASE (CLASS_CSR_BASE_ADDR + 0x258)
358 +#define CLASS_BUS_ACCESS_BASE_MASK (0xFF000000)
359 +/* bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE */
360 +
361 +#define CLASS_HIF_PARSE (CLASS_CSR_BASE_ADDR + 0x25c)
362 +
363 +#define CLASS_HOST_PE0_GP (CLASS_CSR_BASE_ADDR + 0x260)
364 +#define CLASS_PE0_GP (CLASS_CSR_BASE_ADDR + 0x264)
365 +#define CLASS_HOST_PE1_GP (CLASS_CSR_BASE_ADDR + 0x268)
366 +#define CLASS_PE1_GP (CLASS_CSR_BASE_ADDR + 0x26c)
367 +#define CLASS_HOST_PE2_GP (CLASS_CSR_BASE_ADDR + 0x270)
368 +#define CLASS_PE2_GP (CLASS_CSR_BASE_ADDR + 0x274)
369 +#define CLASS_HOST_PE3_GP (CLASS_CSR_BASE_ADDR + 0x278)
370 +#define CLASS_PE3_GP (CLASS_CSR_BASE_ADDR + 0x27c)
371 +#define CLASS_HOST_PE4_GP (CLASS_CSR_BASE_ADDR + 0x280)
372 +#define CLASS_PE4_GP (CLASS_CSR_BASE_ADDR + 0x284)
373 +#define CLASS_HOST_PE5_GP (CLASS_CSR_BASE_ADDR + 0x288)
374 +#define CLASS_PE5_GP (CLASS_CSR_BASE_ADDR + 0x28c)
375 +
376 +#define CLASS_PE_INT_SRC (CLASS_CSR_BASE_ADDR + 0x290)
377 +#define CLASS_PE_INT_ENABLE (CLASS_CSR_BASE_ADDR + 0x294)
378 +
379 +#define CLASS_TPID0_TPID1 (CLASS_CSR_BASE_ADDR + 0x298)
380 +#define CLASS_TPID2 (CLASS_CSR_BASE_ADDR + 0x29c)
381 +
382 +#define CLASS_L4_CHKSUM_ADDR (CLASS_CSR_BASE_ADDR + 0x2a0)
383 +
384 +#define CLASS_PE0_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a4)
385 +#define CLASS_PE1_DEBUG (CLASS_CSR_BASE_ADDR + 0x2a8)
386 +#define CLASS_PE2_DEBUG (CLASS_CSR_BASE_ADDR + 0x2ac)
387 +#define CLASS_PE3_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b0)
388 +#define CLASS_PE4_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b4)
389 +#define CLASS_PE5_DEBUG (CLASS_CSR_BASE_ADDR + 0x2b8)
390 +
391 +#define CLASS_STATE (CLASS_CSR_BASE_ADDR + 0x2bc)
392 +
393 +/* CLASS defines */
394 +#define CLASS_PBUF_SIZE 0x100 /* Fixed by hardware */
395 +#define CLASS_PBUF_HEADER_OFFSET 0x80 /* Can be configured */
396 +
397 +/* Can be configured */
398 +#define CLASS_PBUF0_BASE_ADDR 0x000
399 +/* Can be configured */
400 +#define CLASS_PBUF1_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)
401 +/* Can be configured */
402 +#define CLASS_PBUF2_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)
403 +/* Can be configured */
404 +#define CLASS_PBUF3_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)
405 +
406 +#define CLASS_PBUF0_HEADER_BASE_ADDR (CLASS_PBUF0_BASE_ADDR + \
407 + CLASS_PBUF_HEADER_OFFSET)
408 +#define CLASS_PBUF1_HEADER_BASE_ADDR (CLASS_PBUF1_BASE_ADDR + \
409 + CLASS_PBUF_HEADER_OFFSET)
410 +#define CLASS_PBUF2_HEADER_BASE_ADDR (CLASS_PBUF2_BASE_ADDR + \
411 + CLASS_PBUF_HEADER_OFFSET)
412 +#define CLASS_PBUF3_HEADER_BASE_ADDR (CLASS_PBUF3_BASE_ADDR + \
413 + CLASS_PBUF_HEADER_OFFSET)
414 +
415 +#define CLASS_PE0_RO_DM_ADDR0_VAL ((CLASS_PBUF1_BASE_ADDR << 16) | \
416 + CLASS_PBUF0_BASE_ADDR)
417 +#define CLASS_PE0_RO_DM_ADDR1_VAL ((CLASS_PBUF3_BASE_ADDR << 16) | \
418 + CLASS_PBUF2_BASE_ADDR)
419 +
420 +#define CLASS_PE0_QB_DM_ADDR0_VAL ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) |\
421 + CLASS_PBUF0_HEADER_BASE_ADDR)
422 +#define CLASS_PE0_QB_DM_ADDR1_VAL ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) |\
423 + CLASS_PBUF2_HEADER_BASE_ADDR)
424 +
425 +#define CLASS_ROUTE_SIZE 128
426 +#define CLASS_MAX_ROUTE_SIZE 256
427 +#define CLASS_ROUTE_HASH_BITS 20
428 +#define CLASS_ROUTE_HASH_MASK (BIT(CLASS_ROUTE_HASH_BITS) - 1)
429 +
430 +/* Can be configured */
431 +#define CLASS_ROUTE0_BASE_ADDR 0x400
432 +/* Can be configured */
433 +#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)
434 +/* Can be configured */
435 +#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)
436 +/* Can be configured */
437 +#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)
438 +
439 +#define CLASS_SA_SIZE 128
440 +#define CLASS_IPSEC_SA0_BASE_ADDR 0x600
441 +/* not used */
442 +#define CLASS_IPSEC_SA1_BASE_ADDR (CLASS_IPSEC_SA0_BASE_ADDR + CLASS_SA_SIZE)
443 +/* not used */
444 +#define CLASS_IPSEC_SA2_BASE_ADDR (CLASS_IPSEC_SA1_BASE_ADDR + CLASS_SA_SIZE)
445 +/* not used */
446 +#define CLASS_IPSEC_SA3_BASE_ADDR (CLASS_IPSEC_SA2_BASE_ADDR + CLASS_SA_SIZE)
447 +
448 +/* generic purpose free dmem buffer, last portion of 2K dmem pbuf */
449 +#define CLASS_GP_DMEM_BUF_SIZE (2048 - (CLASS_PBUF_SIZE * 4) - \
450 + (CLASS_ROUTE_SIZE * 4) - (CLASS_SA_SIZE))
451 +#define CLASS_GP_DMEM_BUF ((void *)(CLASS_IPSEC_SA0_BASE_ADDR + \
452 + CLASS_SA_SIZE))
453 +
454 +#define TWO_LEVEL_ROUTE BIT(0)
455 +#define PHYNO_IN_HASH BIT(1)
456 +#define HW_ROUTE_FETCH BIT(3)
457 +#define HW_BRIDGE_FETCH BIT(5)
458 +#define IP_ALIGNED BIT(6)
459 +#define ARC_HIT_CHECK_EN BIT(7)
460 +#define CLASS_TOE BIT(11)
461 +#define HASH_NORMAL (0 << 12)
462 +#define HASH_CRC_PORT BIT(12)
463 +#define HASH_CRC_IP (2 << 12)
464 +#define HASH_CRC_PORT_IP (3 << 12)
465 +#define QB2BUS_LE BIT(15)
466 +
467 +#define TCP_CHKSUM_DROP BIT(0)
468 +#define UDP_CHKSUM_DROP BIT(1)
469 +#define IPV4_CHKSUM_DROP BIT(9)
470 +
471 +/*CLASS_HIF_PARSE bits*/
472 +#define HIF_PKT_CLASS_EN BIT(0)
473 +#define HIF_PKT_OFFSET(ofst) (((ofst) & 0xF) << 1)
474 +
475 +struct class_cfg {
476 + u32 toe_mode;
477 + unsigned long route_table_baseaddr;
478 + u32 route_table_hash_bits;
479 + u32 pe_sys_clk_ratio;
480 + u32 resume;
481 +};
482 +
483 +#endif /* _CLASS_CSR_H_ */
484 --- /dev/null
485 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/emac_mtip.h
486 @@ -0,0 +1,242 @@
487 +/*
488 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
489 + * Copyright 2017 NXP
490 + *
491 + * This program is free software; you can redistribute it and/or modify
492 + * it under the terms of the GNU General Public License as published by
493 + * the Free Software Foundation; either version 2 of the License, or
494 + * (at your option) any later version.
495 + *
496 + * This program is distributed in the hope that it will be useful,
497 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
498 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
499 + * GNU General Public License for more details.
500 + *
501 + * You should have received a copy of the GNU General Public License
502 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
503 + */
504 +
505 +#ifndef _EMAC_H_
506 +#define _EMAC_H_
507 +
508 +#include <linux/ethtool.h>
509 +
510 +#define EMAC_IEVENT_REG 0x004
511 +#define EMAC_IMASK_REG 0x008
512 +#define EMAC_R_DES_ACTIVE_REG 0x010
513 +#define EMAC_X_DES_ACTIVE_REG 0x014
514 +#define EMAC_ECNTRL_REG 0x024
515 +#define EMAC_MII_DATA_REG 0x040
516 +#define EMAC_MII_CTRL_REG 0x044
517 +#define EMAC_MIB_CTRL_STS_REG 0x064
518 +#define EMAC_RCNTRL_REG 0x084
519 +#define EMAC_TCNTRL_REG 0x0C4
520 +#define EMAC_PHY_ADDR_LOW 0x0E4
521 +#define EMAC_PHY_ADDR_HIGH 0x0E8
522 +#define EMAC_GAUR 0x120
523 +#define EMAC_GALR 0x124
524 +#define EMAC_TFWR_STR_FWD 0x144
525 +#define EMAC_RX_SECTION_FULL 0x190
526 +#define EMAC_RX_SECTION_EMPTY 0x194
527 +#define EMAC_TX_SECTION_EMPTY 0x1A0
528 +#define EMAC_TRUNC_FL 0x1B0
529 +
530 +#define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */
531 +#define RMON_T_PACKETS 0x204 /* RMON TX packet count */
532 +#define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */
533 +#define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */
534 +#define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */
535 +#define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */
536 +#define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
537 +#define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */
538 +#define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
539 +#define RMON_T_COL 0x224 /* RMON TX collision count */
540 +#define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */
541 +#define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */
542 +#define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */
543 +#define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */
544 +#define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */
545 +#define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */
546 +#define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */
547 +#define RMON_T_OCTETS 0x244 /* RMON TX octets */
548 +#define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */
549 +#define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */
550 +#define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */
551 +#define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */
552 +#define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */
553 +#define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */
554 +#define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */
555 +#define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */
556 +#define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */
557 +#define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */
558 +#define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */
559 +#define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */
560 +#define RMON_R_PACKETS 0x284 /* RMON RX packet count */
561 +#define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */
562 +#define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */
563 +#define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */
564 +#define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */
565 +#define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
566 +#define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */
567 +#define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
568 +#define RMON_R_RESVD_O 0x2a4 /* Reserved */
569 +#define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */
570 +#define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */
571 +#define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */
572 +#define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */
573 +#define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */
574 +#define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */
575 +#define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */
576 +#define RMON_R_OCTETS 0x2c4 /* RMON RX octets */
577 +#define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */
578 +#define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */
579 +#define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */
580 +#define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */
581 +#define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */
582 +#define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */
583 +#define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */
584 +
585 +#define EMAC_SMAC_0_0 0x500 /*Supplemental MAC Address 0 (RW).*/
586 +#define EMAC_SMAC_0_1 0x504 /*Supplemental MAC Address 0 (RW).*/
587 +
588 +/* GEMAC definitions and settings */
589 +
590 +#define EMAC_PORT_0 0
591 +#define EMAC_PORT_1 1
592 +
593 +/* GEMAC Bit definitions */
594 +#define EMAC_IEVENT_HBERR 0x80000000
595 +#define EMAC_IEVENT_BABR 0x40000000
596 +#define EMAC_IEVENT_BABT 0x20000000
597 +#define EMAC_IEVENT_GRA 0x10000000
598 +#define EMAC_IEVENT_TXF 0x08000000
599 +#define EMAC_IEVENT_TXB 0x04000000
600 +#define EMAC_IEVENT_RXF 0x02000000
601 +#define EMAC_IEVENT_RXB 0x01000000
602 +#define EMAC_IEVENT_MII 0x00800000
603 +#define EMAC_IEVENT_EBERR 0x00400000
604 +#define EMAC_IEVENT_LC 0x00200000
605 +#define EMAC_IEVENT_RL 0x00100000
606 +#define EMAC_IEVENT_UN 0x00080000
607 +
608 +#define EMAC_IMASK_HBERR 0x80000000
609 +#define EMAC_IMASK_BABR 0x40000000
610 +#define EMAC_IMASKT_BABT 0x20000000
611 +#define EMAC_IMASK_GRA 0x10000000
612 +#define EMAC_IMASKT_TXF 0x08000000
613 +#define EMAC_IMASK_TXB 0x04000000
614 +#define EMAC_IMASKT_RXF 0x02000000
615 +#define EMAC_IMASK_RXB 0x01000000
616 +#define EMAC_IMASK_MII 0x00800000
617 +#define EMAC_IMASK_EBERR 0x00400000
618 +#define EMAC_IMASK_LC 0x00200000
619 +#define EMAC_IMASKT_RL 0x00100000
620 +#define EMAC_IMASK_UN 0x00080000
621 +
622 +#define EMAC_RCNTRL_MAX_FL_SHIFT 16
623 +#define EMAC_RCNTRL_LOOP 0x00000001
624 +#define EMAC_RCNTRL_DRT 0x00000002
625 +#define EMAC_RCNTRL_MII_MODE 0x00000004
626 +#define EMAC_RCNTRL_PROM 0x00000008
627 +#define EMAC_RCNTRL_BC_REJ 0x00000010
628 +#define EMAC_RCNTRL_FCE 0x00000020
629 +#define EMAC_RCNTRL_RGMII 0x00000040
630 +#define EMAC_RCNTRL_SGMII 0x00000080
631 +#define EMAC_RCNTRL_RMII 0x00000100
632 +#define EMAC_RCNTRL_RMII_10T 0x00000200
633 +#define EMAC_RCNTRL_CRC_FWD 0x00004000
634 +
635 +#define EMAC_TCNTRL_GTS 0x00000001
636 +#define EMAC_TCNTRL_HBC 0x00000002
637 +#define EMAC_TCNTRL_FDEN 0x00000004
638 +#define EMAC_TCNTRL_TFC_PAUSE 0x00000008
639 +#define EMAC_TCNTRL_RFC_PAUSE 0x00000010
640 +
641 +#define EMAC_ECNTRL_RESET 0x00000001 /* reset the EMAC */
642 +#define EMAC_ECNTRL_ETHER_EN 0x00000002 /* enable the EMAC */
643 +#define EMAC_ECNTRL_MAGIC_ENA 0x00000004
644 +#define EMAC_ECNTRL_SLEEP 0x00000008
645 +#define EMAC_ECNTRL_SPEED 0x00000020
646 +#define EMAC_ECNTRL_DBSWAP 0x00000100
647 +
648 +#define EMAC_X_WMRK_STRFWD 0x00000100
649 +
650 +#define EMAC_X_DES_ACTIVE_TDAR 0x01000000
651 +#define EMAC_R_DES_ACTIVE_RDAR 0x01000000
652 +
653 +#define EMAC_RX_SECTION_EMPTY_V 0x00010006
654 +/*
655 + * The possible operating speeds of the MAC, currently supporting 10, 100 and
656 + * 1000Mb modes.
657 + */
658 +enum mac_speed {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS};
659 +
660 +/* MII-related definitios */
661 +#define EMAC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */
662 +#define EMAC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */
663 +#define EMAC_MII_DATA_OP_CL45_RD 0x30000000 /* Perform a read operation */
664 +#define EMAC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */
665 +#define EMAC_MII_DATA_OP_CL45_WR 0x10000000 /* Perform a write operation */
666 +#define EMAC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */
667 +#define EMAC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */
668 +#define EMAC_MII_DATA_TA 0x00020000 /* Turnaround */
669 +#define EMAC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */
670 +
671 +#define EMAC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */
672 +#define EMAC_MII_DATA_RA_MASK 0x1F /* MII Register address mask */
673 +#define EMAC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */
674 +#define EMAC_MII_DATA_PA_MASK 0x1F /* MII PHY address mask */
675 +
676 +#define EMAC_MII_DATA_RA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
677 + EMAC_MII_DATA_RA_SHIFT)
678 +#define EMAC_MII_DATA_PA(v) (((v) & EMAC_MII_DATA_RA_MASK) << \
679 + EMAC_MII_DATA_PA_SHIFT)
680 +#define EMAC_MII_DATA(v) ((v) & 0xffff)
681 +
682 +#define EMAC_MII_SPEED_SHIFT 1
683 +#define EMAC_HOLDTIME_SHIFT 8
684 +#define EMAC_HOLDTIME_MASK 0x7
685 +#define EMAC_HOLDTIME(v) (((v) & EMAC_HOLDTIME_MASK) << \
686 + EMAC_HOLDTIME_SHIFT)
687 +
688 +/*
689 + * The Address organisation for the MAC device. All addresses are split into
690 + * two 32-bit register fields. The first one (bottom) is the lower 32-bits of
691 + * the address and the other field are the high order bits - this may be 16-bits
692 + * in the case of MAC addresses, or 32-bits for the hash address.
693 + * In terms of memory storage, the first item (bottom) is assumed to be at a
694 + * lower address location than 'top'. i.e. top should be at address location of
695 + * 'bottom' + 4 bytes.
696 + */
697 +struct pfe_mac_addr {
698 + u32 bottom; /* Lower 32-bits of address. */
699 + u32 top; /* Upper 32-bits of address. */
700 +};
701 +
702 +/*
703 + * The following is the organisation of the address filters section of the MAC
704 + * registers. The Cadence MAC contains four possible specific address match
705 + * addresses, if an incoming frame corresponds to any one of these four
706 + * addresses then the frame will be copied to memory.
707 + * It is not necessary for all four of the address match registers to be
708 + * programmed, this is application dependent.
709 + */
710 +struct spec_addr {
711 + struct pfe_mac_addr one; /* Specific address register 1. */
712 + struct pfe_mac_addr two; /* Specific address register 2. */
713 + struct pfe_mac_addr three; /* Specific address register 3. */
714 + struct pfe_mac_addr four; /* Specific address register 4. */
715 +};
716 +
717 +struct gemac_cfg {
718 + u32 mode;
719 + u32 speed;
720 + u32 duplex;
721 +};
722 +
723 +/* EMAC Hash size */
724 +#define EMAC_HASH_REG_BITS 64
725 +
726 +#define EMAC_SPEC_ADDR_MAX 4
727 +
728 +#endif /* _EMAC_H_ */
729 --- /dev/null
730 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/gpi.h
731 @@ -0,0 +1,86 @@
732 +/*
733 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
734 + * Copyright 2017 NXP
735 + *
736 + * This program is free software; you can redistribute it and/or modify
737 + * it under the terms of the GNU General Public License as published by
738 + * the Free Software Foundation; either version 2 of the License, or
739 + * (at your option) any later version.
740 + *
741 + * This program is distributed in the hope that it will be useful,
742 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
743 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
744 + * GNU General Public License for more details.
745 + *
746 + * You should have received a copy of the GNU General Public License
747 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
748 + */
749 +
750 +#ifndef _GPI_H_
751 +#define _GPI_H_
752 +
753 +#define GPI_VERSION 0x00
754 +#define GPI_CTRL 0x04
755 +#define GPI_RX_CONFIG 0x08
756 +#define GPI_HDR_SIZE 0x0c
757 +#define GPI_BUF_SIZE 0x10
758 +#define GPI_LMEM_ALLOC_ADDR 0x14
759 +#define GPI_LMEM_FREE_ADDR 0x18
760 +#define GPI_DDR_ALLOC_ADDR 0x1c
761 +#define GPI_DDR_FREE_ADDR 0x20
762 +#define GPI_CLASS_ADDR 0x24
763 +#define GPI_DRX_FIFO 0x28
764 +#define GPI_TRX_FIFO 0x2c
765 +#define GPI_INQ_PKTPTR 0x30
766 +#define GPI_DDR_DATA_OFFSET 0x34
767 +#define GPI_LMEM_DATA_OFFSET 0x38
768 +#define GPI_TMLF_TX 0x4c
769 +#define GPI_DTX_ASEQ 0x50
770 +#define GPI_FIFO_STATUS 0x54
771 +#define GPI_FIFO_DEBUG 0x58
772 +#define GPI_TX_PAUSE_TIME 0x5c
773 +#define GPI_LMEM_SEC_BUF_DATA_OFFSET 0x60
774 +#define GPI_DDR_SEC_BUF_DATA_OFFSET 0x64
775 +#define GPI_TOE_CHKSUM_EN 0x68
776 +#define GPI_OVERRUN_DROPCNT 0x6c
777 +#define GPI_CSR_MTIP_PAUSE_REG 0x74
778 +#define GPI_CSR_MTIP_PAUSE_QUANTUM 0x78
779 +#define GPI_CSR_RX_CNT 0x7c
780 +#define GPI_CSR_TX_CNT 0x80
781 +#define GPI_CSR_DEBUG1 0x84
782 +#define GPI_CSR_DEBUG2 0x88
783 +
784 +struct gpi_cfg {
785 + u32 lmem_rtry_cnt;
786 + u32 tmlf_txthres;
787 + u32 aseq_len;
788 + u32 mtip_pause_reg;
789 +};
790 +
791 +/* GPI commons defines */
792 +#define GPI_LMEM_BUF_EN 0x1
793 +#define GPI_DDR_BUF_EN 0x1
794 +
795 +/* EGPI 1 defines */
796 +#define EGPI1_LMEM_RTRY_CNT 0x40
797 +#define EGPI1_TMLF_TXTHRES 0xBC
798 +#define EGPI1_ASEQ_LEN 0x50
799 +
800 +/* EGPI 2 defines */
801 +#define EGPI2_LMEM_RTRY_CNT 0x40
802 +#define EGPI2_TMLF_TXTHRES 0xBC
803 +#define EGPI2_ASEQ_LEN 0x40
804 +
805 +/* EGPI 3 defines */
806 +#define EGPI3_LMEM_RTRY_CNT 0x40
807 +#define EGPI3_TMLF_TXTHRES 0xBC
808 +#define EGPI3_ASEQ_LEN 0x40
809 +
810 +/* HGPI defines */
811 +#define HGPI_LMEM_RTRY_CNT 0x40
812 +#define HGPI_TMLF_TXTHRES 0xBC
813 +#define HGPI_ASEQ_LEN 0x40
814 +
815 +#define EGPI_PAUSE_TIME 0x000007D0
816 +#define EGPI_PAUSE_ENABLE 0x40000000
817 +#endif /* _GPI_H_ */
818 --- /dev/null
819 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif.h
820 @@ -0,0 +1,100 @@
821 +/*
822 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
823 + * Copyright 2017 NXP
824 + *
825 + * This program is free software; you can redistribute it and/or modify
826 + * it under the terms of the GNU General Public License as published by
827 + * the Free Software Foundation; either version 2 of the License, or
828 + * (at your option) any later version.
829 + *
830 + * This program is distributed in the hope that it will be useful,
831 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
832 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
833 + * GNU General Public License for more details.
834 + *
835 + * You should have received a copy of the GNU General Public License
836 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
837 + */
838 +
839 +#ifndef _HIF_H_
840 +#define _HIF_H_
841 +
842 +/* @file hif.h.
843 + * hif - PFE hif block control and status register.
844 + * Mapped on CBUS and accessible from all PE's and ARM.
845 + */
846 +#define HIF_VERSION (HIF_BASE_ADDR + 0x00)
847 +#define HIF_TX_CTRL (HIF_BASE_ADDR + 0x04)
848 +#define HIF_TX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x08)
849 +#define HIF_TX_ALLOC (HIF_BASE_ADDR + 0x0c)
850 +#define HIF_TX_BDP_ADDR (HIF_BASE_ADDR + 0x10)
851 +#define HIF_TX_STATUS (HIF_BASE_ADDR + 0x14)
852 +#define HIF_RX_CTRL (HIF_BASE_ADDR + 0x20)
853 +#define HIF_RX_BDP_ADDR (HIF_BASE_ADDR + 0x24)
854 +#define HIF_RX_STATUS (HIF_BASE_ADDR + 0x30)
855 +#define HIF_INT_SRC (HIF_BASE_ADDR + 0x34)
856 +#define HIF_INT_ENABLE (HIF_BASE_ADDR + 0x38)
857 +#define HIF_POLL_CTRL (HIF_BASE_ADDR + 0x3c)
858 +#define HIF_RX_CURR_BD_ADDR (HIF_BASE_ADDR + 0x40)
859 +#define HIF_RX_ALLOC (HIF_BASE_ADDR + 0x44)
860 +#define HIF_TX_DMA_STATUS (HIF_BASE_ADDR + 0x48)
861 +#define HIF_RX_DMA_STATUS (HIF_BASE_ADDR + 0x4c)
862 +#define HIF_INT_COAL (HIF_BASE_ADDR + 0x50)
863 +
864 +/* HIF_INT_SRC/ HIF_INT_ENABLE control bits */
865 +#define HIF_INT BIT(0)
866 +#define HIF_RXBD_INT BIT(1)
867 +#define HIF_RXPKT_INT BIT(2)
868 +#define HIF_TXBD_INT BIT(3)
869 +#define HIF_TXPKT_INT BIT(4)
870 +
871 +/* HIF_TX_CTRL bits */
872 +#define HIF_CTRL_DMA_EN BIT(0)
873 +#define HIF_CTRL_BDP_POLL_CTRL_EN BIT(1)
874 +#define HIF_CTRL_BDP_CH_START_WSTB BIT(2)
875 +
876 +/* HIF_RX_STATUS bits */
877 +#define BDP_CSR_RX_DMA_ACTV BIT(16)
878 +
879 +/* HIF_INT_ENABLE bits */
880 +#define HIF_INT_EN BIT(0)
881 +#define HIF_RXBD_INT_EN BIT(1)
882 +#define HIF_RXPKT_INT_EN BIT(2)
883 +#define HIF_TXBD_INT_EN BIT(3)
884 +#define HIF_TXPKT_INT_EN BIT(4)
885 +
886 +/* HIF_POLL_CTRL bits*/
887 +#define HIF_RX_POLL_CTRL_CYCLE 0x0400
888 +#define HIF_TX_POLL_CTRL_CYCLE 0x0400
889 +
890 +/* HIF_INT_COAL bits*/
891 +#define HIF_INT_COAL_ENABLE BIT(31)
892 +
893 +/* Buffer descriptor control bits */
894 +#define BD_CTRL_BUFLEN_MASK 0x3fff
895 +#define BD_BUF_LEN(x) ((x) & BD_CTRL_BUFLEN_MASK)
896 +#define BD_CTRL_CBD_INT_EN BIT(16)
897 +#define BD_CTRL_PKT_INT_EN BIT(17)
898 +#define BD_CTRL_LIFM BIT(18)
899 +#define BD_CTRL_LAST_BD BIT(19)
900 +#define BD_CTRL_DIR BIT(20)
901 +#define BD_CTRL_LMEM_CPY BIT(21) /* Valid only for HIF_NOCPY */
902 +#define BD_CTRL_PKT_XFER BIT(24)
903 +#define BD_CTRL_DESC_EN BIT(31)
904 +#define BD_CTRL_PARSE_DISABLE BIT(25)
905 +#define BD_CTRL_BRFETCH_DISABLE BIT(26)
906 +#define BD_CTRL_RTFETCH_DISABLE BIT(27)
907 +
908 +/* Buffer descriptor status bits*/
909 +#define BD_STATUS_CONN_ID(x) ((x) & 0xffff)
910 +#define BD_STATUS_DIR_PROC_ID BIT(16)
911 +#define BD_STATUS_CONN_ID_EN BIT(17)
912 +#define BD_STATUS_PE2PROC_ID(x) (((x) & 7) << 18)
913 +#define BD_STATUS_LE_DATA BIT(21)
914 +#define BD_STATUS_CHKSUM_EN BIT(22)
915 +
916 +/* HIF Buffer descriptor status bits */
917 +#define DIR_PROC_ID BIT(16)
918 +#define PROC_ID(id) ((id) << 18)
919 +
920 +#endif /* _HIF_H_ */
921 --- /dev/null
922 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/hif_nocpy.h
923 @@ -0,0 +1,50 @@
924 +/*
925 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
926 + * Copyright 2017 NXP
927 + *
928 + * This program is free software; you can redistribute it and/or modify
929 + * it under the terms of the GNU General Public License as published by
930 + * the Free Software Foundation; either version 2 of the License, or
931 + * (at your option) any later version.
932 + *
933 + * This program is distributed in the hope that it will be useful,
934 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
935 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
936 + * GNU General Public License for more details.
937 + *
938 + * You should have received a copy of the GNU General Public License
939 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
940 + */
941 +
942 +#ifndef _HIF_NOCPY_H_
943 +#define _HIF_NOCPY_H_
944 +
945 +#define HIF_NOCPY_VERSION (HIF_NOCPY_BASE_ADDR + 0x00)
946 +#define HIF_NOCPY_TX_CTRL (HIF_NOCPY_BASE_ADDR + 0x04)
947 +#define HIF_NOCPY_TX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x08)
948 +#define HIF_NOCPY_TX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x0c)
949 +#define HIF_NOCPY_TX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x10)
950 +#define HIF_NOCPY_TX_STATUS (HIF_NOCPY_BASE_ADDR + 0x14)
951 +#define HIF_NOCPY_RX_CTRL (HIF_NOCPY_BASE_ADDR + 0x20)
952 +#define HIF_NOCPY_RX_BDP_ADDR (HIF_NOCPY_BASE_ADDR + 0x24)
953 +#define HIF_NOCPY_RX_STATUS (HIF_NOCPY_BASE_ADDR + 0x30)
954 +#define HIF_NOCPY_INT_SRC (HIF_NOCPY_BASE_ADDR + 0x34)
955 +#define HIF_NOCPY_INT_ENABLE (HIF_NOCPY_BASE_ADDR + 0x38)
956 +#define HIF_NOCPY_POLL_CTRL (HIF_NOCPY_BASE_ADDR + 0x3c)
957 +#define HIF_NOCPY_RX_CURR_BD_ADDR (HIF_NOCPY_BASE_ADDR + 0x40)
958 +#define HIF_NOCPY_RX_ALLOC (HIF_NOCPY_BASE_ADDR + 0x44)
959 +#define HIF_NOCPY_TX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x48)
960 +#define HIF_NOCPY_RX_DMA_STATUS (HIF_NOCPY_BASE_ADDR + 0x4c)
961 +#define HIF_NOCPY_RX_INQ0_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x50)
962 +#define HIF_NOCPY_RX_INQ1_PKTPTR (HIF_NOCPY_BASE_ADDR + 0x54)
963 +#define HIF_NOCPY_TX_PORT_NO (HIF_NOCPY_BASE_ADDR + 0x60)
964 +#define HIF_NOCPY_LMEM_ALLOC_ADDR (HIF_NOCPY_BASE_ADDR + 0x64)
965 +#define HIF_NOCPY_CLASS_ADDR (HIF_NOCPY_BASE_ADDR + 0x68)
966 +#define HIF_NOCPY_TMU_PORT0_ADDR (HIF_NOCPY_BASE_ADDR + 0x70)
967 +#define HIF_NOCPY_TMU_PORT1_ADDR (HIF_NOCPY_BASE_ADDR + 0x74)
968 +#define HIF_NOCPY_TMU_PORT2_ADDR (HIF_NOCPY_BASE_ADDR + 0x7c)
969 +#define HIF_NOCPY_TMU_PORT3_ADDR (HIF_NOCPY_BASE_ADDR + 0x80)
970 +#define HIF_NOCPY_TMU_PORT4_ADDR (HIF_NOCPY_BASE_ADDR + 0x84)
971 +#define HIF_NOCPY_INT_COAL (HIF_NOCPY_BASE_ADDR + 0x90)
972 +
973 +#endif /* _HIF_NOCPY_H_ */
974 --- /dev/null
975 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/tmu_csr.h
976 @@ -0,0 +1,168 @@
977 +/*
978 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
979 + * Copyright 2017 NXP
980 + *
981 + * This program is free software; you can redistribute it and/or modify
982 + * it under the terms of the GNU General Public License as published by
983 + * the Free Software Foundation; either version 2 of the License, or
984 + * (at your option) any later version.
985 + *
986 + * This program is distributed in the hope that it will be useful,
987 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
988 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
989 + * GNU General Public License for more details.
990 + *
991 + * You should have received a copy of the GNU General Public License
992 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
993 + */
994 +
995 +#ifndef _TMU_CSR_H_
996 +#define _TMU_CSR_H_
997 +
998 +#define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
999 +#define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
1000 +#define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
1001 +#define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
1002 +#define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
1003 +#define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
1004 +#define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
1005 +#define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
1006 +#define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
1007 +#define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
1008 +#define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
1009 +#define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
1010 +#define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
1011 +#define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
1012 +#define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
1013 +#define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
1014 +#define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
1015 +#define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
1016 +#define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
1017 +#define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
1018 +#define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
1019 +#define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
1020 +#define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
1021 +#define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
1022 +#define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
1023 +#define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
1024 +#define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
1025 +#define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
1026 +#define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
1027 +#define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
1028 +#define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
1029 +#define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
1030 +#define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
1031 +#define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
1032 +#define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
1033 +#define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
1034 +#define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
1035 +#define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
1036 +#define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
1037 +#define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
1038 +#define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
1039 +#define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
1040 +#define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
1041 +#define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
1042 +#define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
1043 +#define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
1044 +/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
1045 + * This is a global Enable for all schedulers in PHY0
1046 + */
1047 +#define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
1048 +
1049 +#define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
1050 +#define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
1051 +#define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
1052 +#define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
1053 +#define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
1054 +#define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
1055 +#define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
1056 +#define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
1057 +#define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
1058 +#define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
1059 +
1060 +/* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory
1061 + * Write [27:24] Byte Enables of the Internal memory access [23:0] Address of
1062 + * the internal memory. This address is used to access both the PM and DM of
1063 + * all the PE's
1064 + */
1065 +#define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
1066 +
1067 +/* Internal Memory Access Write Data */
1068 +#define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
1069 +/* Internal Memory Access Read Data. The commands are blocked
1070 + * at the mem_access only
1071 + */
1072 +#define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
1073 +
1074 +/* [31:0] PHY0 in queue address (must be initialized with one of the
1075 + * xxx_INQ_PKTPTR cbus addresses)
1076 + */
1077 +#define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
1078 +/* [31:0] PHY1 in queue address (must be initialized with one of the
1079 + * xxx_INQ_PKTPTR cbus addresses)
1080 + */
1081 +#define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
1082 +/* [31:0] PHY2 in queue address (must be initialized with one of the
1083 + * xxx_INQ_PKTPTR cbus addresses)
1084 + */
1085 +#define TMU_PHY2_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f8)
1086 +/* [31:0] PHY3 in queue address (must be initialized with one of the
1087 + * xxx_INQ_PKTPTR cbus addresses)
1088 + */
1089 +#define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
1090 +#define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
1091 +#define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
1092 +
1093 +#define TMU_BUS_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x108)
1094 +#define TMU_BUS_ACCESS (TMU_CSR_BASE_ADDR + 0x10c)
1095 +#define TMU_BUS_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x110)
1096 +
1097 +#define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
1098 +#define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
1099 +#define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
1100 +/* [31:0] PHY4 in queue address (must be initialized with one of the
1101 + * xxx_INQ_PKTPTR cbus addresses)
1102 + */
1103 +#define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
1104 +/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
1105 + * This is a global Enable for all schedulers in PHY1
1106 + */
1107 +#define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
1108 +/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
1109 + * This is a global Enable for all schedulers in PHY2
1110 + */
1111 +#define TMU_TDQ2_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x13c)
1112 +/* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
1113 + * This is a global Enable for all schedulers in PHY3
1114 + */
1115 +#define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
1116 +#define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
1117 +/* [31:0] PHY5 in queue address (must be initialized with one of the
1118 + * xxx_INQ_PKTPTR cbus addresses)
1119 + */
1120 +#define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
1121 +
1122 +#define SW_RESET BIT(0) /* Global software reset */
1123 +#define INQ_RESET BIT(2)
1124 +#define TEQ_RESET BIT(3)
1125 +#define TDQ_RESET BIT(4)
1126 +#define PE_RESET BIT(5)
1127 +#define MEM_INIT BIT(6)
1128 +#define MEM_INIT_DONE BIT(7)
1129 +#define LLM_INIT BIT(8)
1130 +#define LLM_INIT_DONE BIT(9)
1131 +#define ECC_MEM_INIT_DONE BIT(10)
1132 +
1133 +struct tmu_cfg {
1134 + u32 pe_sys_clk_ratio;
1135 + unsigned long llm_base_addr;
1136 + u32 llm_queue_len;
1137 +};
1138 +
1139 +/* Not HW related for pfe_ctrl / pfe common defines */
1140 +#define DEFAULT_MAX_QDEPTH 80
1141 +#define DEFAULT_Q0_QDEPTH 511 /*We keep one large queue for host tx qos */
1142 +#define DEFAULT_TMU3_QDEPTH 127
1143 +
1144 +#endif /* _TMU_CSR_H_ */
1145 --- /dev/null
1146 +++ b/drivers/staging/fsl_ppfe/include/pfe/cbus/util_csr.h
1147 @@ -0,0 +1,61 @@
1148 +/*
1149 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1150 + * Copyright 2017 NXP
1151 + *
1152 + * This program is free software; you can redistribute it and/or modify
1153 + * it under the terms of the GNU General Public License as published by
1154 + * the Free Software Foundation; either version 2 of the License, or
1155 + * (at your option) any later version.
1156 + *
1157 + * This program is distributed in the hope that it will be useful,
1158 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1159 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1160 + * GNU General Public License for more details.
1161 + *
1162 + * You should have received a copy of the GNU General Public License
1163 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1164 + */
1165 +
1166 +#ifndef _UTIL_CSR_H_
1167 +#define _UTIL_CSR_H_
1168 +
1169 +#define UTIL_VERSION (UTIL_CSR_BASE_ADDR + 0x000)
1170 +#define UTIL_TX_CTRL (UTIL_CSR_BASE_ADDR + 0x004)
1171 +#define UTIL_INQ_PKTPTR (UTIL_CSR_BASE_ADDR + 0x010)
1172 +
1173 +#define UTIL_HDR_SIZE (UTIL_CSR_BASE_ADDR + 0x014)
1174 +
1175 +#define UTIL_PE0_QB_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x020)
1176 +#define UTIL_PE0_QB_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x024)
1177 +#define UTIL_PE0_RO_DM_ADDR0 (UTIL_CSR_BASE_ADDR + 0x060)
1178 +#define UTIL_PE0_RO_DM_ADDR1 (UTIL_CSR_BASE_ADDR + 0x064)
1179 +
1180 +#define UTIL_MEM_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x100)
1181 +#define UTIL_MEM_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x104)
1182 +#define UTIL_MEM_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x108)
1183 +
1184 +#define UTIL_TM_INQ_ADDR (UTIL_CSR_BASE_ADDR + 0x114)
1185 +#define UTIL_PE_STATUS (UTIL_CSR_BASE_ADDR + 0x118)
1186 +
1187 +#define UTIL_PE_SYS_CLK_RATIO (UTIL_CSR_BASE_ADDR + 0x200)
1188 +#define UTIL_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x204)
1189 +#define UTIL_GAP_BETWEEN_READS (UTIL_CSR_BASE_ADDR + 0x208)
1190 +#define UTIL_MAX_BUF_CNT (UTIL_CSR_BASE_ADDR + 0x20c)
1191 +#define UTIL_TSQ_FIFO_THRES (UTIL_CSR_BASE_ADDR + 0x210)
1192 +#define UTIL_TSQ_MAX_CNT (UTIL_CSR_BASE_ADDR + 0x214)
1193 +#define UTIL_IRAM_DATA_0 (UTIL_CSR_BASE_ADDR + 0x218)
1194 +#define UTIL_IRAM_DATA_1 (UTIL_CSR_BASE_ADDR + 0x21c)
1195 +#define UTIL_IRAM_DATA_2 (UTIL_CSR_BASE_ADDR + 0x220)
1196 +#define UTIL_IRAM_DATA_3 (UTIL_CSR_BASE_ADDR + 0x224)
1197 +
1198 +#define UTIL_BUS_ACCESS_ADDR (UTIL_CSR_BASE_ADDR + 0x228)
1199 +#define UTIL_BUS_ACCESS_WDATA (UTIL_CSR_BASE_ADDR + 0x22c)
1200 +#define UTIL_BUS_ACCESS_RDATA (UTIL_CSR_BASE_ADDR + 0x230)
1201 +
1202 +#define UTIL_INQ_AFULL_THRES (UTIL_CSR_BASE_ADDR + 0x234)
1203 +
1204 +struct util_cfg {
1205 + u32 pe_sys_clk_ratio;
1206 +};
1207 +
1208 +#endif /* _UTIL_CSR_H_ */
1209 --- /dev/null
1210 +++ b/drivers/staging/fsl_ppfe/include/pfe/pfe.h
1211 @@ -0,0 +1,372 @@
1212 +/*
1213 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1214 + * Copyright 2017 NXP
1215 + *
1216 + * This program is free software; you can redistribute it and/or modify
1217 + * it under the terms of the GNU General Public License as published by
1218 + * the Free Software Foundation; either version 2 of the License, or
1219 + * (at your option) any later version.
1220 + *
1221 + * This program is distributed in the hope that it will be useful,
1222 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1223 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1224 + * GNU General Public License for more details.
1225 + *
1226 + * You should have received a copy of the GNU General Public License
1227 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1228 + */
1229 +
1230 +#ifndef _PFE_H_
1231 +#define _PFE_H_
1232 +
1233 +#include "cbus.h"
1234 +
1235 +#define CLASS_DMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
1236 +/*
1237 + * Only valid for mem access register interface
1238 + */
1239 +#define CLASS_IMEM_BASE_ADDR(i) (0x00000000 | ((i) << 20))
1240 +#define CLASS_DMEM_SIZE 0x00002000
1241 +#define CLASS_IMEM_SIZE 0x00008000
1242 +
1243 +#define TMU_DMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
1244 +/*
1245 + * Only valid for mem access register interface
1246 + */
1247 +#define TMU_IMEM_BASE_ADDR(i) (0x00000000 + ((i) << 20))
1248 +#define TMU_DMEM_SIZE 0x00000800
1249 +#define TMU_IMEM_SIZE 0x00002000
1250 +
1251 +#define UTIL_DMEM_BASE_ADDR 0x00000000
1252 +#define UTIL_DMEM_SIZE 0x00002000
1253 +
1254 +#define PE_LMEM_BASE_ADDR 0xc3010000
1255 +#define PE_LMEM_SIZE 0x8000
1256 +#define PE_LMEM_END (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
1257 +
1258 +#define DMEM_BASE_ADDR 0x00000000
1259 +#define DMEM_SIZE 0x2000 /* TMU has less... */
1260 +#define DMEM_END (DMEM_BASE_ADDR + DMEM_SIZE)
1261 +
1262 +#define PMEM_BASE_ADDR 0x00010000
1263 +#define PMEM_SIZE 0x8000 /* TMU has less... */
1264 +#define PMEM_END (PMEM_BASE_ADDR + PMEM_SIZE)
1265 +
1266 +/* These check memory ranges from PE point of view/memory map */
1267 +#define IS_DMEM(addr, len) \
1268 + ({ typeof(addr) addr_ = (addr); \
1269 + ((unsigned long)(addr_) >= DMEM_BASE_ADDR) && \
1270 + (((unsigned long)(addr_) + (len)) <= DMEM_END); })
1271 +
1272 +#define IS_PMEM(addr, len) \
1273 + ({ typeof(addr) addr_ = (addr); \
1274 + ((unsigned long)(addr_) >= PMEM_BASE_ADDR) && \
1275 + (((unsigned long)(addr_) + (len)) <= PMEM_END); })
1276 +
1277 +#define IS_PE_LMEM(addr, len) \
1278 + ({ typeof(addr) addr_ = (addr); \
1279 + ((unsigned long)(addr_) >= \
1280 + PE_LMEM_BASE_ADDR) && \
1281 + (((unsigned long)(addr_) + \
1282 + (len)) <= PE_LMEM_END); })
1283 +
1284 +#define IS_PFE_LMEM(addr, len) \
1285 + ({ typeof(addr) addr_ = (addr); \
1286 + ((unsigned long)(addr_) >= \
1287 + CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && \
1288 + (((unsigned long)(addr_) + (len)) <= \
1289 + CBUS_VIRT_TO_PFE(LMEM_END)); })
1290 +
1291 +#define __IS_PHYS_DDR(addr, len) \
1292 + ({ typeof(addr) addr_ = (addr); \
1293 + ((unsigned long)(addr_) >= \
1294 + DDR_PHYS_BASE_ADDR) && \
1295 + (((unsigned long)(addr_) + (len)) <= \
1296 + DDR_PHYS_END); })
1297 +
1298 +#define IS_PHYS_DDR(addr, len) __IS_PHYS_DDR(DDR_PFE_TO_PHYS(addr), len)
1299 +
1300 +/*
1301 + * If using a run-time virtual address for the cbus base address use this code
1302 + */
1303 +extern void *cbus_base_addr;
1304 +extern void *ddr_base_addr;
1305 +extern unsigned long ddr_phys_base_addr;
1306 +extern unsigned int ddr_size;
1307 +
1308 +#define CBUS_BASE_ADDR cbus_base_addr
1309 +#define DDR_PHYS_BASE_ADDR ddr_phys_base_addr
1310 +#define DDR_BASE_ADDR ddr_base_addr
1311 +#define DDR_SIZE ddr_size
1312 +
1313 +#define DDR_PHYS_END (DDR_PHYS_BASE_ADDR + DDR_SIZE)
1314 +
1315 +#define LS1012A_PFE_RESET_WA /*
1316 + * PFE doesn't have global reset and re-init
1317 + * should takecare few things to make PFE
1318 + * functional after reset
1319 + */
1320 +#define PFE_CBUS_PHYS_BASE_ADDR 0xc0000000 /* CBUS physical base address
1321 + * as seen by PE's.
1322 + */
1323 +/* CBUS physical base address as seen by PE's. */
1324 +#define PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE 0xc0000000
1325 +
1326 +#define DDR_PHYS_TO_PFE(p) (((unsigned long int)(p)) & 0x7FFFFFFF)
1327 +#define DDR_PFE_TO_PHYS(p) (((unsigned long int)(p)) | 0x80000000)
1328 +#define CBUS_PHYS_TO_PFE(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) + \
1329 + PFE_CBUS_PHYS_BASE_ADDR_FROM_PFE)
1330 +/* Translates to PFE address map */
1331 +
1332 +#define DDR_PHYS_TO_VIRT(p) (((p) - DDR_PHYS_BASE_ADDR) + DDR_BASE_ADDR)
1333 +#define DDR_VIRT_TO_PHYS(v) (((v) - DDR_BASE_ADDR) + DDR_PHYS_BASE_ADDR)
1334 +#define DDR_VIRT_TO_PFE(p) (DDR_PHYS_TO_PFE(DDR_VIRT_TO_PHYS(p)))
1335 +
1336 +#define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) + \
1337 + PFE_CBUS_PHYS_BASE_ADDR)
1338 +#define CBUS_PFE_TO_VIRT(p) (((unsigned long int)(p) - \
1339 + PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
1340 +
1341 +/* The below part of the code is used in QOS control driver from host */
1342 +#define TMU_APB_BASE_ADDR 0xc1000000 /* TMU base address seen by
1343 + * pe's
1344 + */
1345 +
1346 +enum {
1347 + CLASS0_ID = 0,
1348 + CLASS1_ID,
1349 + CLASS2_ID,
1350 + CLASS3_ID,
1351 + CLASS4_ID,
1352 + CLASS5_ID,
1353 + TMU0_ID,
1354 + TMU1_ID,
1355 + TMU2_ID,
1356 + TMU3_ID,
1357 +#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
1358 + UTIL_ID,
1359 +#endif
1360 + MAX_PE
1361 +};
1362 +
1363 +#define CLASS_MASK (BIT(CLASS0_ID) | BIT(CLASS1_ID) |\
1364 + BIT(CLASS2_ID) | BIT(CLASS3_ID) |\
1365 + BIT(CLASS4_ID) | BIT(CLASS5_ID))
1366 +#define CLASS_MAX_ID CLASS5_ID
1367 +
1368 +#define TMU_MASK (BIT(TMU0_ID) | BIT(TMU1_ID) |\
1369 + BIT(TMU3_ID))
1370 +
1371 +#define TMU_MAX_ID TMU3_ID
1372 +
1373 +#if !defined(CONFIG_FSL_PPFE_UTIL_DISABLED)
1374 +#define UTIL_MASK BIT(UTIL_ID)
1375 +#endif
1376 +
1377 +struct pe_status {
1378 + u32 cpu_state;
1379 + u32 activity_counter;
1380 + u32 rx;
1381 + union {
1382 + u32 tx;
1383 + u32 tmu_qstatus;
1384 + };
1385 + u32 drop;
1386 +#if defined(CFG_PE_DEBUG)
1387 + u32 debug_indicator;
1388 + u32 debug[16];
1389 +#endif
1390 +} __aligned(16);
1391 +
1392 +struct pe_sync_mailbox {
1393 + u32 stop;
1394 + u32 stopped;
1395 +};
1396 +
1397 +/* Drop counter definitions */
1398 +
1399 +#define CLASS_NUM_DROP_COUNTERS 13
1400 +#define UTIL_NUM_DROP_COUNTERS 8
1401 +
1402 +/* PE information.
1403 + * Structure containing PE's specific information. It is used to create
1404 + * generic C functions common to all PE's.
1405 + * Before using the library functions this structure needs to be initialized
1406 + * with the different registers virtual addresses
1407 + * (according to the ARM MMU mmaping). The default initialization supports a
1408 + * virtual == physical mapping.
1409 + */
1410 +struct pe_info {
1411 + u32 dmem_base_addr; /* PE's dmem base address */
1412 + u32 pmem_base_addr; /* PE's pmem base address */
1413 + u32 pmem_size; /* PE's pmem size */
1414 +
1415 + void *mem_access_wdata; /* PE's _MEM_ACCESS_WDATA register
1416 + * address
1417 + */
1418 + void *mem_access_addr; /* PE's _MEM_ACCESS_ADDR register
1419 + * address
1420 + */
1421 + void *mem_access_rdata; /* PE's _MEM_ACCESS_RDATA register
1422 + * address
1423 + */
1424 +};
1425 +
1426 +void pe_lmem_read(u32 *dst, u32 len, u32 offset);
1427 +void pe_lmem_write(u32 *src, u32 len, u32 offset);
1428 +
1429 +void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
1430 +void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
1431 +
1432 +u32 pe_pmem_read(int id, u32 addr, u8 size);
1433 +
1434 +void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
1435 +u32 pe_dmem_read(int id, u32 addr, u8 size);
1436 +void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len);
1437 +void class_pe_lmem_memset(u32 dst, int val, unsigned int len);
1438 +void class_bus_write(u32 val, u32 addr, u8 size);
1439 +u32 class_bus_read(u32 addr, u8 size);
1440 +
1441 +#define class_bus_readl(addr) class_bus_read(addr, 4)
1442 +#define class_bus_readw(addr) class_bus_read(addr, 2)
1443 +#define class_bus_readb(addr) class_bus_read(addr, 1)
1444 +
1445 +#define class_bus_writel(val, addr) class_bus_write(val, addr, 4)
1446 +#define class_bus_writew(val, addr) class_bus_write(val, addr, 2)
1447 +#define class_bus_writeb(val, addr) class_bus_write(val, addr, 1)
1448 +
1449 +#define pe_dmem_readl(id, addr) pe_dmem_read(id, addr, 4)
1450 +#define pe_dmem_readw(id, addr) pe_dmem_read(id, addr, 2)
1451 +#define pe_dmem_readb(id, addr) pe_dmem_read(id, addr, 1)
1452 +
1453 +#define pe_dmem_writel(id, val, addr) pe_dmem_write(id, val, addr, 4)
1454 +#define pe_dmem_writew(id, val, addr) pe_dmem_write(id, val, addr, 2)
1455 +#define pe_dmem_writeb(id, val, addr) pe_dmem_write(id, val, addr, 1)
1456 +
1457 +/*int pe_load_elf_section(int id, const void *data, elf32_shdr *shdr); */
1458 +int pe_load_elf_section(int id, const void *data, struct elf32_shdr *shdr,
1459 + struct device *dev);
1460 +
1461 +void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base,
1462 + unsigned int ddr_size);
1463 +void bmu_init(void *base, struct BMU_CFG *cfg);
1464 +void bmu_reset(void *base);
1465 +void bmu_enable(void *base);
1466 +void bmu_disable(void *base);
1467 +void bmu_set_config(void *base, struct BMU_CFG *cfg);
1468 +
1469 +/*
1470 + * An enumerated type for loopback values. This can be one of three values, no
1471 + * loopback -normal operation, local loopback with internal loopback module of
1472 + * MAC or PHY loopback which is through the external PHY.
1473 + */
1474 +#ifndef __MAC_LOOP_ENUM__
1475 +#define __MAC_LOOP_ENUM__
1476 +enum mac_loop {LB_NONE, LB_EXT, LB_LOCAL};
1477 +#endif
1478 +
1479 +void gemac_init(void *base, void *config);
1480 +void gemac_disable_rx_checksum_offload(void *base);
1481 +void gemac_enable_rx_checksum_offload(void *base);
1482 +void gemac_set_mdc_div(void *base, int mdc_div);
1483 +void gemac_set_speed(void *base, enum mac_speed gem_speed);
1484 +void gemac_set_duplex(void *base, int duplex);
1485 +void gemac_set_mode(void *base, int mode);
1486 +void gemac_enable(void *base);
1487 +void gemac_tx_disable(void *base);
1488 +void gemac_tx_enable(void *base);
1489 +void gemac_disable(void *base);
1490 +void gemac_reset(void *base);
1491 +void gemac_set_address(void *base, struct spec_addr *addr);
1492 +struct spec_addr gemac_get_address(void *base);
1493 +void gemac_set_loop(void *base, enum mac_loop gem_loop);
1494 +void gemac_set_laddr1(void *base, struct pfe_mac_addr *address);
1495 +void gemac_set_laddr2(void *base, struct pfe_mac_addr *address);
1496 +void gemac_set_laddr3(void *base, struct pfe_mac_addr *address);
1497 +void gemac_set_laddr4(void *base, struct pfe_mac_addr *address);
1498 +void gemac_set_laddrN(void *base, struct pfe_mac_addr *address,
1499 + unsigned int entry_index);
1500 +void gemac_clear_laddr1(void *base);
1501 +void gemac_clear_laddr2(void *base);
1502 +void gemac_clear_laddr3(void *base);
1503 +void gemac_clear_laddr4(void *base);
1504 +void gemac_clear_laddrN(void *base, unsigned int entry_index);
1505 +struct pfe_mac_addr gemac_get_hash(void *base);
1506 +void gemac_set_hash(void *base, struct pfe_mac_addr *hash);
1507 +struct pfe_mac_addr gem_get_laddr1(void *base);
1508 +struct pfe_mac_addr gem_get_laddr2(void *base);
1509 +struct pfe_mac_addr gem_get_laddr3(void *base);
1510 +struct pfe_mac_addr gem_get_laddr4(void *base);
1511 +struct pfe_mac_addr gem_get_laddrN(void *base, unsigned int entry_index);
1512 +void gemac_set_config(void *base, struct gemac_cfg *cfg);
1513 +void gemac_allow_broadcast(void *base);
1514 +void gemac_no_broadcast(void *base);
1515 +void gemac_enable_1536_rx(void *base);
1516 +void gemac_disable_1536_rx(void *base);
1517 +void gemac_enable_rx_jmb(void *base);
1518 +void gemac_disable_rx_jmb(void *base);
1519 +void gemac_enable_stacked_vlan(void *base);
1520 +void gemac_disable_stacked_vlan(void *base);
1521 +void gemac_enable_pause_rx(void *base);
1522 +void gemac_disable_pause_rx(void *base);
1523 +void gemac_enable_copy_all(void *base);
1524 +void gemac_disable_copy_all(void *base);
1525 +void gemac_set_bus_width(void *base, int width);
1526 +void gemac_set_wol(void *base, u32 wol_conf);
1527 +
1528 +void gpi_init(void *base, struct gpi_cfg *cfg);
1529 +void gpi_reset(void *base);
1530 +void gpi_enable(void *base);
1531 +void gpi_disable(void *base);
1532 +void gpi_set_config(void *base, struct gpi_cfg *cfg);
1533 +
1534 +void class_init(struct class_cfg *cfg);
1535 +void class_reset(void);
1536 +void class_enable(void);
1537 +void class_disable(void);
1538 +void class_set_config(struct class_cfg *cfg);
1539 +
1540 +void tmu_reset(void);
1541 +void tmu_init(struct tmu_cfg *cfg);
1542 +void tmu_enable(u32 pe_mask);
1543 +void tmu_disable(u32 pe_mask);
1544 +u32 tmu_qstatus(u32 if_id);
1545 +u32 tmu_pkts_processed(u32 if_id);
1546 +
1547 +void util_init(struct util_cfg *cfg);
1548 +void util_reset(void);
1549 +void util_enable(void);
1550 +void util_disable(void);
1551 +
1552 +void hif_init(void);
1553 +void hif_tx_enable(void);
1554 +void hif_tx_disable(void);
1555 +void hif_rx_enable(void);
1556 +void hif_rx_disable(void);
1557 +
1558 +/* Get Chip Revision level
1559 + *
1560 + */
1561 +static inline unsigned int CHIP_REVISION(void)
1562 +{
1563 + /*For LS1012A return always 1 */
1564 + return 1;
1565 +}
1566 +
1567 +/* Start HIF rx DMA
1568 + *
1569 + */
1570 +static inline void hif_rx_dma_start(void)
1571 +{
1572 + writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_RX_CTRL);
1573 +}
1574 +
1575 +/* Start HIF tx DMA
1576 + *
1577 + */
1578 +static inline void hif_tx_dma_start(void)
1579 +{
1580 + writel(HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB, HIF_TX_CTRL);
1581 +}
1582 +
1583 +#endif /* _PFE_H_ */
1584 --- /dev/null
1585 +++ b/drivers/staging/fsl_ppfe/pfe_ctrl.h
1586 @@ -0,0 +1,112 @@
1587 +/*
1588 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1589 + * Copyright 2017 NXP
1590 + *
1591 + * This program is free software; you can redistribute it and/or modify
1592 + * it under the terms of the GNU General Public License as published by
1593 + * the Free Software Foundation; either version 2 of the License, or
1594 + * (at your option) any later version.
1595 + *
1596 + * This program is distributed in the hope that it will be useful,
1597 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1598 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1599 + * GNU General Public License for more details.
1600 + *
1601 + * You should have received a copy of the GNU General Public License
1602 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1603 + */
1604 +
1605 +#ifndef _PFE_CTRL_H_
1606 +#define _PFE_CTRL_H_
1607 +
1608 +#include <linux/dmapool.h>
1609 +
1610 +#include "pfe_mod.h"
1611 +#include "pfe/pfe.h"
1612 +
1613 +#define DMA_BUF_SIZE_128 0x80 /* enough for 1 conntracks */
1614 +#define DMA_BUF_SIZE_256 0x100
1615 +/* enough for 2 conntracks, 1 bridge entry or 1 multicast entry */
1616 +#define DMA_BUF_SIZE_512 0x200
1617 +/* 512bytes dma allocated buffers used by rtp relay feature */
1618 +#define DMA_BUF_MIN_ALIGNMENT 8
1619 +#define DMA_BUF_BOUNDARY (4 * 1024)
1620 +/* bursts can not cross 4k boundary */
1621 +
1622 +#define CMD_TX_ENABLE 0x0501
1623 +#define CMD_TX_DISABLE 0x0502
1624 +
1625 +#define CMD_RX_LRO 0x0011
1626 +#define CMD_PKTCAP_ENABLE 0x0d01
1627 +#define CMD_QM_EXPT_RATE 0x020c
1628 +
1629 +#define CLASS_DM_SH_STATIC (0x800)
1630 +#define CLASS_DM_CPU_TICKS (CLASS_DM_SH_STATIC)
1631 +#define CLASS_DM_SYNC_MBOX (0x808)
1632 +#define CLASS_DM_MSG_MBOX (0x810)
1633 +#define CLASS_DM_DROP_CNTR (0x820)
1634 +#define CLASS_DM_RESUME (0x854)
1635 +#define CLASS_DM_PESTATUS (0x860)
1636 +
1637 +#define TMU_DM_SH_STATIC (0x80)
1638 +#define TMU_DM_CPU_TICKS (TMU_DM_SH_STATIC)
1639 +#define TMU_DM_SYNC_MBOX (0x88)
1640 +#define TMU_DM_MSG_MBOX (0x90)
1641 +#define TMU_DM_RESUME (0xA0)
1642 +#define TMU_DM_PESTATUS (0xB0)
1643 +#define TMU_DM_CONTEXT (0x300)
1644 +#define TMU_DM_TX_TRANS (0x480)
1645 +
1646 +#define UTIL_DM_SH_STATIC (0x0)
1647 +#define UTIL_DM_CPU_TICKS (UTIL_DM_SH_STATIC)
1648 +#define UTIL_DM_SYNC_MBOX (0x8)
1649 +#define UTIL_DM_MSG_MBOX (0x10)
1650 +#define UTIL_DM_DROP_CNTR (0x20)
1651 +#define UTIL_DM_RESUME (0x40)
1652 +#define UTIL_DM_PESTATUS (0x50)
1653 +
1654 +struct pfe_ctrl {
1655 + struct mutex mutex; /* to serialize pfe control access */
1656 + spinlock_t lock;
1657 +
1658 + void *dma_pool;
1659 + void *dma_pool_512;
1660 + void *dma_pool_128;
1661 +
1662 + struct device *dev;
1663 +
1664 + void *hash_array_baseaddr; /*
1665 + * Virtual base address of
1666 + * the conntrack hash array
1667 + */
1668 + unsigned long hash_array_phys_baseaddr; /*
1669 + * Physical base address of
1670 + * the conntrack hash array
1671 + */
1672 +
1673 + int (*event_cb)(u16, u16, u16*);
1674 +
1675 + unsigned long sync_mailbox_baseaddr[MAX_PE]; /*
1676 + * Sync mailbox PFE
1677 + * internal address,
1678 + * initialized
1679 + * when parsing elf images
1680 + */
1681 + unsigned long msg_mailbox_baseaddr[MAX_PE]; /*
1682 + * Msg mailbox PFE internal
1683 + * address, initialized
1684 + * when parsing elf images
1685 + */
1686 + unsigned int sys_clk; /* AXI clock value, in KHz */
1687 +};
1688 +
1689 +int pfe_ctrl_init(struct pfe *pfe);
1690 +void pfe_ctrl_exit(struct pfe *pfe);
1691 +int pe_sync_stop(struct pfe_ctrl *ctrl, int pe_mask);
1692 +void pe_start(struct pfe_ctrl *ctrl, int pe_mask);
1693 +int pe_reset_all(struct pfe_ctrl *ctrl);
1694 +void pfe_ctrl_suspend(struct pfe_ctrl *ctrl);
1695 +void pfe_ctrl_resume(struct pfe_ctrl *ctrl);
1696 +int relax(unsigned long end);
1697 +
1698 +#endif /* _PFE_CTRL_H_ */
1699 --- /dev/null
1700 +++ b/drivers/staging/fsl_ppfe/pfe_debugfs.h
1701 @@ -0,0 +1,25 @@
1702 +/*
1703 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1704 + * Copyright 2017 NXP
1705 + *
1706 + * This program is free software; you can redistribute it and/or modify
1707 + * it under the terms of the GNU General Public License as published by
1708 + * the Free Software Foundation; either version 2 of the License, or
1709 + * (at your option) any later version.
1710 + *
1711 + * This program is distributed in the hope that it will be useful,
1712 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1713 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1714 + * GNU General Public License for more details.
1715 + *
1716 + * You should have received a copy of the GNU General Public License
1717 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1718 + */
1719 +
1720 +#ifndef _PFE_DEBUGFS_H_
1721 +#define _PFE_DEBUGFS_H_
1722 +
1723 +int pfe_debugfs_init(struct pfe *pfe);
1724 +void pfe_debugfs_exit(struct pfe *pfe);
1725 +
1726 +#endif /* _PFE_DEBUGFS_H_ */
1727 --- /dev/null
1728 +++ b/drivers/staging/fsl_ppfe/pfe_eth.h
1729 @@ -0,0 +1,184 @@
1730 +/*
1731 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1732 + * Copyright 2017 NXP
1733 + *
1734 + * This program is free software; you can redistribute it and/or modify
1735 + * it under the terms of the GNU General Public License as published by
1736 + * the Free Software Foundation; either version 2 of the License, or
1737 + * (at your option) any later version.
1738 + *
1739 + * This program is distributed in the hope that it will be useful,
1740 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1741 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1742 + * GNU General Public License for more details.
1743 + *
1744 + * You should have received a copy of the GNU General Public License
1745 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1746 + */
1747 +
1748 +#ifndef _PFE_ETH_H_
1749 +#define _PFE_ETH_H_
1750 +#include <linux/kernel.h>
1751 +#include <linux/netdevice.h>
1752 +#include <linux/etherdevice.h>
1753 +#include <linux/ethtool.h>
1754 +#include <linux/mii.h>
1755 +#include <linux/phy.h>
1756 +#include <linux/clk.h>
1757 +#include <linux/interrupt.h>
1758 +#include <linux/time.h>
1759 +
1760 +#define PFE_ETH_NAPI_STATS
1761 +#define PFE_ETH_TX_STATS
1762 +
1763 +#define PFE_ETH_FRAGS_MAX (65536 / HIF_RX_PKT_MIN_SIZE)
1764 +#define LRO_LEN_COUNT_MAX 32
1765 +#define LRO_NB_COUNT_MAX 32
1766 +
1767 +#define PFE_PAUSE_FLAG_ENABLE 1
1768 +#define PFE_PAUSE_FLAG_AUTONEG 2
1769 +
1770 +/* GEMAC configured by SW */
1771 +/* GEMAC configured by phy lines (not for MII/GMII) */
1772 +
1773 +#define GEMAC_SW_FULL_DUPLEX BIT(9)
1774 +#define GEMAC_SW_SPEED_10M (0 << 12)
1775 +#define GEMAC_SW_SPEED_100M BIT(12)
1776 +#define GEMAC_SW_SPEED_1G (2 << 12)
1777 +
1778 +#define GEMAC_NO_PHY BIT(0)
1779 +
1780 +struct ls1012a_eth_platform_data {
1781 + /* device specific information */
1782 + u32 device_flags;
1783 + char name[16];
1784 +
1785 + /* board specific information */
1786 + u32 mii_config;
1787 + u32 phy_flags;
1788 + u32 gem_id;
1789 + u32 bus_id;
1790 + u32 phy_id;
1791 + u32 mdio_muxval;
1792 + u8 mac_addr[ETH_ALEN];
1793 +};
1794 +
1795 +struct ls1012a_mdio_platform_data {
1796 + int enabled;
1797 + int irq[32];
1798 + u32 phy_mask;
1799 + int mdc_div;
1800 +};
1801 +
1802 +struct ls1012a_pfe_platform_data {
1803 + struct ls1012a_eth_platform_data ls1012a_eth_pdata[3];
1804 + struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];
1805 +};
1806 +
1807 +#define NUM_GEMAC_SUPPORT 2
1808 +#define DRV_NAME "pfe-eth"
1809 +#define DRV_VERSION "1.0"
1810 +
1811 +#define LS1012A_TX_FAST_RECOVERY_TIMEOUT_MS 3
1812 +#define TX_POLL_TIMEOUT_MS 1000
1813 +
1814 +#define EMAC_TXQ_CNT 16
1815 +#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT)
1816 +
1817 +#define JUMBO_FRAME_SIZE 10258
1818 +/*
1819 + * Client Tx queue threshold, for txQ flush condition.
1820 + * It must be smaller than the queue size (in case we ever change it in the
1821 + * future).
1822 + */
1823 +#define HIF_CL_TX_FLUSH_MARK 32
1824 +
1825 +/*
1826 + * Max number of TX resources (HIF descriptors or skbs) that will be released
1827 + * in a single go during batch recycling.
1828 + * Should be lower than the flush mark so the SW can provide the HW with a
1829 + * continuous stream of packets instead of bursts.
1830 + */
1831 +#define TX_FREE_MAX_COUNT 16
1832 +#define EMAC_RXQ_CNT 3
1833 +#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT
1834 +/* make sure clients can receive a full burst of packets */
1835 +#define EMAC_RMON_TXBYTES_POS 0x00
1836 +#define EMAC_RMON_RXBYTES_POS 0x14
1837 +
1838 +#define EMAC_QUEUENUM_MASK (emac_txq_cnt - 1)
1839 +#define EMAC_MDIO_TIMEOUT 1000
1840 +#define MAX_UC_SPEC_ADDR_REG 31
1841 +
1842 +struct pfe_eth_fast_timer {
1843 + int queuenum;
1844 + struct hrtimer timer;
1845 + void *base;
1846 +};
1847 +
1848 +struct pfe_eth_priv_s {
1849 + struct pfe *pfe;
1850 + struct hif_client_s client;
1851 + struct napi_struct lro_napi;
1852 + struct napi_struct low_napi;
1853 + struct napi_struct high_napi;
1854 + int low_tmu_q;
1855 + int high_tmu_q;
1856 + struct net_device_stats stats;
1857 + struct net_device *ndev;
1858 + int id;
1859 + int promisc;
1860 + unsigned int msg_enable;
1861 + unsigned int usr_features;
1862 +
1863 + spinlock_t lock; /* protect member variables */
1864 + unsigned int event_status;
1865 + int irq;
1866 + void *EMAC_baseaddr;
1867 + /* This points to the EMAC base from where we access PHY */
1868 + void *PHY_baseaddr;
1869 + void *GPI_baseaddr;
1870 + /* PHY stuff */
1871 + struct phy_device *phydev;
1872 + int oldspeed;
1873 + int oldduplex;
1874 + int oldlink;
1875 + /* mdio info */
1876 + int mdc_div;
1877 + struct mii_bus *mii_bus;
1878 + struct clk *gemtx_clk;
1879 + int wol;
1880 + int pause_flag;
1881 +
1882 + int default_priority;
1883 + struct pfe_eth_fast_timer fast_tx_timeout[EMAC_TXQ_CNT];
1884 +
1885 + struct ls1012a_eth_platform_data *einfo;
1886 + struct sk_buff *skb_inflight[EMAC_RXQ_CNT + 6];
1887 +
1888 +#ifdef PFE_ETH_TX_STATS
1889 + unsigned int stop_queue_total[EMAC_TXQ_CNT];
1890 + unsigned int stop_queue_hif[EMAC_TXQ_CNT];
1891 + unsigned int stop_queue_hif_client[EMAC_TXQ_CNT];
1892 + unsigned int stop_queue_credit[EMAC_TXQ_CNT];
1893 + unsigned int clean_fail[EMAC_TXQ_CNT];
1894 + unsigned int was_stopped[EMAC_TXQ_CNT];
1895 +#endif
1896 +
1897 +#ifdef PFE_ETH_NAPI_STATS
1898 + unsigned int napi_counters[NAPI_MAX_COUNT];
1899 +#endif
1900 + unsigned int frags_inflight[EMAC_RXQ_CNT + 6];
1901 +};
1902 +
1903 +struct pfe_eth {
1904 + struct pfe_eth_priv_s *eth_priv[3];
1905 +};
1906 +
1907 +int pfe_eth_init(struct pfe *pfe);
1908 +void pfe_eth_exit(struct pfe *pfe);
1909 +int pfe_eth_suspend(struct net_device *dev);
1910 +int pfe_eth_resume(struct net_device *dev);
1911 +int pfe_eth_mdio_reset(struct mii_bus *bus);
1912 +
1913 +#endif /* _PFE_ETH_H_ */
1914 --- /dev/null
1915 +++ b/drivers/staging/fsl_ppfe/pfe_firmware.h
1916 @@ -0,0 +1,32 @@
1917 +/*
1918 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1919 + * Copyright 2017 NXP
1920 + *
1921 + * This program is free software; you can redistribute it and/or modify
1922 + * it under the terms of the GNU General Public License as published by
1923 + * the Free Software Foundation; either version 2 of the License, or
1924 + * (at your option) any later version.
1925 + *
1926 + * This program is distributed in the hope that it will be useful,
1927 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1928 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1929 + * GNU General Public License for more details.
1930 + *
1931 + * You should have received a copy of the GNU General Public License
1932 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1933 + */
1934 +
1935 +#ifndef _PFE_FIRMWARE_H_
1936 +#define _PFE_FIRMWARE_H_
1937 +
1938 +#define CLASS_FIRMWARE_FILENAME "ppfe_class_ls1012a.elf"
1939 +#define TMU_FIRMWARE_FILENAME "ppfe_tmu_ls1012a.elf"
1940 +
1941 +#define PFE_FW_CHECK_PASS 0
1942 +#define PFE_FW_CHECK_FAIL 1
1943 +#define NUM_PFE_FW 3
1944 +
1945 +int pfe_firmware_init(struct pfe *pfe);
1946 +void pfe_firmware_exit(struct pfe *pfe);
1947 +
1948 +#endif /* _PFE_FIRMWARE_H_ */
1949 --- /dev/null
1950 +++ b/drivers/staging/fsl_ppfe/pfe_hif.h
1951 @@ -0,0 +1,211 @@
1952 +/*
1953 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
1954 + * Copyright 2017 NXP
1955 + *
1956 + * This program is free software; you can redistribute it and/or modify
1957 + * it under the terms of the GNU General Public License as published by
1958 + * the Free Software Foundation; either version 2 of the License, or
1959 + * (at your option) any later version.
1960 + *
1961 + * This program is distributed in the hope that it will be useful,
1962 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1963 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1964 + * GNU General Public License for more details.
1965 + *
1966 + * You should have received a copy of the GNU General Public License
1967 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
1968 + */
1969 +
1970 +#ifndef _PFE_HIF_H_
1971 +#define _PFE_HIF_H_
1972 +
1973 +#include <linux/netdevice.h>
1974 +
1975 +#define HIF_NAPI_STATS
1976 +
1977 +#define HIF_CLIENT_QUEUES_MAX 16
1978 +#define HIF_RX_POLL_WEIGHT 64
1979 +
1980 +#define HIF_RX_PKT_MIN_SIZE 0x800 /* 2KB */
1981 +#define HIF_RX_PKT_MIN_SIZE_MASK ~(HIF_RX_PKT_MIN_SIZE - 1)
1982 +#define ROUND_MIN_RX_SIZE(_sz) (((_sz) + (HIF_RX_PKT_MIN_SIZE - 1)) \
1983 + & HIF_RX_PKT_MIN_SIZE_MASK)
1984 +#define PRESENT_OFST_IN_PAGE(_buf) (((unsigned long int)(_buf) & (PAGE_SIZE \
1985 + - 1)) & HIF_RX_PKT_MIN_SIZE_MASK)
1986 +
1987 +enum {
1988 + NAPI_SCHED_COUNT = 0,
1989 + NAPI_POLL_COUNT,
1990 + NAPI_PACKET_COUNT,
1991 + NAPI_DESC_COUNT,
1992 + NAPI_FULL_BUDGET_COUNT,
1993 + NAPI_CLIENT_FULL_COUNT,
1994 + NAPI_MAX_COUNT
1995 +};
1996 +
1997 +/*
1998 + * HIF_TX_DESC_NT value should be always greter than 4,
1999 + * Otherwise HIF_TX_POLL_MARK will become zero.
2000 + */
2001 +#define HIF_RX_DESC_NT 256
2002 +#define HIF_TX_DESC_NT 2048
2003 +
2004 +#define HIF_FIRST_BUFFER BIT(0)
2005 +#define HIF_LAST_BUFFER BIT(1)
2006 +#define HIF_DONT_DMA_MAP BIT(2)
2007 +#define HIF_DATA_VALID BIT(3)
2008 +#define HIF_TSO BIT(4)
2009 +
2010 +enum {
2011 + PFE_CL_GEM0 = 0,
2012 + PFE_CL_GEM1,
2013 + HIF_CLIENTS_MAX
2014 +};
2015 +
2016 +/*structure to store client queue info */
2017 +struct hif_rx_queue {
2018 + struct rx_queue_desc *base;
2019 + u32 size;
2020 + u32 write_idx;
2021 +};
2022 +
2023 +struct hif_tx_queue {
2024 + struct tx_queue_desc *base;
2025 + u32 size;
2026 + u32 ack_idx;
2027 +};
2028 +
2029 +/*Structure to store the client info */
2030 +struct hif_client {
2031 + int rx_qn;
2032 + struct hif_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
2033 + int tx_qn;
2034 + struct hif_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
2035 +};
2036 +
2037 +/*HIF hardware buffer descriptor */
2038 +struct hif_desc {
2039 + u32 ctrl;
2040 + u32 status;
2041 + u32 data;
2042 + u32 next;
2043 +};
2044 +
2045 +struct __hif_desc {
2046 + u32 ctrl;
2047 + u32 status;
2048 + u32 data;
2049 +};
2050 +
2051 +struct hif_desc_sw {
2052 + dma_addr_t data;
2053 + u16 len;
2054 + u8 client_id;
2055 + u8 q_no;
2056 + u16 flags;
2057 +};
2058 +
2059 +struct hif_hdr {
2060 + u8 client_id;
2061 + u8 q_num;
2062 + u16 client_ctrl;
2063 + u16 client_ctrl1;
2064 +};
2065 +
2066 +struct __hif_hdr {
2067 + union {
2068 + struct hif_hdr hdr;
2069 + u32 word[2];
2070 + };
2071 +};
2072 +
2073 +struct hif_ipsec_hdr {
2074 + u16 sa_handle[2];
2075 +} __packed;
2076 +
2077 +/* HIF_CTRL_TX... defines */
2078 +#define HIF_CTRL_TX_CHECKSUM BIT(2)
2079 +
2080 +/* HIF_CTRL_RX... defines */
2081 +#define HIF_CTRL_RX_OFFSET_OFST (24)
2082 +#define HIF_CTRL_RX_CHECKSUMMED BIT(2)
2083 +#define HIF_CTRL_RX_CONTINUED BIT(1)
2084 +
2085 +struct pfe_hif {
2086 + /* To store registered clients in hif layer */
2087 + struct hif_client client[HIF_CLIENTS_MAX];
2088 + struct hif_shm *shm;
2089 + int irq;
2090 +
2091 + void *descr_baseaddr_v;
2092 + unsigned long descr_baseaddr_p;
2093 +
2094 + struct hif_desc *rx_base;
2095 + u32 rx_ring_size;
2096 + u32 rxtoclean_index;
2097 + void *rx_buf_addr[HIF_RX_DESC_NT];
2098 + int rx_buf_len[HIF_RX_DESC_NT];
2099 + unsigned int qno;
2100 + unsigned int client_id;
2101 + unsigned int client_ctrl;
2102 + unsigned int started;
2103 +
2104 + struct hif_desc *tx_base;
2105 + u32 tx_ring_size;
2106 + u32 txtosend;
2107 + u32 txtoclean;
2108 + u32 txavail;
2109 + u32 txtoflush;
2110 + struct hif_desc_sw tx_sw_queue[HIF_TX_DESC_NT];
2111 +
2112 +/* tx_lock synchronizes hif packet tx as well as pfe_hif structure access */
2113 + spinlock_t tx_lock;
2114 +/* lock synchronizes hif rx queue processing */
2115 + spinlock_t lock;
2116 + struct net_device dummy_dev;
2117 + struct napi_struct napi;
2118 + struct device *dev;
2119 +
2120 +#ifdef HIF_NAPI_STATS
2121 + unsigned int napi_counters[NAPI_MAX_COUNT];
2122 +#endif
2123 + struct tasklet_struct tx_cleanup_tasklet;
2124 +};
2125 +
2126 +void __hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int
2127 + q_no, void *data, u32 len, unsigned int flags);
2128 +int hif_xmit_pkt(struct pfe_hif *hif, unsigned int client_id, unsigned int q_no,
2129 + void *data, unsigned int len);
2130 +void __hif_tx_done_process(struct pfe_hif *hif, int count);
2131 +void hif_process_client_req(struct pfe_hif *hif, int req, int data1, int
2132 + data2);
2133 +int pfe_hif_init(struct pfe *pfe);
2134 +void pfe_hif_exit(struct pfe *pfe);
2135 +void pfe_hif_rx_idle(struct pfe_hif *hif);
2136 +static inline void hif_tx_done_process(struct pfe_hif *hif, int count)
2137 +{
2138 + spin_lock_bh(&hif->tx_lock);
2139 + __hif_tx_done_process(hif, count);
2140 + spin_unlock_bh(&hif->tx_lock);
2141 +}
2142 +
2143 +static inline void hif_tx_lock(struct pfe_hif *hif)
2144 +{
2145 + spin_lock_bh(&hif->tx_lock);
2146 +}
2147 +
2148 +static inline void hif_tx_unlock(struct pfe_hif *hif)
2149 +{
2150 + spin_unlock_bh(&hif->tx_lock);
2151 +}
2152 +
2153 +static inline int __hif_tx_avail(struct pfe_hif *hif)
2154 +{
2155 + return hif->txavail;
2156 +}
2157 +
2158 +#define __memcpy8(dst, src) memcpy(dst, src, 8)
2159 +#define __memcpy12(dst, src) memcpy(dst, src, 12)
2160 +#define __memcpy(dst, src, len) memcpy(dst, src, len)
2161 +
2162 +#endif /* _PFE_HIF_H_ */
2163 --- /dev/null
2164 +++ b/drivers/staging/fsl_ppfe/pfe_hif_lib.h
2165 @@ -0,0 +1,239 @@
2166 +/*
2167 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
2168 + * Copyright 2017 NXP
2169 + *
2170 + * This program is free software; you can redistribute it and/or modify
2171 + * it under the terms of the GNU General Public License as published by
2172 + * the Free Software Foundation; either version 2 of the License, or
2173 + * (at your option) any later version.
2174 + *
2175 + * This program is distributed in the hope that it will be useful,
2176 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2177 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2178 + * GNU General Public License for more details.
2179 + *
2180 + * You should have received a copy of the GNU General Public License
2181 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2182 + */
2183 +
2184 +#ifndef _PFE_HIF_LIB_H_
2185 +#define _PFE_HIF_LIB_H_
2186 +
2187 +#include "pfe_hif.h"
2188 +
2189 +#define HIF_CL_REQ_TIMEOUT 10
2190 +#define GFP_DMA_PFE 0
2191 +
2192 +enum {
2193 + REQUEST_CL_REGISTER = 0,
2194 + REQUEST_CL_UNREGISTER,
2195 + HIF_REQUEST_MAX
2196 +};
2197 +
2198 +enum {
2199 + /* Event to indicate that client rx queue is reached water mark level */
2200 + EVENT_HIGH_RX_WM = 0,
2201 + /* Event to indicate that, packet received for client */
2202 + EVENT_RX_PKT_IND,
2203 + /* Event to indicate that, packet tx done for client */
2204 + EVENT_TXDONE_IND,
2205 + HIF_EVENT_MAX
2206 +};
2207 +
2208 +/*structure to store client queue info */
2209 +
2210 +/*structure to store client queue info */
2211 +struct hif_client_rx_queue {
2212 + struct rx_queue_desc *base;
2213 + u32 size;
2214 + u32 read_idx;
2215 + u32 write_idx;
2216 +};
2217 +
2218 +struct hif_client_tx_queue {
2219 + struct tx_queue_desc *base;
2220 + u32 size;
2221 + u32 read_idx;
2222 + u32 write_idx;
2223 + u32 tx_pending;
2224 + unsigned long jiffies_last_packet;
2225 + u32 nocpy_flag;
2226 + u32 prev_tmu_tx_pkts;
2227 + u32 done_tmu_tx_pkts;
2228 +};
2229 +
2230 +struct hif_client_s {
2231 + int id;
2232 + int tx_qn;
2233 + int rx_qn;
2234 + void *rx_qbase;
2235 + void *tx_qbase;
2236 + int tx_qsize;
2237 + int rx_qsize;
2238 + int cpu_id;
2239 + struct hif_client_tx_queue tx_q[HIF_CLIENT_QUEUES_MAX];
2240 + struct hif_client_rx_queue rx_q[HIF_CLIENT_QUEUES_MAX];
2241 + int (*event_handler)(void *priv, int event, int data);
2242 + unsigned long queue_mask[HIF_EVENT_MAX];
2243 + struct pfe *pfe;
2244 + void *priv;
2245 +};
2246 +
2247 +/*
2248 + * Client specific shared memory
2249 + * It contains number of Rx/Tx queues, base addresses and queue sizes
2250 + */
2251 +struct hif_client_shm {
2252 + u32 ctrl; /*0-7: number of Rx queues, 8-15: number of tx queues */
2253 + unsigned long rx_qbase; /*Rx queue base address */
2254 + u32 rx_qsize; /*each Rx queue size, all Rx queues are of same size */
2255 + unsigned long tx_qbase; /* Tx queue base address */
2256 + u32 tx_qsize; /*each Tx queue size, all Tx queues are of same size */
2257 +};
2258 +
2259 +/*Client shared memory ctrl bit description */
2260 +#define CLIENT_CTRL_RX_Q_CNT_OFST 0
2261 +#define CLIENT_CTRL_TX_Q_CNT_OFST 8
2262 +#define CLIENT_CTRL_RX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_RX_Q_CNT_OFST) \
2263 + & 0xFF)
2264 +#define CLIENT_CTRL_TX_Q_CNT(ctrl) (((ctrl) >> CLIENT_CTRL_TX_Q_CNT_OFST) \
2265 + & 0xFF)
2266 +
2267 +/*
2268 + * Shared memory used to communicate between HIF driver and host/client drivers
2269 + * Before starting the hif driver rx_buf_pool ans rx_buf_pool_cnt should be
2270 + * initialized with host buffers and buffers count in the pool.
2271 + * rx_buf_pool_cnt should be >= HIF_RX_DESC_NT.
2272 + *
2273 + */
2274 +struct hif_shm {
2275 + u32 rx_buf_pool_cnt; /*Number of rx buffers available*/
2276 + /*Rx buffers required to initialize HIF rx descriptors */
2277 + void *rx_buf_pool[HIF_RX_DESC_NT];
2278 + unsigned long g_client_status[2]; /*Global client status bit mask */
2279 + /* Client specific shared memory */
2280 + struct hif_client_shm client[HIF_CLIENTS_MAX];
2281 +};
2282 +
2283 +#define CL_DESC_OWN BIT(31)
2284 +/* This sets owner ship to HIF driver */
2285 +#define CL_DESC_LAST BIT(30)
2286 +/* This indicates last packet for multi buffers handling */
2287 +#define CL_DESC_FIRST BIT(29)
2288 +/* This indicates first packet for multi buffers handling */
2289 +
2290 +#define CL_DESC_BUF_LEN(x) ((x) & 0xFFFF)
2291 +#define CL_DESC_FLAGS(x) (((x) & 0xF) << 16)
2292 +#define CL_DESC_GET_FLAGS(x) (((x) >> 16) & 0xF)
2293 +
2294 +struct rx_queue_desc {
2295 + void *data;
2296 + u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
2297 + u32 client_ctrl;
2298 +};
2299 +
2300 +struct tx_queue_desc {
2301 + void *data;
2302 + u32 ctrl; /*0-15bit len, 16-20bit flags, 31bit owner*/
2303 +};
2304 +
2305 +/* HIF Rx is not working properly for 2-byte aligned buffers and
2306 + * ip_header should be 4byte aligned for better iperformance.
2307 + * "ip_header = 64 + 6(hif_header) + 14 (MAC Header)" will be 4byte aligned.
2308 + */
2309 +#define PFE_PKT_HEADER_SZ sizeof(struct hif_hdr)
2310 +/* must be big enough for headroom, pkt size and skb shared info */
2311 +#define PFE_BUF_SIZE 2048
2312 +#define PFE_PKT_HEADROOM 128
2313 +
2314 +#define SKB_SHARED_INFO_SIZE (sizeof(struct skb_shared_info))
2315 +#define PFE_PKT_SIZE (PFE_BUF_SIZE - PFE_PKT_HEADROOM \
2316 + - SKB_SHARED_INFO_SIZE)
2317 +#define MAX_L2_HDR_SIZE 14 /* Not correct for VLAN/PPPoE */
2318 +#define MAX_L3_HDR_SIZE 20 /* Not correct for IPv6 */
2319 +#define MAX_L4_HDR_SIZE 60 /* TCP with maximum options */
2320 +#define MAX_HDR_SIZE (MAX_L2_HDR_SIZE + MAX_L3_HDR_SIZE \
2321 + + MAX_L4_HDR_SIZE)
2322 +/* Used in page mode to clamp packet size to the maximum supported by the hif
2323 + *hw interface (<16KiB)
2324 + */
2325 +#define MAX_PFE_PKT_SIZE 16380UL
2326 +
2327 +extern unsigned int pfe_pkt_size;
2328 +extern unsigned int pfe_pkt_headroom;
2329 +extern unsigned int page_mode;
2330 +extern unsigned int lro_mode;
2331 +extern unsigned int tx_qos;
2332 +extern unsigned int emac_txq_cnt;
2333 +
2334 +int pfe_hif_lib_init(struct pfe *pfe);
2335 +void pfe_hif_lib_exit(struct pfe *pfe);
2336 +int hif_lib_client_register(struct hif_client_s *client);
2337 +int hif_lib_client_unregister(struct hif_client_s *client);
2338 +void __hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void
2339 + *data, unsigned int len, u32 client_ctrl,
2340 + unsigned int flags, void *client_data);
2341 +int hif_lib_xmit_pkt(struct hif_client_s *client, unsigned int qno, void *data,
2342 + unsigned int len, u32 client_ctrl, void *client_data);
2343 +void hif_lib_indicate_client(int cl_id, int event, int data);
2344 +int hif_lib_event_handler_start(struct hif_client_s *client, int event, int
2345 + data);
2346 +int hif_lib_tmu_queue_start(struct hif_client_s *client, int qno);
2347 +int hif_lib_tmu_queue_stop(struct hif_client_s *client, int qno);
2348 +void *hif_lib_tx_get_next_complete(struct hif_client_s *client, int qno,
2349 + unsigned int *flags, int count);
2350 +void *hif_lib_receive_pkt(struct hif_client_s *client, int qno, int *len, int
2351 + *ofst, unsigned int *rx_ctrl,
2352 + unsigned int *desc_ctrl, void **priv_data);
2353 +void hif_lib_set_rx_cpu_affinity(struct hif_client_s *client, int cpu_id);
2354 +void hif_lib_set_tx_queue_nocpy(struct hif_client_s *client, int qno, int
2355 + enable);
2356 +static inline int hif_lib_tx_avail(struct hif_client_s *client, unsigned int
2357 + qno)
2358 +{
2359 + struct hif_client_tx_queue *queue = &client->tx_q[qno];
2360 +
2361 + return (queue->size - queue->tx_pending);
2362 +}
2363 +
2364 +static inline int hif_lib_get_tx_wr_index(struct hif_client_s *client, unsigned
2365 + int qno)
2366 +{
2367 + struct hif_client_tx_queue *queue = &client->tx_q[qno];
2368 +
2369 + return queue->write_idx;
2370 +}
2371 +
2372 +static inline int hif_lib_tx_pending(struct hif_client_s *client, unsigned int
2373 + qno)
2374 +{
2375 + struct hif_client_tx_queue *queue = &client->tx_q[qno];
2376 +
2377 + return queue->tx_pending;
2378 +}
2379 +
2380 +#define hif_lib_tx_credit_avail(pfe, id, qno) \
2381 + ((pfe)->tmu_credit.tx_credit[id][qno])
2382 +
2383 +#define hif_lib_tx_credit_max(pfe, id, qno) \
2384 + ((pfe)->tmu_credit.tx_credit_max[id][qno])
2385 +
2386 +/*
2387 + * Test comment
2388 + */
2389 +#define hif_lib_tx_credit_use(pfe, id, qno, credit) \
2390 + ({ typeof(pfe) pfe_ = pfe; \
2391 + typeof(id) id_ = id; \
2392 + typeof(qno) qno_ = qno_; \
2393 + typeof(credit) credit_ = credit; \
2394 + do { \
2395 + if (tx_qos) { \
2396 + (pfe_)->tmu_credit.tx_credit[id_][qno_]\
2397 + -= credit_; \
2398 + (pfe_)->tmu_credit.tx_packets[id_][qno_]\
2399 + += credit_; \
2400 + } \
2401 + } while (0); \
2402 + })
2403 +
2404 +#endif /* _PFE_HIF_LIB_H_ */
2405 --- /dev/null
2406 +++ b/drivers/staging/fsl_ppfe/pfe_hw.h
2407 @@ -0,0 +1,27 @@
2408 +/*
2409 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
2410 + * Copyright 2017 NXP
2411 + *
2412 + * This program is free software; you can redistribute it and/or modify
2413 + * it under the terms of the GNU General Public License as published by
2414 + * the Free Software Foundation; either version 2 of the License, or
2415 + * (at your option) any later version.
2416 + *
2417 + * This program is distributed in the hope that it will be useful,
2418 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2419 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2420 + * GNU General Public License for more details.
2421 + *
2422 + * You should have received a copy of the GNU General Public License
2423 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2424 + */
2425 +
2426 +#ifndef _PFE_HW_H_
2427 +#define _PFE_HW_H_
2428 +
2429 +#define PE_SYS_CLK_RATIO 1 /* SYS/AXI = 250MHz, HFE = 500MHz */
2430 +
2431 +int pfe_hw_init(struct pfe *pfe, int resume);
2432 +void pfe_hw_exit(struct pfe *pfe);
2433 +
2434 +#endif /* _PFE_HW_H_ */
2435 --- /dev/null
2436 +++ b/drivers/staging/fsl_ppfe/pfe_mod.h
2437 @@ -0,0 +1,112 @@
2438 +/*
2439 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
2440 + * Copyright 2017 NXP
2441 + *
2442 + * This program is free software; you can redistribute it and/or modify
2443 + * it under the terms of the GNU General Public License as published by
2444 + * the Free Software Foundation; either version 2 of the License, or
2445 + * (at your option) any later version.
2446 + *
2447 + * This program is distributed in the hope that it will be useful,
2448 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2449 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2450 + * GNU General Public License for more details.
2451 + *
2452 + * You should have received a copy of the GNU General Public License
2453 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2454 + */
2455 +
2456 +#ifndef _PFE_MOD_H_
2457 +#define _PFE_MOD_H_
2458 +
2459 +#include <linux/device.h>
2460 +#include <linux/elf.h>
2461 +
2462 +struct pfe;
2463 +
2464 +#include "pfe_hw.h"
2465 +#include "pfe_firmware.h"
2466 +#include "pfe_ctrl.h"
2467 +#include "pfe_hif.h"
2468 +#include "pfe_hif_lib.h"
2469 +#include "pfe_eth.h"
2470 +#include "pfe_sysfs.h"
2471 +#include "pfe_perfmon.h"
2472 +#include "pfe_debugfs.h"
2473 +
2474 +#define PHYID_MAX_VAL 32
2475 +
2476 +struct pfe_tmu_credit {
2477 + /* Number of allowed TX packet in-flight, matches TMU queue size */
2478 + unsigned int tx_credit[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
2479 + unsigned int tx_credit_max[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
2480 + unsigned int tx_packets[NUM_GEMAC_SUPPORT][EMAC_TXQ_CNT];
2481 +};
2482 +
2483 +struct pfe {
2484 + struct regmap *scfg;
2485 + unsigned long ddr_phys_baseaddr;
2486 + void *ddr_baseaddr;
2487 + unsigned int ddr_size;
2488 + void *cbus_baseaddr;
2489 + void *apb_baseaddr;
2490 + unsigned long iram_phys_baseaddr;
2491 + void *iram_baseaddr;
2492 + unsigned long ipsec_phys_baseaddr;
2493 + void *ipsec_baseaddr;
2494 + int hif_irq;
2495 + int wol_irq;
2496 + int hif_client_irq;
2497 + struct device *dev;
2498 + struct dentry *dentry;
2499 + struct pfe_ctrl ctrl;
2500 + struct pfe_hif hif;
2501 + struct pfe_eth eth;
2502 + struct hif_client_s *hif_client[HIF_CLIENTS_MAX];
2503 +#if defined(CFG_DIAGS)
2504 + struct pfe_diags diags;
2505 +#endif
2506 + struct pfe_tmu_credit tmu_credit;
2507 + struct pfe_cpumon cpumon;
2508 + struct pfe_memmon memmon;
2509 + int wake;
2510 + int mdio_muxval[PHYID_MAX_VAL];
2511 + struct clk *hfe_clock;
2512 +};
2513 +
2514 +extern struct pfe *pfe;
2515 +
2516 +int pfe_probe(struct pfe *pfe);
2517 +int pfe_remove(struct pfe *pfe);
2518 +
2519 +/* DDR Mapping in reserved memory*/
2520 +#define ROUTE_TABLE_BASEADDR 0
2521 +#define ROUTE_TABLE_HASH_BITS 15 /* 32K entries */
2522 +#define ROUTE_TABLE_SIZE ((1 << ROUTE_TABLE_HASH_BITS) \
2523 + * CLASS_ROUTE_SIZE)
2524 +#define BMU2_DDR_BASEADDR (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
2525 +#define BMU2_BUF_COUNT (4096 - 256)
2526 +/* This is to get a total DDR size of 12MiB */
2527 +#define BMU2_DDR_SIZE (DDR_BUF_SIZE * BMU2_BUF_COUNT)
2528 +#define UTIL_CODE_BASEADDR (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
2529 +#define UTIL_CODE_SIZE (128 * SZ_1K)
2530 +#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
2531 +#define UTIL_DDR_DATA_SIZE (64 * SZ_1K)
2532 +#define CLASS_DDR_DATA_BASEADDR (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
2533 +#define CLASS_DDR_DATA_SIZE (32 * SZ_1K)
2534 +#define TMU_DDR_DATA_BASEADDR (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
2535 +#define TMU_DDR_DATA_SIZE (32 * SZ_1K)
2536 +#define TMU_LLM_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
2537 +#define TMU_LLM_QUEUE_LEN (8 * 512)
2538 +/* Must be power of two and at least 16 * 8 = 128 bytes */
2539 +#define TMU_LLM_SIZE (4 * 16 * TMU_LLM_QUEUE_LEN)
2540 +/* (4 TMU's x 16 queues x queue_len) */
2541 +
2542 +#define DDR_MAX_SIZE (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
2543 +
2544 +/* LMEM Mapping */
2545 +#define BMU1_LMEM_BASEADDR 0
2546 +#define BMU1_BUF_COUNT 256
2547 +#define BMU1_LMEM_SIZE (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
2548 +
2549 +#endif /* _PFE_MOD_H */
2550 --- /dev/null
2551 +++ b/drivers/staging/fsl_ppfe/pfe_perfmon.h
2552 @@ -0,0 +1,38 @@
2553 +/*
2554 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
2555 + * Copyright 2017 NXP
2556 + *
2557 + * This program is free software; you can redistribute it and/or modify
2558 + * it under the terms of the GNU General Public License as published by
2559 + * the Free Software Foundation; either version 2 of the License, or
2560 + * (at your option) any later version.
2561 + *
2562 + * This program is distributed in the hope that it will be useful,
2563 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2564 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2565 + * GNU General Public License for more details.
2566 + *
2567 + * You should have received a copy of the GNU General Public License
2568 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2569 + */
2570 +
2571 +#ifndef _PFE_PERFMON_H_
2572 +#define _PFE_PERFMON_H_
2573 +
2574 +#include "pfe/pfe.h"
2575 +
2576 +#define CT_CPUMON_INTERVAL (1 * TIMER_TICKS_PER_SEC)
2577 +
2578 +struct pfe_cpumon {
2579 + u32 cpu_usage_pct[MAX_PE];
2580 + u32 class_usage_pct;
2581 +};
2582 +
2583 +struct pfe_memmon {
2584 + u32 kernel_memory_allocated;
2585 +};
2586 +
2587 +int pfe_perfmon_init(struct pfe *pfe);
2588 +void pfe_perfmon_exit(struct pfe *pfe);
2589 +
2590 +#endif /* _PFE_PERFMON_H_ */
2591 --- /dev/null
2592 +++ b/drivers/staging/fsl_ppfe/pfe_sysfs.h
2593 @@ -0,0 +1,29 @@
2594 +/*
2595 + * Copyright 2015-2016 Freescale Semiconductor, Inc.
2596 + * Copyright 2017 NXP
2597 + *
2598 + * This program is free software; you can redistribute it and/or modify
2599 + * it under the terms of the GNU General Public License as published by
2600 + * the Free Software Foundation; either version 2 of the License, or
2601 + * (at your option) any later version.
2602 + *
2603 + * This program is distributed in the hope that it will be useful,
2604 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2605 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2606 + * GNU General Public License for more details.
2607 + *
2608 + * You should have received a copy of the GNU General Public License
2609 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
2610 + */
2611 +
2612 +#ifndef _PFE_SYSFS_H_
2613 +#define _PFE_SYSFS_H_
2614 +
2615 +#include <linux/proc_fs.h>
2616 +
2617 +u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset);
2618 +
2619 +int pfe_sysfs_init(struct pfe *pfe);
2620 +void pfe_sysfs_exit(struct pfe *pfe);
2621 +
2622 +#endif /* _PFE_SYSFS_H_ */
Staging tree of Zoltan Herpai