target/linux/layerscape/patches-5.4/804-crypto-0017-MLKU-114-2-crypto-caam-SCU-firmware-support.patch

   1 From b752c8ed4ab83d47a585c363056d64fb978ef481 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
   3 Date: Fri, 27 Sep 2019 20:05:26 +0300
   4 Subject: [PATCH] MLKU-114-2 crypto: caam - SCU firmware support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Some i.MX8 processors, e.g. i.MX8QM (QM, QP), i.MX8QX (QXP, DX) have a
  10 System Controller Firmware (SCFW) running on a dedicated Cortex-M core
  11 that provides power, clock, and resource management.
  12
  13 caam driver needs to be aware of SCU f/w presence, since some things
  14 are done differently:
  15
  16 1. clocks are under SCU f/w control and are turned on automatically
  17
  18 2. there is no access to controller's register page (note however that
  19 some registers are aliased in job rings' register pages)
  20
  21 It's worth mentioning that due to this, MCFGR[PS] cannot be read
  22 and driver assumes MCFGR[PS] = b'0 - engine using 32-bit address pointers.
  23 This is in sync with the limitation imposed by the
  24 SECO (Security Controller) ROM and f/w running on a dedicated Cortex-M.
  25
  26 3. as a consequence of "2.", part of the initialization is moved in
  27 other f/w (SCU, TF-A etc.), e.g. RNG initialization
  28
  29 Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
  30 ---
  31  drivers/crypto/caam/ctrl.c   | 28 ++++++++++++++++++++++++++--
  32  drivers/crypto/caam/intern.h |  1 +
  33  2 files changed, 27 insertions(+), 2 deletions(-)
  34
  35 --- a/drivers/crypto/caam/ctrl.c
  36 +++ b/drivers/crypto/caam/ctrl.c
  37 @@ -596,6 +596,17 @@ static int caam_probe(struct platform_de
  38         caam_imx = (bool)imx_soc_match;
  39
  40         if (imx_soc_match) {
  41 +               np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu");
  42 +               ctrlpriv->scu_en = !!np;
  43 +               of_node_put(np);
  44 +
  45 +               /*
  46 +                * CAAM clocks cannot be controlled from kernel.
  47 +                * They are automatically turned on by SCU f/w.
  48 +                */
  49 +               if (ctrlpriv->scu_en)
  50 +                       goto iomap_ctrl;
  51 +
  52                 if (!imx_soc_match->data) {
  53                         dev_err(dev, "No clock data provided for i.MX SoC");
  54                         return -EINVAL;
  55 @@ -606,7 +617,7 @@ static int caam_probe(struct platform_de
  56                         return ret;
  57         }
  58
  59 -
  60 +iomap_ctrl:
  61         /* Get configuration properties from device tree */
  62         /* First, get register page */
  63         ctrl = devm_of_iomap(dev, nprop, 0, NULL);
  64 @@ -646,7 +657,8 @@ static int caam_probe(struct platform_de
  65         caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
  66                                   (CSTA_PLEND | CSTA_ALT_PLEND));
  67         comp_params = rd_reg32(&perfmon->comp_parms_ms);
  68 -       if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
  69 +       if (!ctrlpriv->scu_en && comp_params & CTPR_MS_PS &&
  70 +           rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
  71                 caam_ptr_sz = sizeof(u64);
  72         else
  73                 caam_ptr_sz = sizeof(u32);
  74 @@ -696,6 +708,9 @@ static int caam_probe(struct platform_de
  75         /* Get the IRQ of the controller (for security violations only) */
  76         ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
  77
  78 +       if (ctrlpriv->scu_en)
  79 +               goto set_dma_mask;
  80 +
  81         /*
  82          * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
  83          * long pointers in master configuration register.
  84 @@ -739,6 +754,7 @@ static int caam_probe(struct platform_de
  85                               JRSTART_JR1_START | JRSTART_JR2_START |
  86                               JRSTART_JR3_START);
  87
  88 +set_dma_mask:
  89         ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
  90         if (ret) {
  91                 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
  92 @@ -785,6 +801,9 @@ static int caam_probe(struct platform_de
  93                 return -ENOMEM;
  94         }
  95
  96 +       if (ctrlpriv->scu_en)
  97 +               goto report_live;
  98 +
  99         if (ctrlpriv->era < 10) {
 100                 rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
 101                            CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
 102 @@ -865,6 +884,7 @@ static int caam_probe(struct platform_de
 103
 104         /* NOTE: RTIC detection ought to go here, around Si time */
 105
 106 +report_live:
 107         caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
 108                   (u64)rd_reg32(&perfmon->caam_id_ls);
 109
 110 @@ -908,6 +928,9 @@ static int caam_probe(struct platform_de
 111                             ctrlpriv->ctl, &perfmon->status,
 112                             &caam_fops_u32_ro);
 113
 114 +       if (ctrlpriv->scu_en)
 115 +               goto probe_jrs;
 116 +
 117         /* Internal covering keys (useful in non-secure mode only) */
 118         ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
 119         ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
 120 @@ -925,6 +948,7 @@ static int caam_probe(struct platform_de
 121                             &ctrlpriv->ctl_tdsk_wrap);
 122  #endif
 123
 124 +probe_jrs:
 125         ret = devm_of_platform_populate(dev);
 126         if (ret)
 127                 dev_err(dev, "JR platform devices creation error\n");
 128 --- a/drivers/crypto/caam/intern.h
 129 +++ b/drivers/crypto/caam/intern.h
 130 @@ -82,6 +82,7 @@ struct caam_drv_private {
 131         u8 total_jobrs;         /* Total Job Rings in device */
 132         u8 qi_present;          /* Nonzero if QI present in device */
 133         u8 mc_en;               /* Nonzero if MC f/w is active */
 134 +       u8 scu_en;              /* Nonzero if SCU f/w is active */
 135         int secvio_irq;         /* Security violation interrupt number */
 136         int virt_en;            /* Virtualization enabled in CAAM */
 137         int era;                /* CAAM Era (internal HW revision) */