target/linux/layerscape/patches-5.4/812-pcie-0017-PCI-mobiveil-Add-PCIe-Gen4-EP-driver-for-NXP-Layersc.patch

   1 From 9e1faafe9d650a06e212ad5a3b8ed0e7eb7f0aa2 Mon Sep 17 00:00:00 2001
   2 From: Xiaowei Bao <xiaowei.bao@nxp.com>
   3 Date: Sat, 5 Jan 2019 16:30:42 +0800
   4 Subject: [PATCH] PCI: mobiveil: Add PCIe Gen4 EP driver for NXP Layerscape
   5  SoCs
   6
   7 This PCIe controller is based on the Mobiveil GPEX IP, it work in EP
   8 mode if select this config opteration.
   9
  10 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
  11 [Zhiqiang: Correct the Copyright]
  12 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  13 [drop maintainer change]
  14 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
  15 ---
  16  drivers/pci/controller/mobiveil/Kconfig            |  17 ++-
  17  drivers/pci/controller/mobiveil/Makefile           |   1 +
  18  .../controller/mobiveil/pcie-layerscape-gen4-ep.c  | 156 +++++++++++++++++++++
  19  3 files changed, 171 insertions(+), 3 deletions(-)
  20  create mode 100644 drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
  21
  22 --- a/drivers/pci/controller/mobiveil/Kconfig
  23 +++ b/drivers/pci/controller/mobiveil/Kconfig
  24 @@ -27,13 +27,24 @@ config PCIE_MOBIVEIL_PLAT
  25           for address translation and it is a PCIe Gen4 IP.
  26
  27  config PCIE_LAYERSCAPE_GEN4
  28 -       bool "Freescale Layerscape PCIe Gen4 controller"
  29 +       bool "Freescale Layerscpe PCIe Gen4 controller in RC mode"
  30         depends on PCI
  31         depends on OF && (ARM64 || ARCH_LAYERSCAPE)
  32         depends on PCI_MSI_IRQ_DOMAIN
  33         select PCIE_MOBIVEIL_HOST
  34         help
  35           Say Y here if you want PCIe Gen4 controller support on
  36 -         Layerscape SoCs. The PCIe controller can work in RC or
  37 -         EP mode according to RCW[HOST_AGT_PEX] setting.
  38 +         Layerscape SoCs. And the PCIe controller work in RC mode
  39 +         by setting the RCW[HOST_AGT_PEX] to 0.
  40 +
  41 +config PCIE_LAYERSCAPE_GEN4_EP
  42 +       bool "Freescale Layerscpe PCIe Gen4 controller in EP mode"
  43 +       depends on PCI
  44 +       depends on OF && (ARM64 || ARCH_LAYERSCAPE)
  45 +       depends on PCI_ENDPOINT
  46 +       select PCIE_MOBIVEIL_EP
  47 +       help
  48 +         Say Y here if you want PCIe Gen4 controller support on
  49 +         Layerscape SoCs. And the PCIe controller work in EP mode
  50 +         by setting the RCW[HOST_AGT_PEX] to 1.
  51  endmenu
  52 --- a/drivers/pci/controller/mobiveil/Makefile
  53 +++ b/drivers/pci/controller/mobiveil/Makefile
  54 @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie
  55  obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
  56  obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
  57  obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
  58 +obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4_EP) += pcie-layerscape-gen4-ep.o
  59 --- /dev/null
  60 +++ b/drivers/pci/controller/mobiveil/pcie-layerscape-gen4-ep.c
  61 @@ -0,0 +1,156 @@
  62 +// SPDX-License-Identifier: GPL-2.0
  63 +/*
  64 + * PCIe controller EP driver for Freescale Layerscape SoCs
  65 + *
  66 + * Copyright 2019 NXP
  67 + *
  68 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
  69 + */
  70 +
  71 +#include <linux/kernel.h>
  72 +#include <linux/init.h>
  73 +#include <linux/of_pci.h>
  74 +#include <linux/of_platform.h>
  75 +#include <linux/of_address.h>
  76 +#include <linux/pci.h>
  77 +#include <linux/platform_device.h>
  78 +#include <linux/resource.h>
  79 +
  80 +#include "pcie-mobiveil.h"
  81 +
  82 +#define PCIE_LX2_BAR_NUM       4
  83 +
  84 +#define to_ls_pcie_g4_ep(x)    dev_get_drvdata((x)->dev)
  85 +
  86 +struct ls_pcie_g4_ep {
  87 +       struct mobiveil_pcie            *mv_pci;
  88 +};
  89 +
  90 +static const struct of_device_id ls_pcie_g4_ep_of_match[] = {
  91 +       { .compatible = "fsl,lx2160a-pcie-ep",},
  92 +       { },
  93 +};
  94 +
  95 +static const struct pci_epc_features ls_pcie_g4_epc_features = {
  96 +       .linkup_notifier = false,
  97 +       .msi_capable = true,
  98 +       .msix_capable = true,
  99 +       .reserved_bar = (1 << BAR_4) | (1 << BAR_5),
 100 +};
 101 +
 102 +static const struct pci_epc_features*
 103 +ls_pcie_g4_ep_get_features(struct mobiveil_pcie_ep *ep)
 104 +{
 105 +       return &ls_pcie_g4_epc_features;
 106 +}
 107 +
 108 +static void ls_pcie_g4_ep_init(struct mobiveil_pcie_ep *ep)
 109 +{
 110 +       struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
 111 +       int win_idx;
 112 +       u8 bar;
 113 +
 114 +       ep->bar_num = PCIE_LX2_BAR_NUM;
 115 +
 116 +       for (bar = BAR_0; bar < ep->epc->max_functions * ep->bar_num; bar++)
 117 +               mobiveil_pcie_ep_reset_bar(mv_pci, bar);
 118 +
 119 +       for (win_idx = 0; win_idx < ep->apio_wins; win_idx++)
 120 +               mobiveil_pcie_disable_ob_win(mv_pci, win_idx);
 121 +}
 122 +
 123 +static int ls_pcie_g4_ep_raise_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
 124 +                                  enum pci_epc_irq_type type,
 125 +                                  u16 interrupt_num)
 126 +{
 127 +       struct mobiveil_pcie *mv_pci = to_mobiveil_pcie_from_ep(ep);
 128 +
 129 +       switch (type) {
 130 +       case PCI_EPC_IRQ_LEGACY:
 131 +               return mobiveil_pcie_ep_raise_legacy_irq(ep, func_no);
 132 +       case PCI_EPC_IRQ_MSI:
 133 +               return mobiveil_pcie_ep_raise_msi_irq(ep, func_no,
 134 +                                                     interrupt_num);
 135 +       case PCI_EPC_IRQ_MSIX:
 136 +               return mobiveil_pcie_ep_raise_msix_irq(ep, func_no,
 137 +                                                      interrupt_num);
 138 +       default:
 139 +               dev_err(&mv_pci->pdev->dev, "UNKNOWN IRQ type\n");
 140 +       }
 141 +
 142 +       return 0;
 143 +}
 144 +
 145 +static const struct mobiveil_pcie_ep_ops pcie_ep_ops = {
 146 +       .ep_init = ls_pcie_g4_ep_init,
 147 +       .raise_irq = ls_pcie_g4_ep_raise_irq,
 148 +       .get_features = ls_pcie_g4_ep_get_features,
 149 +};
 150 +
 151 +static int __init ls_pcie_gen4_add_pcie_ep(struct ls_pcie_g4_ep *ls_ep,
 152 +                                          struct platform_device *pdev)
 153 +{
 154 +       struct mobiveil_pcie *mv_pci = ls_ep->mv_pci;
 155 +       struct device *dev = &pdev->dev;
 156 +       struct mobiveil_pcie_ep *ep;
 157 +       struct resource *res;
 158 +       int ret;
 159 +
 160 +       ep = &mv_pci->ep;
 161 +       ep->ops = &pcie_ep_ops;
 162 +
 163 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
 164 +       if (!res)
 165 +               return -EINVAL;
 166 +
 167 +       ep->phys_base = res->start;
 168 +       ep->addr_size = resource_size(res);
 169 +
 170 +       ret = mobiveil_pcie_ep_init(ep);
 171 +       if (ret) {
 172 +               dev_err(dev, "failed to initialize layerscape endpoint\n");
 173 +               return ret;
 174 +       }
 175 +
 176 +       return 0;
 177 +}
 178 +
 179 +static int __init ls_pcie_g4_ep_probe(struct platform_device *pdev)
 180 +{
 181 +       struct device *dev = &pdev->dev;
 182 +       struct mobiveil_pcie *mv_pci;
 183 +       struct ls_pcie_g4_ep *ls_ep;
 184 +       struct resource *res;
 185 +       int ret;
 186 +
 187 +       ls_ep = devm_kzalloc(dev, sizeof(*ls_ep), GFP_KERNEL);
 188 +       if (!ls_ep)
 189 +               return -ENOMEM;
 190 +
 191 +       mv_pci = devm_kzalloc(dev, sizeof(*mv_pci), GFP_KERNEL);
 192 +       if (!mv_pci)
 193 +               return -ENOMEM;
 194 +
 195 +       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
 196 +       mv_pci->csr_axi_slave_base = devm_pci_remap_cfg_resource(dev, res);
 197 +       if (IS_ERR(mv_pci->csr_axi_slave_base))
 198 +               return PTR_ERR(mv_pci->csr_axi_slave_base);
 199 +
 200 +       mv_pci->pdev = pdev;
 201 +       ls_ep->mv_pci = mv_pci;
 202 +
 203 +       platform_set_drvdata(pdev, ls_ep);
 204 +
 205 +       ret = ls_pcie_gen4_add_pcie_ep(ls_ep, pdev);
 206 +
 207 +       return ret;
 208 +}
 209 +
 210 +static struct platform_driver ls_pcie_g4_ep_driver = {
 211 +       .driver = {
 212 +               .name = "layerscape-pcie-gen4-ep",
 213 +               .of_match_table = ls_pcie_g4_ep_of_match,
 214 +               .suppress_bind_attrs = true,
 215 +       },
 216 +};
 217 +builtin_platform_driver_probe(ls_pcie_g4_ep_driver, ls_pcie_g4_ep_probe);