target/linux/magicbox/files/drivers/ide/ppc/magicbox_ide.c

   1 /*
   2  * Driver for MagicBox 2.0 onboard CompactFlash adapter.
   3  *
   4  * Written by Wojtek Kaniewski <wojtekka@toxygen.net>
   5  * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * GNU General Public License.
   8  */
   9
  10 #include <linux/version.h>
  11 #include <linux/types.h>
  12 #include <linux/mm.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/blkdev.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/delay.h>
  18 #include <linux/platform_device.h>
  19
  20 #define UIC0_PR         0xc4
  21 #define UIC0_TR         0xc5
  22 #define MAGICBOX_CF_IRQ 25
  23
  24 static u8 magicbox_ide_inb(unsigned long port)
  25 {
  26         return (u8) (readw((void __iomem *) port) >> 8) & 0xff;
  27 }
  28
  29 static void magicbox_ide_outb(u8 value, unsigned long port)
  30 {
  31         writew(value << 8, (void __iomem *) port);
  32 }
  33
  34 static void magicbox_ide_outbsync(ide_drive_t *drive, u8 value,
  35                                   unsigned long port)
  36 {
  37         writew(value << 8, (void __iomem *) port);
  38 }
  39
  40 static inline void magicbox_ide_insw(unsigned long port, void *addr, u32 count)
  41 {
  42         u16 *ptr;
  43
  44         for (ptr = addr; count--; ptr++)
  45                 *ptr = readw((void __iomem *) port);
  46 }
  47
  48 static inline void magicbox_ide_insl(unsigned long port, void *addr, u32 count)
  49 {
  50         u32 *ptr;
  51
  52         for (ptr = addr; count--; ptr++)
  53                 *ptr = readl((void __iomem *) port);
  54 }
  55
  56 static inline void magicbox_ide_outsw(unsigned long port, void *addr,
  57                                         u32 count)
  58 {
  59         u16 *ptr;
  60
  61         for (ptr = addr; count--; ptr++)
  62                 writew(*ptr, (void __iomem *) port);
  63 }
  64
  65 static inline void magicbox_ide_outsl(unsigned long port, void *addr,
  66                                         u32 count)
  67 {
  68         u32 *ptr;
  69
  70         for (ptr = addr; count--; ptr++)
  71                 writel(*ptr, (void __iomem *) port);
  72 }
  73
  74 static void magicbox_ide_tf_load(ide_drive_t *drive, ide_task_t *task)
  75 {
  76         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
  77         struct ide_taskfile *tf = &task->tf;
  78         u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
  79
  80         if (task->tf_flags & IDE_TFLAG_FLAGGED)
  81                 HIHI = 0xFF;
  82
  83         ide_set_irq(drive, 1);
  84
  85         if (task->tf_flags & IDE_TFLAG_OUT_DATA)
  86                 writel((tf->hob_data << 8) | tf->data,
  87                         (void __iomem *) io_ports->data_addr);
  88
  89         if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
  90                 magicbox_ide_outb(tf->hob_feature, io_ports->feature_addr);
  91         if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
  92                 magicbox_ide_outb(tf->hob_nsect, io_ports->nsect_addr);
  93         if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
  94                 magicbox_ide_outb(tf->hob_lbal, io_ports->lbal_addr);
  95         if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
  96                 magicbox_ide_outb(tf->hob_lbam, io_ports->lbam_addr);
  97         if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
  98                 magicbox_ide_outb(tf->hob_lbah, io_ports->lbah_addr);
  99
 100         if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
 101                 magicbox_ide_outb(tf->feature, io_ports->feature_addr);
 102         if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
 103                 magicbox_ide_outb(tf->nsect, io_ports->nsect_addr);
 104         if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
 105                 magicbox_ide_outb(tf->lbal, io_ports->lbal_addr);
 106         if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
 107                 magicbox_ide_outb(tf->lbam, io_ports->lbam_addr);
 108         if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
 109                 magicbox_ide_outb(tf->lbah, io_ports->lbah_addr);
 110
 111         if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
 112                 magicbox_ide_outb((tf->device & HIHI) | drive->select.all,
 113                              io_ports->device_addr);
 114 }
 115
 116 static void magicbox_ide_tf_read(ide_drive_t *drive, ide_task_t *task)
 117 {
 118         struct ide_io_ports *io_ports = &drive->hwif->io_ports;
 119         struct ide_taskfile *tf = &task->tf;
 120
 121         if (task->tf_flags & IDE_TFLAG_IN_DATA) {
 122                 u16 data = (u16) readl((void __iomem *) io_ports->data_addr);
 123
 124                 tf->data = data & 0xff;
 125                 tf->hob_data = (data >> 8) & 0xff;
 126         }
 127
 128         /* be sure we're looking at the low order bits */
 129         magicbox_ide_outb(drive->ctl & ~0x80, io_ports->ctl_addr);
 130
 131         if (task->tf_flags & IDE_TFLAG_IN_NSECT)
 132                 tf->nsect  = magicbox_ide_inb(io_ports->nsect_addr);
 133         if (task->tf_flags & IDE_TFLAG_IN_LBAL)
 134                 tf->lbal   = magicbox_ide_inb(io_ports->lbal_addr);
 135         if (task->tf_flags & IDE_TFLAG_IN_LBAM)
 136                 tf->lbam   = magicbox_ide_inb(io_ports->lbam_addr);
 137         if (task->tf_flags & IDE_TFLAG_IN_LBAH)
 138                 tf->lbah   = magicbox_ide_inb(io_ports->lbah_addr);
 139         if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
 140                 tf->device = magicbox_ide_inb(io_ports->device_addr);
 141
 142         if (task->tf_flags & IDE_TFLAG_LBA48) {
 143                 magicbox_ide_outb(drive->ctl | 0x80, io_ports->ctl_addr);
 144
 145                 if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
 146                         tf->hob_feature = magicbox_ide_inb(io_ports->feature_addr);
 147                 if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
 148                         tf->hob_nsect   = magicbox_ide_inb(io_ports->nsect_addr);
 149                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
 150                         tf->hob_lbal    = magicbox_ide_inb(io_ports->lbal_addr);
 151                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
 152                         tf->hob_lbam    = magicbox_ide_inb(io_ports->lbam_addr);
 153                 if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
 154                         tf->hob_lbah    = magicbox_ide_inb(io_ports->lbah_addr);
 155         }
 156 }
 157
 158 static void magicbox_ide_input_data(ide_drive_t *drive, struct request *rq,
 159                            void *buf, unsigned int len)
 160 {
 161         unsigned long port = drive->hwif->io_ports.data_addr;
 162
 163         len++;
 164
 165         if (drive->io_32bit) {
 166                 magicbox_ide_insl(port, buf, len / 4);
 167
 168                 if ((len & 3) >= 2)
 169                         magicbox_ide_insw(port, (u8 *)buf + (len & ~3), 1);
 170         } else
 171                 magicbox_ide_insw(port, buf, len / 2);
 172 }
 173
 174 static void magicbox_ide_output_data(ide_drive_t *drive,  struct request *rq,
 175                             void *buf, unsigned int len)
 176 {
 177         unsigned long port = drive->hwif->io_ports.data_addr;
 178
 179         len++;
 180
 181         if (drive->io_32bit) {
 182                 magicbox_ide_outsl(port, buf, len / 4);
 183
 184                 if ((len & 3) >= 2)
 185                         magicbox_ide_outsw(port, (u8 *)buf + (len & ~3), 1);
 186         } else
 187                 magicbox_ide_outsw(port, buf, len / 2);
 188 }
 189
 190 static void __init magicbox_ide_setup_hw(hw_regs_t *hw, u16 __iomem *base,
 191                                         u16 __iomem *ctrl, int irq)
 192 {
 193         unsigned long port = (unsigned long) base;
 194         int i;
 195
 196         memset(hw, 0, sizeof(*hw));
 197         for (i = 0; i <= 7; i++)
 198                 hw->io_ports_array[i] = port + i * 2;
 199
 200         /*
 201          * the IDE control register is at ATA address 6,
 202          * with CS1 active instead of CS0
 203          */
 204         hw->io_ports.ctl_addr = (unsigned long)ctrl + (6 * 2);
 205
 206         hw->irq = irq;
 207
 208         hw->chipset = ide_generic;
 209         hw->ack_intr = NULL;
 210 }
 211
 212 static int __init magibox_ide_probe(void)
 213 {
 214         hw_regs_t hw;
 215         ide_hwif_t *hwif;
 216         u16 __iomem *base;
 217         u16 __iomem *ctrl;
 218         u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
 219         int err;
 220
 221         /* Remap physical address space */
 222         base = ioremap_nocache(0xff100000, 4096);
 223         if (base == NULL) {
 224                 err = -EBUSY;
 225                 goto err_out;
 226         }
 227
 228         ctrl = ioremap_nocache(0xff200000, 4096);
 229         if (ctrl == NULL) {
 230                 err = -EBUSY;
 231                 goto err_unmap_base;
 232         }
 233
 234         magicbox_ide_setup_hw(&hw, base, ctrl, MAGICBOX_CF_IRQ);
 235
 236         hwif = ide_find_port();
 237         if (!hwif) {
 238                 err = -ENODEV;
 239                 goto err_unmap_ctrl;
 240         }
 241
 242         ide_init_port_data(hwif, hwif->index);
 243         ide_init_port_hw(hwif, &hw);
 244
 245         hwif->host_flags = IDE_HFLAG_MMIO;
 246
 247         hwif->tf_load = magicbox_ide_tf_load;
 248         hwif->tf_read = magicbox_ide_tf_read;
 249
 250         hwif->input_data  = magicbox_ide_input_data;
 251         hwif->output_data = magicbox_ide_output_data;
 252
 253         hwif->drives[0].unmask = 1;
 254         hwif->OUTB = magicbox_ide_outb;
 255         hwif->OUTBSYNC = magicbox_ide_outbsync;
 256         hwif->INB = magicbox_ide_inb;
 257
 258         printk(KERN_INFO "ide%d: Magicbox CF interface\n", hwif->index);
 259
 260         idx[0] = hwif->index;
 261
 262         ide_device_add(idx, NULL);
 263
 264         return 0;
 265
 266 err_unmap_ctrl:
 267         iounmap(ctrl);
 268 err_unmap_base:
 269         iounmap(base);
 270 err_out:
 271         return err;
 272 }
 273
 274 static int __init magicbox_ide_init(void)
 275 {
 276         /* Turn on PerWE instead of PCIsomething */
 277         mtdcr(DCRN_CPC0_PCI_BASE,
 278                         mfdcr(DCRN_CPC0_PCI_BASE) | (0x80000000L >> 27));
 279
 280         /* PerCS1 (CF's CS0): base 0xff100000, 16-bit, rw */
 281         mtdcr(DCRN_EBC_BASE, 1);
 282         mtdcr(DCRN_EBC_BASE + 1, 0xff11a000);
 283         mtdcr(DCRN_EBC_BASE, 0x11);
 284         mtdcr(DCRN_EBC_BASE + 1, 0x080bd800);
 285
 286         /* PerCS2 (CF's CS1): base 0xff200000, 16-bit, rw */
 287         mtdcr(DCRN_EBC_BASE, 2);
 288         mtdcr(DCRN_EBC_BASE + 1, 0xff21a000);
 289         mtdcr(DCRN_EBC_BASE, 0x12);
 290         mtdcr(DCRN_EBC_BASE + 1, 0x080bd800);
 291
 292         /* Set interrupt to low-to-high-edge-triggered */
 293         mtdcr(UIC0_TR, mfdcr(UIC0_TR) & ~(0x80000000L >> MAGICBOX_CF_IRQ));
 294         mtdcr(UIC0_PR, mfdcr(UIC0_PR) | (0x80000000L >> MAGICBOX_CF_IRQ));
 295
 296         return magibox_ide_probe();
 297 }
 298
 299 module_init(magicbox_ide_init);
 300
 301 MODULE_LICENSE("GPL");