1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
3 * Copyright (C) 2023 Tianling Shen <cnsztl@immortalwrt.org>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/leds/common.h>
11 #include "mt7986a.dtsi"
14 model = "JDCloud RE-CP-03";
15 compatible = "jdcloud,re-cp-03", "mediatek,mt7986a";
19 led-failsafe = &red_led;
20 led-running = &green_led;
21 led-upgrade = &green_led;
26 bootargs-override = "root=/dev/fit0 rootwait";
27 stdout-path = "serial0:115200n8";
28 rootdisk = <&emmc_rootdisk>;
32 reg = <0 0x40000000 0 0x40000000>;
36 compatible = "gpio-keys";
41 gpios = <&pio 10 GPIO_ACTIVE_LOW>;
46 linux,code = <KEY_RESTART>;
47 gpios = <&pio 9 GPIO_ACTIVE_LOW>;
52 compatible = "gpio-leds";
55 color = <LED_COLOR_ID_BLUE>;
56 function = LED_FUNCTION_STATUS;
57 gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
61 color = <LED_COLOR_ID_RED>;
62 function = LED_FUNCTION_STATUS;
63 gpios = <&pio 11 GPIO_ACTIVE_HIGH>;
67 color = <LED_COLOR_ID_GREEN>;
68 function = LED_FUNCTION_STATUS;
69 gpios = <&pio 12 GPIO_ACTIVE_LOW>;
73 reg_1p8v: regulator-1p8v {
74 compatible = "regulator-fixed";
75 regulator-name = "fixed-1.8V";
76 regulator-min-microvolt = <1800000>;
77 regulator-max-microvolt = <1800000>;
82 reg_3p3v: regulator-3p3v {
83 compatible = "regulator-fixed";
84 regulator-name = "fixed-3.3V";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
100 compatible = "mediatek,eth-mac";
102 phy-mode = "2500base-x";
112 compatible = "mediatek,eth-mac";
114 phy-mode = "2500base-x";
115 phy-handle = <&phy6>;
119 #address-cells = <1>;
126 compatible = "ethernet-phy-ieee802.3-c45";
129 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
130 reset-assert-us = <10000>;
131 reset-deassert-us = <50000>;
132 realtek,aldps-enable;
136 compatible = "mediatek,mt7531";
138 reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>;
139 interrupt-controller;
140 #interrupt-cells = <1>;
141 interrupt-parent = <&pio>;
142 interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
149 hs400-ds-delay = <0x14014>;
150 max-frequency = <200000000>;
156 pinctrl-names = "default", "state_uhs";
157 pinctrl-0 = <&mmc0_pins_default>;
158 pinctrl-1 = <&mmc0_pins_uhs>;
159 vmmc-supply = <®_3p3v>;
160 vqmmc-supply = <®_1p8v>;
164 compatible = "mmc-card";
168 compatible = "block-device";
170 emmc_rootdisk: block-partition-production {
171 partname = "production";
179 mmc0_pins_default: mmc0-pins-default {
185 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
186 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
187 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
189 drive-strength = <4>;
190 mediatek,pull-up-adv = <1>;
194 drive-strength = <6>;
195 mediatek,pull-down-adv = <2>;
199 mediatek,pull-down-adv = <2>;
203 drive-strength = <4>;
204 mediatek,pull-up-adv = <1>;
208 mmc0_pins_uhs: mmc0-uhs-pins {
214 pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
215 "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
216 "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
218 drive-strength = <4>;
219 mediatek,pull-up-adv = <1>;
223 drive-strength = <6>;
224 mediatek,pull-down-adv = <2>;
228 mediatek,pull-down-adv = <2>;
232 drive-strength = <4>;
233 mediatek,pull-up-adv = <1>;
237 wf_2g_5g_pins: wf-2g-5g-pins {
240 groups = "wf_2g", "wf_5g";
243 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
244 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
245 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
246 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
247 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
248 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
249 "WF1_TOP_CLK", "WF1_TOP_DATA";
250 drive-strength = <4>;
257 #address-cells = <1>;
283 phy-mode = "2500base-x";
307 pinctrl-names = "default";
308 pinctrl-0 = <&wf_2g_5g_pins>;