target/linux/mediatek/dts/mt7986b-netgear-wax220.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/leds/common.h>
   7
   8 #include "mt7986b.dtsi"
   9
  10 / {
  11         model = "Netgear WAX220";
  12         compatible = "netgear,wax220", "mediatek,mt7986b";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_power_blue;
  17                 led-failsafe = &led_power_amber;
  18                 led-running = &led_power_green;
  19                 led-upgrade = &led_power_amber;
  20         };
  21
  22         gpio-keys {
  23                 compatible = "gpio-keys";
  24
  25                 reset {
  26                         gpios = <&pio 9 GPIO_ACTIVE_LOW>;
  27                         linux,code = <KEY_RESTART>;
  28                         label = "reset";
  29                 };
  30         };
  31
  32         chosen {
  33                 stdout-path = "serial0:115200n8";
  34         };
  35
  36         leds {
  37                 compatible = "gpio-leds";
  38
  39                 wlan5g_green {
  40                         gpios = <&pio 12 GPIO_ACTIVE_LOW>;
  41                         label = "green:wlan5g";
  42                 };
  43
  44                 led_power_amber: power_amber {
  45                         gpios = <&pio 15 GPIO_ACTIVE_LOW>;
  46                         label = "amber:power";
  47                 };
  48
  49                 wlan2g_green {
  50                         gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
  51                         label = "green:wlan2g";
  52                 };
  53
  54                 led_power_blue: power_blue {
  55                         gpios = <&pio 7 GPIO_ACTIVE_HIGH>;
  56                         label = "blue:power";
  57                 };
  58
  59                 led_power_green: power_green {
  60                         gpios = <&pio 10 GPIO_ACTIVE_LOW>;
  61                         label = "green:power";
  62                 };
  63
  64                 wlan2g_blue {
  65                         gpios = <&pio 1 GPIO_ACTIVE_LOW>;
  66                         label = "blue:wlan2g";
  67                 };
  68
  69                 lan_green {
  70                         gpios = <&pio 22 GPIO_ACTIVE_HIGH>;
  71                         label = "green:lan";
  72                 };
  73
  74                 lan_amber {
  75                         gpios = <&pio 13 GPIO_ACTIVE_LOW>;
  76                         label = "amber:lan";
  77                 };
  78
  79                 wlan5g_blue {
  80                         gpios = <&pio 2 GPIO_ACTIVE_LOW>;
  81                         label = "blue:wlan5g";
  82                 };
  83         };
  84 };
  85
  86 &crypto {
  87         status = "okay";
  88 };
  89
  90 &eth {
  91         status = "okay";
  92
  93         gmac1: mac@1 {
  94                 compatible = "mediatek,eth-mac";
  95                 reg = <1>;
  96                 phy-handle = <&phy6>;
  97                 phy-mode = "2500base-x";
  98         };
  99
 100         mdio: mdio-bus {
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103         };
 104 };
 105
 106 &mdio {
 107         phy6: ethernet-phy@6 {
 108                 reg = <6>;
 109                 reset-assert-us = <100000>;
 110                 reset-deassert-us = <100000>;
 111                 reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>;
 112                 interrupt-controller;
 113                 #interrupt-cells = <1>;
 114                 interrupt-parent = <&pio>;
 115                 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
 116         };
 117 };
 118
 119 &pio {
 120         spi_flash_pins: spi-flash-pins-33-to-38 {
 121                 mux {
 122                         function = "spi";
 123                         groups = "spi0", "spi0_wp_hold";
 124                 };
 125                 conf-pu {
 126                         pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
 127                         drive-strength = <8>;
 128                         mediatek,pull-up-adv = <0>; /* bias-disable */
 129                 };
 130                 conf-pd {
 131                         pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
 132                         drive-strength = <8>;
 133                         mediatek,pull-down-adv = <0>; /* bias-disable */
 134                 };
 135         };
 136
 137         wf_2g_5g_pins: wf_2g_5g-pins {
 138                 mux {
 139                         function = "wifi";
 140                         groups = "wf_2g", "wf_5g";
 141                 };
 142                 conf {
 143                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 144                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 145                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 146                                "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
 147                                "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
 148                                "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
 149                                "WF1_TOP_CLK", "WF1_TOP_DATA";
 150                         drive-strength = <4>;
 151                 };
 152         };
 153
 154         wf_dbdc_pins: wf-dbdc-pins {
 155                 mux {
 156                         function = "wifi";
 157                         groups = "wf_dbdc";
 158                 };
 159                 conf {
 160                         pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
 161                                "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
 162                                "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
 163                                "WF0_TOP_CLK", "WF0_TOP_DATA";
 164                         drive-strength = <4>;
 165                 };
 166         };
 167 };
 168
 169 &spi0 {
 170         pinctrl-names = "default";
 171         pinctrl-0 = <&spi_flash_pins>;
 172         status = "okay";
 173
 174         spi_nand_flash: flash@0 {
 175                 #address-cells = <1>;
 176                 #size-cells = <1>;
 177                 compatible = "spi-nand";
 178                 reg = <0>;
 179
 180                 spi-max-frequency = <20000000>;
 181                 spi-tx-buswidth = <4>;
 182                 spi-rx-buswidth = <4>;
 183
 184                 mediatek,nmbm;
 185                 mediatek,bmt-max-ratio = <1>;
 186                 mediatek,bmt-max-reserved-blocks = <256>;
 187                 mediatek,bmt-remap-range = <0x0 0x580000>;
 188
 189                 partitions: partitions {
 190                         #address-cells = <0x1>;
 191                         #size-cells = <0x1>;
 192                         compatible = "fixed-partitions";
 193
 194                         partition@0 {
 195                                 label = "BL2";
 196                                 read-only;
 197                                 reg = <0x0 0x100000>;
 198                         };
 199
 200                         partition@100000 {
 201                                 label = "u-boot-env";
 202                                 reg = <0x100000 0x80000>;
 203                         };
 204
 205                         factory: partition@180000 {
 206                                 label = "Factory";
 207                                 reg = <0x180000 0x200000>;
 208                         };
 209
 210                         partition@380000 {
 211                                 label = "FIP";
 212                                 reg = <0x380000 0x200000>;
 213                         };
 214
 215                         partition@580000 {
 216                                 label = "ubi";
 217                                 reg = <0x580000 0x5140000>;
 218                         };
 219
 220                         partition@56c0000 {
 221                                 label = "RAE";
 222                                 reg = <0x56c0000 0x400000>;
 223                         };
 224
 225                         partition@5ac0000 {
 226                                 label = "POT";
 227                                 reg = <0x5ac0000 0x100000>;
 228                         };
 229
 230                         partition@5bc0000 {
 231                                 label = "Language";
 232                                 reg = <0x5bc0000 0x400000>;
 233                         };
 234
 235                         partition@5fc0000 {
 236                                 label = "Traffic";
 237                                 reg = <0x5fc0000 0x200000>;
 238                         };
 239
 240                         partition@61c0000 {
 241                                 label = "Cert";
 242                                 reg = <0x61c0000 0x100000>;
 243                         };
 244
 245                         partition@62c0000 {
 246                                 label = "NTGRcryptK";
 247                                 reg = <0x62c0000 0x100000>;
 248                         };
 249
 250                         partition@63c0000 {
 251                                 label = "NTGRcryptD";
 252                                 reg = <0x63c0000 0x500000>;
 253                         };
 254
 255                         partition@68c0000 {
 256                                 label = "LOG";
 257                                 reg = <0x68c0000 0x100000>;
 258                         };
 259
 260                         partition@69c0000 {
 261                                 label = "User_data";
 262                                 reg = <0x69c0000 0x640000>;
 263                         };
 264                 };
 265         };
 266
 267 };
 268
 269 &trng {
 270         status = "okay";
 271 };
 272
 273 &uart0 {
 274         status = "okay";
 275 };
 276
 277 &watchdog {
 278         status = "okay";
 279 };
 280
 281 &wifi {
 282         status = "okay";
 283         pinctrl-names = "default", "dbdc";
 284         pinctrl-0 = <&wf_2g_5g_pins>;
 285         pinctrl-1 = <&wf_dbdc_pins>;
 286
 287         mediatek,mtd-eeprom = <&factory 0x0>;
 288 };