target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64-rootdisk.dts

   1 /*
   2  * Copyright (c) 2018 MediaTek Inc.
   3  * Author: Ryder Lee <ryder.lee@mediatek.com>
   4  *
   5  * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   6  */
   7
   8 /dts-v1/;
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11
  12 #include "mt7622.dtsi"
  13 #include "mt6380.dtsi"
  14
  15 / {
  16         model = "Bananapi BPI-R64";
  17         compatible = "bananapi,bpi-r64-rootdisk", "mediatek,mt7622";
  18
  19         aliases {
  20                 serial0 = &uart0;
  21         };
  22
  23         chosen {
  24                 stdout-path = "serial0:115200n8";
  25                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512 root=/dev/mmcblk0p7 rootfstype=squashfs,f2fs";
  26         };
  27
  28         cpus {
  29                 cpu@0 {
  30                         proc-supply = <&mt6380_vcpu_reg>;
  31                         sram-supply = <&mt6380_vm_reg>;
  32                 };
  33
  34                 cpu@1 {
  35                         proc-supply = <&mt6380_vcpu_reg>;
  36                         sram-supply = <&mt6380_vm_reg>;
  37                 };
  38         };
  39
  40         gpio-keys {
  41                 compatible = "gpio-keys";
  42
  43                 factory {
  44                         label = "factory";
  45                         linux,code = <BTN_0>;
  46                         gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
  47                 };
  48
  49                 wps {
  50                         label = "wps";
  51                         linux,code = <KEY_WPS_BUTTON>;
  52                         gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
  53                 };
  54         };
  55
  56         leds {
  57                 compatible = "gpio-leds";
  58
  59                 green {
  60                         label = "bpi-r64:pio:green";
  61                         gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
  62                 };
  63
  64                 red {
  65                         label = "bpi-r64:pio:red";
  66                         gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
  67                 };
  68         };
  69
  70         memory {
  71                 reg = <0 0x40000000 0 0x40000000>;
  72         };
  73
  74         reg_1p8v: regulator-1p8v {
  75                 compatible = "regulator-fixed";
  76                 regulator-name = "fixed-1.8V";
  77                 regulator-min-microvolt = <1800000>;
  78                 regulator-max-microvolt = <1800000>;
  79                 regulator-always-on;
  80         };
  81
  82         reg_3p3v: regulator-3p3v {
  83                 compatible = "regulator-fixed";
  84                 regulator-name = "fixed-3.3V";
  85                 regulator-min-microvolt = <3300000>;
  86                 regulator-max-microvolt = <3300000>;
  87                 regulator-boot-on;
  88                 regulator-always-on;
  89         };
  90
  91         reg_5v: regulator-5v {
  92                 compatible = "regulator-fixed";
  93                 regulator-name = "fixed-5V";
  94                 regulator-min-microvolt = <5000000>;
  95                 regulator-max-microvolt = <5000000>;
  96                 regulator-boot-on;
  97                 regulator-always-on;
  98         };
  99 };
 100
 101 &bch {
 102         status = "disabled";
 103 };
 104
 105 &btif {
 106         status = "okay";
 107 };
 108
 109 &cir {
 110         pinctrl-names = "default";
 111         pinctrl-0 = <&irrx_pins>;
 112         status = "okay";
 113 };
 114
 115 &eth {
 116         status = "okay";
 117         gmac0: mac@0 {
 118                 compatible = "mediatek,eth-mac";
 119                 reg = <0>;
 120                 phy-mode = "2500base-x";
 121
 122                 fixed-link {
 123                         speed = <2500>;
 124                         full-duplex;
 125                         pause;
 126                 };
 127         };
 128
 129         gmac1: mac@1 {
 130                 compatible = "mediatek,eth-mac";
 131                 reg = <1>;
 132                 phy-mode = "rgmii";
 133
 134                 fixed-link {
 135                         speed = <1000>;
 136                         full-duplex;
 137                         pause;
 138                 };
 139         };
 140
 141         mdio: mdio-bus {
 142                 #address-cells = <1>;
 143                 #size-cells = <0>;
 144
 145                 switch@1f {
 146                         compatible = "mediatek,mt7531";
 147                         reg = <0x1f>;
 148                         reset-gpios = <&pio 54 0>;
 149
 150                         ports {
 151                                 #address-cells = <1>;
 152                                 #size-cells = <0>;
 153
 154                                 wan: port@0 {
 155                                         reg = <0>;
 156                                         label = "wan";
 157                                 };
 158
 159                                 port@1 {
 160                                         reg = <1>;
 161                                         label = "lan0";
 162                                 };
 163
 164                                 port@2 {
 165                                         reg = <2>;
 166                                         label = "lan1";
 167                                 };
 168
 169                                 port@3 {
 170                                         reg = <3>;
 171                                         label = "lan2";
 172                                 };
 173
 174                                 port@4 {
 175                                         reg = <4>;
 176                                         label = "lan3";
 177                                 };
 178
 179                                 port@6 {
 180                                         reg = <6>;
 181                                         label = "cpu";
 182                                         ethernet = <&gmac0>;
 183                                         phy-mode = "2500base-x";
 184
 185                                         fixed-link {
 186                                                 speed = <2500>;
 187                                                 full-duplex;
 188                                                 pause;
 189                                         };
 190                                 };
 191                         };
 192                 };
 193
 194         };
 195 };
 196
 197 &i2c1 {
 198         pinctrl-names = "default";
 199         pinctrl-0 = <&i2c1_pins>;
 200         status = "okay";
 201 };
 202
 203 &i2c2 {
 204         pinctrl-names = "default";
 205         pinctrl-0 = <&i2c2_pins>;
 206         status = "okay";
 207 };
 208
 209 &mmc0 {
 210         pinctrl-names = "default", "state_uhs";
 211         pinctrl-0 = <&emmc_pins_default>;
 212         pinctrl-1 = <&emmc_pins_uhs>;
 213         status = "okay";
 214         bus-width = <8>;
 215         max-frequency = <50000000>;
 216         cap-mmc-highspeed;
 217         mmc-hs200-1_8v;
 218         vmmc-supply = <&reg_3p3v>;
 219         vqmmc-supply = <&reg_1p8v>;
 220         assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
 221         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 222         non-removable;
 223 };
 224
 225 &mmc1 {
 226         pinctrl-names = "default", "state_uhs";
 227         pinctrl-0 = <&sd0_pins_default>;
 228         pinctrl-1 = <&sd0_pins_uhs>;
 229         status = "okay";
 230         bus-width = <4>;
 231         max-frequency = <50000000>;
 232         cap-sd-highspeed;
 233         r_smpl = <1>;
 234         cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
 235         vmmc-supply = <&reg_3p3v>;
 236         vqmmc-supply = <&reg_3p3v>;
 237         assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
 238         assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
 239 };
 240
 241 &nandc {
 242         pinctrl-names = "default";
 243         pinctrl-0 = <&parallel_nand_pins>;
 244         status = "disabled";
 245 };
 246
 247 &nor_flash {
 248         pinctrl-names = "default";
 249         pinctrl-0 = <&spi_nor_pins>;
 250         status = "disabled";
 251
 252         flash@0 {
 253                 compatible = "jedec,spi-nor";
 254                 reg = <0>;
 255         };
 256 };
 257
 258 &pcie0 {
 259         pinctrl-names = "default";
 260         pinctrl-0 = <&pcie0_pins>;
 261         status = "okay";
 262 };
 263
 264 &pcie1 {
 265         pinctrl-names = "default";
 266         pinctrl-0 = <&pcie1_pins>;
 267         status = "okay";
 268 };
 269
 270 &pio {
 271         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 272          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 273          */
 274         asm_sel {
 275                 gpio-hog;
 276                 gpios = <90 GPIO_ACTIVE_HIGH>;
 277                 output-high;
 278         };
 279
 280         /* eMMC is shared pin with parallel NAND */
 281         emmc_pins_default: emmc-pins-default {
 282                 mux {
 283                         function = "emmc", "emmc_rst";
 284                         groups = "emmc";
 285                 };
 286
 287                 /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
 288                  * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
 289                  * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
 290                  */
 291                 conf-cmd-dat {
 292                         pins = "NDL0", "NDL1", "NDL2",
 293                                "NDL3", "NDL4", "NDL5",
 294                                "NDL6", "NDL7", "NRB";
 295                         input-enable;
 296                         bias-pull-up;
 297                 };
 298
 299                 conf-clk {
 300                         pins = "NCLE";
 301                         bias-pull-down;
 302                 };
 303         };
 304
 305         emmc_pins_uhs: emmc-pins-uhs {
 306                 mux {
 307                         function = "emmc";
 308                         groups = "emmc";
 309                 };
 310
 311                 conf-cmd-dat {
 312                         pins = "NDL0", "NDL1", "NDL2",
 313                                "NDL3", "NDL4", "NDL5",
 314                                "NDL6", "NDL7", "NRB";
 315                         input-enable;
 316                         drive-strength = <4>;
 317                         bias-pull-up;
 318                 };
 319
 320                 conf-clk {
 321                         pins = "NCLE";
 322                         drive-strength = <4>;
 323                         bias-pull-down;
 324                 };
 325         };
 326
 327         eth_pins: eth-pins {
 328                 mux {
 329                         function = "eth";
 330                         groups = "mdc_mdio", "rgmii_via_gmac2";
 331                 };
 332         };
 333
 334         i2c1_pins: i2c1-pins {
 335                 mux {
 336                         function = "i2c";
 337                         groups =  "i2c1_0";
 338                 };
 339         };
 340
 341         i2c2_pins: i2c2-pins {
 342                 mux {
 343                         function = "i2c";
 344                         groups =  "i2c2_0";
 345                 };
 346         };
 347
 348         i2s1_pins: i2s1-pins {
 349                 mux {
 350                         function = "i2s";
 351                         groups =  "i2s_out_mclk_bclk_ws",
 352                                   "i2s1_in_data",
 353                                   "i2s1_out_data";
 354                 };
 355
 356                 conf {
 357                         pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
 358                                "I2S_WS", "I2S_MCLK";
 359                         drive-strength = <12>;
 360                         bias-pull-down;
 361                 };
 362         };
 363
 364         irrx_pins: irrx-pins {
 365                 mux {
 366                         function = "ir";
 367                         groups =  "ir_1_rx";
 368                 };
 369         };
 370
 371         irtx_pins: irtx-pins {
 372                 mux {
 373                         function = "ir";
 374                         groups =  "ir_1_tx";
 375                 };
 376         };
 377
 378         /* Parallel nand is shared pin with eMMC */
 379         parallel_nand_pins: parallel-nand-pins {
 380                 mux {
 381                         function = "flash";
 382                         groups = "par_nand";
 383                 };
 384         };
 385
 386         pcie0_pins: pcie0-pins {
 387                 mux {
 388                         function = "pcie";
 389                         groups = "pcie0_pad_perst",
 390                                  "pcie0_1_waken",
 391                                  "pcie0_1_clkreq";
 392                 };
 393         };
 394
 395         pcie1_pins: pcie1-pins {
 396                 mux {
 397                         function = "pcie";
 398                         groups = "pcie1_pad_perst",
 399                                  "pcie1_0_waken",
 400                                  "pcie1_0_clkreq";
 401                 };
 402         };
 403
 404         pmic_bus_pins: pmic-bus-pins {
 405                 mux {
 406                         function = "pmic";
 407                         groups = "pmic_bus";
 408                 };
 409         };
 410
 411         pwm7_pins: pwm1-2-pins {
 412                 mux {
 413                         function = "pwm";
 414                         groups = "pwm_ch7_2";
 415                 };
 416         };
 417
 418         wled_pins: wled-pins {
 419                 mux {
 420                         function = "led";
 421                         groups = "wled";
 422                 };
 423         };
 424
 425         sd0_pins_default: sd0-pins-default {
 426                 mux {
 427                         function = "sd";
 428                         groups = "sd_0";
 429                 };
 430
 431                 /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
 432                  *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
 433                  *  DAT2, DAT3, CMD, CLK for SD respectively.
 434                  */
 435                 conf-cmd-data {
 436                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 437                                "I2S2_IN","I2S4_OUT";
 438                         input-enable;
 439                         drive-strength = <8>;
 440                         bias-pull-up;
 441                 };
 442                 conf-clk {
 443                         pins = "I2S3_OUT";
 444                         drive-strength = <12>;
 445                         bias-pull-down;
 446                 };
 447                 conf-cd {
 448                         pins = "TXD3";
 449                         bias-pull-up;
 450                 };
 451         };
 452
 453         sd0_pins_uhs: sd0-pins-uhs {
 454                 mux {
 455                         function = "sd";
 456                         groups = "sd_0";
 457                 };
 458
 459                 conf-cmd-data {
 460                         pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
 461                                "I2S2_IN","I2S4_OUT";
 462                         input-enable;
 463                         bias-pull-up;
 464                 };
 465
 466                 conf-clk {
 467                         pins = "I2S3_OUT";
 468                         bias-pull-down;
 469                 };
 470         };
 471
 472         /* Serial NAND is shared pin with SPI-NOR */
 473         serial_nand_pins: serial-nand-pins {
 474                 mux {
 475                         function = "flash";
 476                         groups = "snfi";
 477                 };
 478         };
 479
 480         spic0_pins: spic0-pins {
 481                 mux {
 482                         function = "spi";
 483                         groups = "spic0_0";
 484                 };
 485         };
 486
 487         spic1_pins: spic1-pins {
 488                 mux {
 489                         function = "spi";
 490                         groups = "spic1_0";
 491                 };
 492         };
 493
 494         /* SPI-NOR is shared pin with serial NAND */
 495         spi_nor_pins: spi-nor-pins {
 496                 mux {
 497                         function = "flash";
 498                         groups = "spi_nor";
 499                 };
 500         };
 501
 502         /* serial NAND is shared pin with SPI-NOR */
 503         serial_nand_pins: serial-nand-pins {
 504                 mux {
 505                         function = "flash";
 506                         groups = "snfi";
 507                 };
 508         };
 509
 510         uart0_pins: uart0-pins {
 511                 mux {
 512                         function = "uart";
 513                         groups = "uart0_0_tx_rx" ;
 514                 };
 515         };
 516
 517         uart2_pins: uart2-pins {
 518                 mux {
 519                         function = "uart";
 520                         groups = "uart2_1_tx_rx" ;
 521                 };
 522         };
 523
 524         watchdog_pins: watchdog-pins {
 525                 mux {
 526                         function = "watchdog";
 527                         groups = "watchdog";
 528                 };
 529         };
 530 };
 531
 532 &pwm {
 533         pinctrl-names = "default";
 534         pinctrl-0 = <&pwm7_pins>;
 535         status = "okay";
 536 };
 537
 538 &pwrap {
 539         pinctrl-names = "default";
 540         pinctrl-0 = <&pmic_bus_pins>;
 541
 542         status = "okay";
 543 };
 544
 545 &sata {
 546         status = "disable";
 547 };
 548
 549 &sata_phy {
 550         status = "disable";
 551 };
 552
 553 &spi0 {
 554         pinctrl-names = "default";
 555         pinctrl-0 = <&spic0_pins>;
 556         status = "okay";
 557 };
 558
 559 &spi1 {
 560         pinctrl-names = "default";
 561         pinctrl-0 = <&spic1_pins>;
 562         status = "okay";
 563 };
 564
 565 &ssusb {
 566         vusb33-supply = <&reg_3p3v>;
 567         vbus-supply = <&reg_5v>;
 568         status = "okay";
 569 };
 570
 571 &u3phy {
 572         status = "okay";
 573 };
 574
 575 &uart0 {
 576         pinctrl-names = "default";
 577         pinctrl-0 = <&uart0_pins>;
 578         status = "okay";
 579 };
 580
 581 &uart2 {
 582         pinctrl-names = "default";
 583         pinctrl-0 = <&uart2_pins>;
 584         status = "okay";
 585 };
 586
 587 &watchdog {
 588         pinctrl-names = "default";
 589         pinctrl-0 = <&watchdog_pins>;
 590         status = "okay";
 591 };