target/linux/mediatek/patches/0073-clk.patch

   1 From a4df453fbfa6199ad33435cee6ce2dfcc65321b0 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Fri, 3 Jul 2015 05:45:58 +0200
   4 Subject: [PATCH 73/76] clk
   5
   6 ---
   7  include/dt-bindings/clock/mt7623-clk.h |  158 +++++++++++++++-----------------
   8  1 file changed, 73 insertions(+), 85 deletions(-)
   9
  10 diff --git a/include/dt-bindings/clock/mt7623-clk.h b/include/dt-bindings/clock/mt7623-clk.h
  11 index cb1e8a9..410ef31 100644
  12 --- a/include/dt-bindings/clock/mt7623-clk.h
  13 +++ b/include/dt-bindings/clock/mt7623-clk.h
  14 @@ -17,96 +17,76 @@
  15
  16  /* TOPCKGEN */
  17
  18 -#define CLK_TOP_AUDPLL_24              1
  19 -#define CLK_TOP_AUDPLL_D16             2
  20 -#define CLK_TOP_AUDPLL_D4              3
  21 -#define CLK_TOP_AUDPLL_D8              4
  22 -#define CLK_TOP_CLKPH_MCK              5
  23 -#define CLK_TOP_CPUM_TCK_IN            6
  24 -#define CLK_TOP_DSI0_LNTC_DSICLK       7
  25 -#define CLK_TOP_HDMITX_CLKDIG_CTS      8
  26 -#define CLK_TOP_LVDS_ETH               9
  27 -#define CLK_TOP_LVDSPLL_D2             10
  28 -#define CLK_TOP_LVDSPLL_D4             11
  29 -#define CLK_TOP_LVDSPLL_D8             12
  30 -#define CLK_TOP_MAINPLL_230P3M         13
  31 -#define CLK_TOP_MAINPLL_322P4M         14
  32 -#define CLK_TOP_MAINPLL_537P3M         15
  33 -#define CLK_TOP_MAINPLL_806M           16
  34 -#define CLK_TOP_MEMPLL_MCK_D4          17
  35 -#define CLK_TOP_MMPLL_D2               18
  36 -#define CLK_TOP_MSDCPLL_D2             19
  37 -#define CLK_TOP_SYSPLL1_D16            20
  38 -#define CLK_TOP_SYSPLL1_D2             21
  39 -#define CLK_TOP_SYSPLL1_D4             22
  40 -#define CLK_TOP_SYSPLL1_D8             23
  41 -#define CLK_TOP_SYSPLL2_D2             24
  42 -#define CLK_TOP_SYSPLL2_D4             25
  43 -#define CLK_TOP_SYSPLL2_D8             26
  44 -#define CLK_TOP_SYSPLL3_D2             27
  45 -#define CLK_TOP_SYSPLL3_D4             28
  46 -#define CLK_TOP_SYSPLL4_D2             29
  47 -#define CLK_TOP_SYSPLL4_D4             30
  48 -#define CLK_TOP_SYSPLL_D3              31
  49 -#define CLK_TOP_SYSPLL_D5              32
  50 -#define CLK_TOP_SYSPLL_D7              33
  51 -#define CLK_TOP_TVDPLL_d2              34
  52 -#define CLK_TOP_TVDPLL_D4              35
  53 -#define CLK_TOP_UNIVPLL_178P3M         36
  54 -#define CLK_TOP_UNIVPLL1_D10           37
  55 -#define CLK_TOP_UNIVPLL1_D2            38
  56 -#define CLK_TOP_UNIVPLL1_D4            39
  57 -#define CLK_TOP_UNIVPLL1_D6            40
  58 -#define CLK_TOP_UNIVPLL1_D8            41
  59 -#define CLK_TOP_UNIVPLL_249P6M         42
  60 -#define CLK_TOP_UNIVPLL2_D2            43
  61 -#define CLK_TOP_UNIVPLL2_D4            44
  62 -#define CLK_TOP_UNIVPLL2_D6            45
  63 -#define CLK_TOP_UNIVPLL2_D8            46
  64 -#define CLK_TOP_UNIVPLL_416M           47
  65 -#define CLK_TOP_UNIVPLL_48M            48
  66 -#define CLK_TOP_UNIVPLL_624M           49
  67 -#define CLK_TOP_UNIVPLL_D26            50
  68 -#define CLK_TOP_UNIVPLL_D5             51
  69 -#define CLK_TOP_APLL_SEL               52
  70 +#define CLK_TOP_MAINPLL_650M           1
  71 +#define CLK_TOP_MAINPLL_433P3M         2
  72 +#define CLK_TOP_MAINPLL_260M           3
  73 +#define CLK_TOP_MAINPLL_185P6M         4
  74 +#define CLK_TOP_UNIVPLL_624M           5
  75 +#define CLK_TOP_UNIVPLL_416M           6
  76 +#define CLK_TOP_UNIVPLL_249P6M         7
  77 +#define CLK_TOP_UNIVPLL_178P3M         8
  78 +#define CLK_TOP_UNIVPLL_48M            9
  79 +#define CLK_TOP_AUDPLL_D4              10
  80 +#define CLK_TOP_AUDPLL_D8              11
  81 +#define CLK_TOP_AUDPLL_D16             12
  82 +#define CLK_TOP_AUDPLL_24              13
  83 +#define CLK_TOP_MSDCPLL_D2             14
  84 +#define CLK_TOP_SYSPLL1_D2             15
  85 +#define CLK_TOP_SYSPLL1_D4             16
  86 +#define CLK_TOP_SYSPLL1_D8             17
  87 +#define CLK_TOP_SYSPLL1_D16            18
  88 +#define CLK_TOP_SYSPLL2_D2             19
  89 +#define CLK_TOP_SYSPLL2_D4             20
  90 +#define CLK_TOP_SYSPLL2_D8             21
  91 +#define CLK_TOP_SYSPLL3_D2             22
  92 +#define CLK_TOP_SYSPLL3_D4             23
  93 +#define CLK_TOP_SYSPLL4_D2             24
  94 +#define CLK_TOP_SYSPLL4_D4             25
  95 +#define CLK_TOP_SYSPLL_D3              26
  96 +#define CLK_TOP_SYSPLL_D5              27
  97 +#define CLK_TOP_SYSPLL_D7              28
  98 +#define CLK_TOP_UNIVPLL1_D2            29
  99 +#define CLK_TOP_UNIVPLL1_D4            30
 100 +#define CLK_TOP_UNIVPLL1_D6            31
 101 +#define CLK_TOP_UNIVPLL1_D8            32
 102 +#define CLK_TOP_UNIVPLL1_D10           33
 103 +#define CLK_TOP_UNIVPLL2_D2            34
 104 +#define CLK_TOP_UNIVPLL2_D4            35
 105 +#define CLK_TOP_UNIVPLL2_D6            36
 106 +#define CLK_TOP_UNIVPLL2_D8            37
 107 +#define CLK_TOP_UNIVPLL_D5             38
 108 +#define CLK_TOP_UNIVPLL_D26            39
 109 +#define CLK_TOP_AXI_SEL                        40
 110 +#define CLK_TOP_MEM_SEL                        41
 111 +#define CLK_TOP_DDR_SEL                        42
 112 +#define CLK_TOP_MM_SEL                 43
 113 +#define CLK_TOP_PWM_SEL                        44
 114 +#define CLK_TOP_MFG_SEL                        45
 115 +#define CLK_TOP_UART_SEL               46
 116 +#define CLK_TOP_SPI_SEL                        47
 117 +#define CLK_TOP_USB20_SEL              48
 118 +#define CLK_TOP_MSDC30_0_SEL           49
 119 +#define CLK_TOP_MSDC30_1_SEL           50
 120 +#define CLK_TOP_MSDC30_2_SEL           51
 121 +#define CLK_TOP_AUDIO_SEL              52
 122  #define CLK_TOP_AUDIO_INTBUS_SEL       53
 123 -#define CLK_TOP_AUDIO_SEL              54
 124 -#define CLK_TOP_AXI_SEL                        55
 125 -#define CLK_TOP_CAM_SEL                        56
 126 -#define CLK_TOP_DDR_SEL                        57
 127 -#define CLK_TOP_DPI0_SEL               58
 128 -#define CLK_TOP_DPI1_SEL               59
 129 -#define CLK_TOP_DPILVDS_SEL            60
 130 -#define CLK_TOP_ETH_SEL                        61
 131 -#define CLK_TOP_MEM_SEL                        62
 132 -#define CLK_TOP_MFG_SEL                        63
 133 -#define CLK_TOP_MM_SEL                 64
 134 -#define CLK_TOP_MSDC30_0_SEL           65
 135 -#define CLK_TOP_MSDC30_1_SEL           66
 136 -#define CLK_TOP_MSDC30_2_SEL           67
 137 -#define CLK_TOP_NFI2X_SEL              68
 138 -#define CLK_TOP_PMICSPI_SEL            69
 139 -#define CLK_TOP_PWM_SEL                        70
 140 -#define CLK_TOP_RTC_SEL                        71
 141 -#define CLK_TOP_SCP_SEL                        72
 142 -#define CLK_TOP_SPI_SEL                        73
 143 -#define CLK_TOP_TVE_SEL                        74
 144 -#define CLK_TOP_UART_SEL               75
 145 -#define CLK_TOP_USB20_SEL              76
 146 -#define CLK_TOP_VDEC_SEL               77
 147 -#define CLK_TOP_NR_CLK                 78
 148 +#define CLK_TOP_PMICSPI_SEL            54
 149 +#define CLK_TOP_SCP_SEL                        55
 150 +#define CLK_TOP_APLL_SEL               56
 151 +#define CLK_TOP_RTC_SEL                        57
 152 +#define CLK_TOP_NFI2X_SEL              58
 153 +#define CLK_TOP_ETH_SEL                        59
 154 +#define CLK_TOP_NR_CLK                 60
 155
 156  /* APMIXED_SYS */
 157
 158  #define CLK_APMIXED_ARMPLL             1
 159  #define CLK_APMIXED_MAINPLL            2
 160 -#define CLK_APMIXED_MSDCPLL            3
 161 -#define CLK_APMIXED_UNIVPLL            4
 162 -#define CLK_APMIXED_MMPLL              5
 163 -#define CLK_APMIXED_VENCPLL            6
 164 -#define CLK_APMIXED_TVDPLL             7
 165 -#define CLK_APMIXED_LVDSPLL            8
 166 -#define CLK_APMIXED_AUDPLL             9
 167 +#define CLK_APMIXED_UNIVPLL            3
 168 +#define CLK_APMIXED_MSDCPLL            4
 169 +#define CLK_APMIXED_AUDPLL             5
 170 +#define CLK_APMIXED_TRGPLL             6
 171 +#define CLK_APMIXED_ETHPLL             7
 172
 173  /* INFRA_SYS */
 174
 175 @@ -124,7 +104,8 @@
 176  #define CLK_INFRA_IRRX                 19
 177  #define CLK_INFRA_PMICSPI              22
 178  #define CLK_INFRA_PMIC_WRAP            23
 179 -#define CLK_INFRA_NR_CLK               24
 180 +#define CLK_INFRA_CA7SEL               24
 181 +#define CLK_INFRA_NR_CLK               25
 182
 183  /* PERI_SYS */
 184
 185 @@ -169,5 +150,12 @@
 186  #define CLK_PERI_UART3_SEL             38
 187  #define CLK_PERI_NR_CLK                        39
 188
 189 +#define CLK_HIFSYS_USB0_PHY            1
 190 +#define CLK_HIFSYS_USB1_PHY            2
 191 +#define CLK_HIFSYS_PCIE0               3
 192 +#define CLK_HIFSYS_PCIE1               4
 193 +#define CLK_HIFSYS_PCIE2               5
 194 +#define CLK_HIFSYS_NR_CLK              6
 195 +
 196  #endif /* _DT_BINDINGS_CLK_MT7623_H */
 197
 198 --
 199 1.7.10.4
 200