target/linux/mediatek/patches-4.14/0227-arm-dts-Add-Unielec-U7623-DTS.patch

   1 From 0c88c72bf130c9276958dc6f595ea473ea357a75 Mon Sep 17 00:00:00 2001
   2 From: Kristian Evensen <kristian.evensen@gmail.com>
   3 Date: Sun, 17 Jun 2018 14:41:47 +0200
   4 Subject: [PATCH] arm: dts: Add Unielec U7623 DTS
   5
   6 ---
   7  arch/arm/boot/dts/Makefile                         |   1 +
   8  .../dts/mt7623a-unielec-u7623-02-emmc-512M.dts     |  17 +
   9  .../boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi    | 374 +++++++++++++++++++++
  10  3 files changed, 392 insertions(+)
  11  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  12  create mode 100644 arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  13
  14 --- a/arch/arm/boot/dts/Makefile
  15 +++ b/arch/arm/boot/dts/Makefile
  16 @@ -1062,6 +1062,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
  17         mt6589-aquaris5.dtb \
  18         mt6592-evb.dtb \
  19         mt7623a-rfb-emmc.dtb \
  20 +       mt7623a-unielec-u7623-02-emmc-512M.dtb \
  21         mt7623n-rfb-nand.dtb \
  22         mt7623n-bananapi-bpi-r2.dtb \
  23         mt8127-moose.dtb \
  24 --- /dev/null
  25 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc-512M.dts
  26 @@ -0,0 +1,17 @@
  27 +/*
  28 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  29 + *
  30 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  31 + */
  32 +
  33 +/dts-v1/;
  34 +#include "mt7623a-unielec-u7623-02-emmc.dtsi"
  35 +
  36 +/ {
  37 +       model = "UniElec U7623-02 eMMC (512M RAM)";
  38 +       compatible = "unielec,u7623-02-emmc-512m", "unielec,u7623-02-emmc", "mediatek,mt7623";
  39 +
  40 +       memory {
  41 +               reg = <0 0x80000000 0 0x20000000>;
  42 +       };
  43 +};
  44 --- /dev/null
  45 +++ b/arch/arm/boot/dts/mt7623a-unielec-u7623-02-emmc.dtsi
  46 @@ -0,0 +1,374 @@
  47 +/*
  48 + * Copyright 2018 Kristian Evensen <kristian.evensen@gmail.com>
  49 + *
  50 + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  51 + */
  52 +
  53 +#include <dt-bindings/input/input.h>
  54 +#include "mt7623.dtsi"
  55 +#include "mt6323.dtsi"
  56 +
  57 +/ {
  58 +       compatible = "unielec,u7623-02-emmc", "mediatek,mt7623";
  59 +
  60 +       aliases {
  61 +               serial2 = &uart2;
  62 +       };
  63 +
  64 +       chosen {
  65 +               bootargs = "root=/dev/mmcblk0p2 rootfstype=squashfs,f2fs";
  66 +               stdout-path = "serial2:115200n8";
  67 +       };
  68 +
  69 +       memory {
  70 +               reg = <0 0x80000000 0 0x20000000>;
  71 +       };
  72 +
  73 +       cpus {
  74 +               cpu@0 {
  75 +                       proc-supply = <&mt6323_vproc_reg>;
  76 +               };
  77 +
  78 +               cpu@1 {
  79 +                       proc-supply = <&mt6323_vproc_reg>;
  80 +               };
  81 +
  82 +               cpu@2 {
  83 +                       proc-supply = <&mt6323_vproc_reg>;
  84 +               };
  85 +
  86 +               cpu@3 {
  87 +                       proc-supply = <&mt6323_vproc_reg>;
  88 +               };
  89 +       };
  90 +
  91 +       reg_1p8v: regulator-1p8v {
  92 +               compatible = "regulator-fixed";
  93 +               regulator-name = "fixed-1.8V";
  94 +               regulator-min-microvolt = <1800000>;
  95 +               regulator-max-microvolt = <1800000>;
  96 +               regulator-boot-on;
  97 +               regulator-always-on;
  98 +       };
  99 +
 100 +       reg_3p3v: regulator-3p3v {
 101 +               compatible = "regulator-fixed";
 102 +               regulator-name = "fixed-3.3V";
 103 +               regulator-min-microvolt = <3300000>;
 104 +               regulator-max-microvolt = <3300000>;
 105 +               regulator-boot-on;
 106 +               regulator-always-on;
 107 +       };
 108 +
 109 +       reg_5v: regulator-5v {
 110 +               compatible = "regulator-fixed";
 111 +               regulator-name = "fixed-5V";
 112 +               regulator-min-microvolt = <5000000>;
 113 +               regulator-max-microvolt = <5000000>;
 114 +               regulator-boot-on;
 115 +               regulator-always-on;
 116 +       };
 117 +
 118 +       gpio-keys {
 119 +               compatible = "gpio-keys";
 120 +               pinctrl-names = "default";
 121 +               pinctrl-0 = <&key_pins_a>;
 122 +
 123 +               factory {
 124 +                       label = "factory";
 125 +                       linux,code = <KEY_RESTART>;
 126 +                       gpios = <&pio 256 GPIO_ACTIVE_LOW>;
 127 +               };
 128 +       };
 129 +
 130 +       leds {
 131 +               compatible = "gpio-leds";
 132 +               pinctrl-names = "default";
 133 +               pinctrl-0 = <&led_pins_unielec>;
 134 +
 135 +               led3 {
 136 +                       label = "u7623-01:green:led3";
 137 +                       gpios = <&pio 14 GPIO_ACTIVE_LOW>;
 138 +                       default-state = "off";
 139 +               };
 140 +
 141 +               led4 {
 142 +                       label = "u7623-01:green:led4";
 143 +                       gpios = <&pio 15 GPIO_ACTIVE_LOW>;
 144 +                       default-state = "off";
 145 +               };
 146 +       };
 147 +
 148 +       memory@80000000 {
 149 +               reg = <0 0x80000000 0 0x40000000>;
 150 +       };
 151 +
 152 +       mt7530: switch@0 {
 153 +               compatible = "mediatek,mt7530";
 154 +               #address-cells = <1>;
 155 +               #size-cells = <0>;
 156 +       };
 157 +};
 158 +
 159 +&crypto {
 160 +       status = "okay";
 161 +};
 162 +
 163 +&eth {
 164 +       status = "okay";
 165 +
 166 +       gmac0: mac@0 {
 167 +               compatible = "mediatek,eth-mac";
 168 +               reg = <0>;
 169 +               phy-mode = "trgmii";
 170 +
 171 +               fixed-link {
 172 +                       speed = <1000>;
 173 +                       full-duplex;
 174 +                       pause;
 175 +               };
 176 +       };
 177 +
 178 +       mdio: mdio-bus {
 179 +               #address-cells = <1>;
 180 +               #size-cells = <0>;
 181 +               phy5: ethernet-phy@5 {
 182 +                       reg = <5>;
 183 +                       phy-mode = "rgmii-rxid";
 184 +               };
 185 +       };
 186 +};
 187 +
 188 +&mt7530 {
 189 +       compatible = "mediatek,mt7530";
 190 +       #address-cells = <1>;
 191 +       #size-cells = <0>;
 192 +       reg = <0>;
 193 +       pinctrl-names = "default";
 194 +       mediatek,mcm;
 195 +       resets = <&ethsys 2>;
 196 +       reset-names = "mcm";
 197 +       core-supply = <&mt6323_vpa_reg>;
 198 +       io-supply = <&mt6323_vemc3v3_reg>;
 199 +
 200 +       dsa,mii-bus = <&mdio>;
 201 +
 202 +       ports {
 203 +               #address-cells = <1>;
 204 +               #size-cells = <0>;
 205 +               reg = <0>;
 206 +
 207 +               port@0 {
 208 +                       reg = <0>;
 209 +                       label = "lan0";
 210 +                       cpu = <&cpu_port0>;
 211 +               };
 212 +
 213 +               port@1 {
 214 +                       reg = <1>;
 215 +                       label = "lan1";
 216 +                       cpu = <&cpu_port0>;
 217 +               };
 218 +
 219 +               port@2 {
 220 +                       reg = <2>;
 221 +                       label = "lan2";
 222 +                       cpu = <&cpu_port0>;
 223 +               };
 224 +
 225 +               port@3 {
 226 +                       reg = <3>;
 227 +                       label = "lan3";
 228 +                       cpu = <&cpu_port0>;
 229 +               };
 230 +
 231 +               port@4 {
 232 +                       reg = <4>;
 233 +                       label = "wan";
 234 +                       cpu = <&cpu_port0>;
 235 +               };
 236 +
 237 +               cpu_port0: port@6 {
 238 +                       reg = <6>;
 239 +                       label = "cpu";
 240 +                       ethernet = <&gmac0>;
 241 +                       phy-mode = "trgmii";
 242 +
 243 +                       fixed-link {
 244 +                               speed = <1000>;
 245 +                               full-duplex;
 246 +                       };
 247 +               };
 248 +       };
 249 +};
 250 +
 251 +&mmc0 {
 252 +       pinctrl-names = "default", "state_uhs";
 253 +       pinctrl-0 = <&mmc0_pins_default>;
 254 +       pinctrl-1 = <&mmc0_pins_uhs>;
 255 +       status = "okay";
 256 +       bus-width = <8>;
 257 +       max-frequency = <50000000>;
 258 +       cap-mmc-highspeed;
 259 +       vmmc-supply = <&reg_3p3v>;
 260 +       vqmmc-supply = <&reg_1p8v>;
 261 +       non-removable;
 262 +};
 263 +
 264 +&pio {
 265 +       key_pins_a: keys-alt {
 266 +               pins-keys {
 267 +                       pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
 268 +                                <MT7623_PIN_257_GPIO257_FUNC_GPIO257>;
 269 +                       input-enable;
 270 +               };
 271 +       };
 272 +
 273 +       led_pins_unielec: leds-unielec {
 274 +               pins-leds {
 275 +                       pinmux = <MT7623_PIN_14_GPIO14_FUNC_GPIO14>,
 276 +                                <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
 277 +               };
 278 +       };
 279 +
 280 +       mmc0_pins_default: mmc0default {
 281 +               pins_cmd_dat {
 282 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 283 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 284 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 285 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 286 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 287 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 288 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 289 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 290 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 291 +                       input-enable;
 292 +                       bias-pull-up;
 293 +               };
 294 +
 295 +               pins_clk {
 296 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 297 +                       bias-pull-down;
 298 +               };
 299 +
 300 +               pins_rst {
 301 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 302 +                       bias-pull-up;
 303 +               };
 304 +       };
 305 +
 306 +       mmc0_pins_uhs: mmc0 {
 307 +               pins_cmd_dat {
 308 +                       pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
 309 +                                <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
 310 +                                <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
 311 +                                <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
 312 +                                <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
 313 +                                <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
 314 +                                <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
 315 +                                <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
 316 +                                <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
 317 +                       input-enable;
 318 +                       drive-strength = <MTK_DRIVE_2mA>;
 319 +                       bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 320 +               };
 321 +
 322 +               pins_clk {
 323 +                       pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
 324 +                       drive-strength = <MTK_DRIVE_2mA>;
 325 +                       bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
 326 +               };
 327 +
 328 +               pins_rst {
 329 +                       pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
 330 +                       bias-pull-up;
 331 +               };
 332 +       };
 333 +
 334 +       pwm_pins_a: pwm@0 {
 335 +               pins_pwm {
 336 +                       pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
 337 +                                <MT7623_PIN_204_PWM1_FUNC_PWM1>,
 338 +                                <MT7623_PIN_205_PWM2_FUNC_PWM2>,
 339 +                                <MT7623_PIN_206_PWM3_FUNC_PWM3>,
 340 +                                <MT7623_PIN_207_PWM4_FUNC_PWM4>;
 341 +               };
 342 +       };
 343 +
 344 +       uart2_pins_b: uart@2 {
 345 +               pins_dat {
 346 +                       pinmux = <MT7623_PIN_200_URXD2_FUNC_URXD2>,
 347 +                                <MT7623_PIN_201_UTXD2_FUNC_UTXD2>;
 348 +               };
 349 +       };
 350 +
 351 +       pcie_default: pcie_pin_default {
 352 +               pins_cmd_dat {
 353 +                       pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
 354 +                                <MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
 355 +                       bias-disable;
 356 +               };
 357 +       };
 358 +};
 359 +
 360 +&pwm {
 361 +       pinctrl-names = "default";
 362 +       pinctrl-0 = <&pwm_pins_a>;
 363 +       status = "okay";
 364 +};
 365 +
 366 +&pwrap {
 367 +       mt6323 {
 368 +               mt6323led: led {
 369 +                       compatible = "mediatek,mt6323-led";
 370 +                       #address-cells = <1>;
 371 +                       #size-cells = <0>;
 372 +
 373 +                       led@0 {
 374 +                               reg = <0>;
 375 +                               label = "led0";
 376 +                               default-state = "off";
 377 +                       };
 378 +               };
 379 +       };
 380 +};
 381 +
 382 +&uart2 {
 383 +       pinctrl-names = "default";
 384 +       pinctrl-0 = <&uart2_pins_b>;
 385 +       status = "okay";
 386 +};
 387 +
 388 +&usb1 {
 389 +       vusb33-supply = <&reg_3p3v>;
 390 +       vbus-supply = <&reg_3p3v>;
 391 +       status = "okay";
 392 +};
 393 +
 394 +&u3phy1 {
 395 +       status = "okay";
 396 +};
 397 +
 398 +&u3phy2 {
 399 +       status = "okay";
 400 +       mediatek,phy-switch = <&hifsys>;
 401 +};
 402 +
 403 +&pcie {
 404 +       pinctrl-names = "default";
 405 +       pinctrl-0 = <&pcie_default>;
 406 +       status = "okay";
 407 +
 408 +       pcie@1,0 {
 409 +               status = "okay";
 410 +       };
 411 +
 412 +       pcie@2,0 {
 413 +               status = "okay";
 414 +       };
 415 +};
 416 +
 417 +&pcie1_phy {
 418 +       status = "okay";
 419 +};
 420 +