projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
mediatek: bump to v4.4
[openwrt/openwrt.git] / target / linux / mediatek / patches-4.4 / 0023-ARM-dts-mediatek-add-MT7623-basic-support.patch
1 From cfe366d7a20f88c7fc92faaf8b25c24e730bd40b Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Tue, 5 Jan 2016 12:16:17 +0100
4 Subject: [PATCH 23/53] ARM: dts: mediatek: add MT7623 basic support
5
6 This adds basic chip support for Mediatek MT7623.
7
8 Signed-off-by: John Crispin <blogic@openwrt.org>
9 ---
10 arch/arm/boot/dts/Makefile | 1 +
11 arch/arm/boot/dts/mt7623-evb.dts | 459 +++++++++++++++++++++++++++++++++
12 arch/arm/boot/dts/mt7623.dtsi | 507 +++++++++++++++++++++++++++++++++++++
13 arch/arm/mach-mediatek/Kconfig | 4 +
14 arch/arm/mach-mediatek/mediatek.c | 1 +
15 5 files changed, 972 insertions(+)
16 create mode 100644 arch/arm/boot/dts/mt7623-evb.dts
17 create mode 100644 arch/arm/boot/dts/mt7623.dtsi
18
19 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
20 index 30bbc37..2bce370 100644
21 --- a/arch/arm/boot/dts/Makefile
22 +++ b/arch/arm/boot/dts/Makefile
23 @@ -774,6 +774,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
24 mt6580-evbp1.dtb \
25 mt6589-aquaris5.dtb \
26 mt6592-evb.dtb \
27 + mt7623-evb.dtb \
28 mt8127-moose.dtb \
29 mt8135-evbp1.dtb
30 dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb
31 diff --git a/arch/arm/boot/dts/mt7623-evb.dts b/arch/arm/boot/dts/mt7623-evb.dts
32 new file mode 100644
33 index 0000000..5e9381d
34 --- /dev/null
35 +++ b/arch/arm/boot/dts/mt7623-evb.dts
36 @@ -0,0 +1,459 @@
37 +/*
38 + * Copyright (c) 2016 MediaTek Inc.
39 + * Author: John Crispin <blogic@openwrt.org>
40 + *
41 + * This program is free software; you can redistribute it and/or modify
42 + * it under the terms of the GNU General Public License version 2 as
43 + * published by the Free Software Foundation.
44 + *
45 + * This program is distributed in the hope that it will be useful,
46 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
47 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
48 + * GNU General Public License for more details.
49 + */
50 +
51 +/dts-v1/;
52 +
53 +#include "mt7623.dtsi"
54 +#include <dt-bindings/gpio/gpio.h>
55 +
56 +/ {
57 + model = "MediaTek MT7623 evaluation board";
58 + compatible = "mediatek,mt7623-evb", "mediatek,mt7623";
59 +
60 + chosen {
61 + stdout-path = &uart2;
62 + };
63 +
64 + memory {
65 + reg = <0 0x80000000 0 0x20000000>;
66 + };
67 +
68 + usb_p1_vbus: regulator@0 {
69 + compatible = "regulator-fixed";
70 + regulator-name = "usb_vbus";
71 + regulator-min-microvolt = <5000000>;
72 + regulator-max-microvolt = <5000000>;
73 + gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
74 + enable-active-high;
75 + };
76 +};
77 +
78 +&pwrap {
79 + pmic: mt6323 {
80 + compatible = "mediatek,mt6323";
81 + interrupt-parent = <&pio>;
82 + interrupts = <150 IRQ_TYPE_LEVEL_HIGH>;
83 + interrupt-controller;
84 + #interrupt-cells = <2>;
85 +
86 + mt6323regulator: mt6323regulator{
87 + compatible = "mediatek,mt6323-regulator";
88 +
89 + mt6323_vproc_reg: buck_vproc{
90 + regulator-name = "vproc";
91 + regulator-min-microvolt = < 700000>;
92 + regulator-max-microvolt = <1350000>;
93 + regulator-ramp-delay = <12500>;
94 + regulator-always-on;
95 + regulator-boot-on;
96 + };
97 +
98 + mt6323_vsys_reg: buck_vsys{
99 + regulator-name = "vsys";
100 + regulator-min-microvolt = <1400000>;
101 + regulator-max-microvolt = <2987500>;
102 + regulator-ramp-delay = <25000>;
103 + regulator-always-on;
104 + regulator-boot-on;
105 + };
106 +
107 + mt6323_vpa_reg: buck_vpa{
108 + regulator-name = "vpa";
109 + regulator-min-microvolt = < 500000>;
110 + regulator-max-microvolt = <3650000>;
111 + };
112 +
113 + mt6323_vtcxo_reg: ldo_vtcxo{
114 + regulator-name = "vtcxo";
115 + regulator-min-microvolt = <2800000>;
116 + regulator-max-microvolt = <2800000>;
117 + regulator-enable-ramp-delay = <90>;
118 + regulator-always-on;
119 + regulator-boot-on;
120 + };
121 +
122 + mt6323_vcn28_reg: ldo_vcn28{
123 + regulator-name = "vcn28";
124 + regulator-min-microvolt = <2800000>;
125 + regulator-max-microvolt = <2800000>;
126 + regulator-enable-ramp-delay = <185>;
127 + };
128 +
129 + mt6323_vcn33_bt_reg: ldo_vcn33_bt{
130 + regulator-name = "vcn33_bt";
131 + regulator-min-microvolt = <3300000>;
132 + regulator-max-microvolt = <3600000>;
133 + regulator-enable-ramp-delay = <185>;
134 + };
135 +
136 + mt6323_vcn33_wifi_reg: ldo_vcn33_wifi{
137 + regulator-name = "vcn33_wifi";
138 + regulator-min-microvolt = <3300000>;
139 + regulator-max-microvolt = <3600000>;
140 + regulator-enable-ramp-delay = <185>;
141 + };
142 +
143 + mt6323_va_reg: ldo_va{
144 + regulator-name = "va";
145 + regulator-min-microvolt = <2800000>;
146 + regulator-max-microvolt = <2800000>;
147 + regulator-enable-ramp-delay = <216>;
148 + regulator-always-on;
149 + regulator-boot-on;
150 + };
151 +
152 + mt6323_vcama_reg: ldo_vcama{
153 + regulator-name = "vcama";
154 + regulator-min-microvolt = <1500000>;
155 + regulator-max-microvolt = <2800000>;
156 + regulator-enable-ramp-delay = <216>;
157 + };
158 +
159 + mt6323_vio28_reg: ldo_vio28{
160 + regulator-name = "vio28";
161 + regulator-min-microvolt = <2800000>;
162 + regulator-max-microvolt = <2800000>;
163 + regulator-enable-ramp-delay = <216>;
164 + regulator-always-on;
165 + regulator-boot-on;
166 + };
167 +
168 + mt6323_vusb_reg: ldo_vusb{
169 + regulator-name = "vusb";
170 + regulator-min-microvolt = <3300000>;
171 + regulator-max-microvolt = <3300000>;
172 + regulator-enable-ramp-delay = <216>;
173 + regulator-boot-on;
174 + };
175 +
176 + mt6323_vmc_reg: ldo_vmc{
177 + regulator-name = "vmc";
178 + regulator-min-microvolt = <1800000>;
179 + regulator-max-microvolt = <3300000>;
180 + regulator-enable-ramp-delay = <36>;
181 + regulator-boot-on;
182 + };
183 +
184 + mt6323_vmch_reg: ldo_vmch{
185 + regulator-name = "vmch";
186 + regulator-min-microvolt = <3000000>;
187 + regulator-max-microvolt = <3300000>;
188 + regulator-enable-ramp-delay = <36>;
189 + regulator-boot-on;
190 + };
191 +
192 + mt6323_vemc3v3_reg: ldo_vemc3v3{
193 + regulator-name = "vemc3v3";
194 + regulator-min-microvolt = <3000000>;
195 + regulator-max-microvolt = <3300000>;
196 + regulator-enable-ramp-delay = <36>;
197 + regulator-boot-on;
198 + };
199 +
200 + mt6323_vgp1_reg: ldo_vgp1{
201 + regulator-name = "vgp1";
202 + regulator-min-microvolt = <1200000>;
203 + regulator-max-microvolt = <3300000>;
204 + regulator-enable-ramp-delay = <216>;
205 + };
206 +
207 + mt6323_vgp2_reg: ldo_vgp2{
208 + regulator-name = "vgp2";
209 + regulator-min-microvolt = <1200000>;
210 + regulator-max-microvolt = <3000000>;
211 + regulator-enable-ramp-delay = <216>;
212 + };
213 +
214 + mt6323_vgp3_reg: ldo_vgp3{
215 + regulator-name = "vgp3";
216 + regulator-min-microvolt = <1200000>;
217 + regulator-max-microvolt = <1800000>;
218 + regulator-enable-ramp-delay = <216>;
219 + };
220 +
221 + mt6323_vcn18_reg: ldo_vcn18{
222 + regulator-name = "vcn18";
223 + regulator-min-microvolt = <1800000>;
224 + regulator-max-microvolt = <1800000>;
225 + regulator-enable-ramp-delay = <216>;
226 + };
227 +
228 + mt6323_vsim1_reg: ldo_vsim1{
229 + regulator-name = "vsim1";
230 + regulator-min-microvolt = <1800000>;
231 + regulator-max-microvolt = <3000000>;
232 + regulator-enable-ramp-delay = <216>;
233 + };
234 +
235 + mt6323_vsim2_reg: ldo_vsim2{
236 + regulator-name = "vsim2";
237 + regulator-min-microvolt = <1800000>;
238 + regulator-max-microvolt = <3000000>;
239 + regulator-enable-ramp-delay = <216>;
240 + };
241 +
242 + mt6323_vrtc_reg: ldo_vrtc{
243 + regulator-name = "vrtc";
244 + regulator-min-microvolt = <2800000>;
245 + regulator-max-microvolt = <2800000>;
246 + regulator-always-on;
247 + regulator-boot-on;
248 + };
249 +
250 + mt6323_vcamaf_reg: ldo_vcamaf{
251 + regulator-name = "vcamaf";
252 + regulator-min-microvolt = <1200000>;
253 + regulator-max-microvolt = <3300000>;
254 + regulator-enable-ramp-delay = <216>;
255 + };
256 +
257 + mt6323_vibr_reg: ldo_vibr{
258 + regulator-name = "vibr";
259 + regulator-min-microvolt = <1200000>;
260 + regulator-max-microvolt = <3300000>;
261 + regulator-enable-ramp-delay = <36>;
262 + };
263 +
264 + mt6323_vrf18_reg: ldo_vrf18{
265 + regulator-name = "vrf18";
266 + regulator-min-microvolt = <1825000>;
267 + regulator-max-microvolt = <1825000>;
268 + regulator-enable-ramp-delay = <187>;
269 + };
270 +
271 + mt6323_vm_reg: ldo_vm{
272 + regulator-name = "vm";
273 + regulator-min-microvolt = <1200000>;
274 + regulator-max-microvolt = <1800000>;
275 + regulator-enable-ramp-delay = <216>;
276 + regulator-always-on;
277 + regulator-boot-on;
278 + };
279 +
280 + mt6323_vio18_reg: ldo_vio18{
281 + regulator-name = "vio18";
282 + regulator-min-microvolt = <1800000>;
283 + regulator-max-microvolt = <1800000>;
284 + regulator-enable-ramp-delay = <216>;
285 + regulator-always-on;
286 + regulator-boot-on;
287 + };
288 +
289 + mt6323_vcamd_reg: ldo_vcamd{
290 + regulator-name = "vcamd";
291 + regulator-min-microvolt = <1200000>;
292 + regulator-max-microvolt = <1800000>;
293 + regulator-enable-ramp-delay = <216>;
294 + };
295 +
296 + mt6323_vcamio_reg: ldo_vcamio{
297 + regulator-name = "vcamio";
298 + regulator-min-microvolt = <1800000>;
299 + regulator-max-microvolt = <1800000>;
300 + regulator-enable-ramp-delay = <216>;
301 + };
302 + };
303 + };
304 +};
305 +
306 +&uart2 {
307 + status = "okay";
308 +};
309 +
310 +&mmc0 {
311 + status = "okay";
312 + pinctrl-names = "default", "state_uhs";
313 + pinctrl-0 = <&mmc0_pins_default>;
314 + pinctrl-1 = <&mmc0_pins_uhs>;
315 + bus-width = <8>;
316 + max-frequency = <50000000>;
317 + cap-mmc-highspeed;
318 + vmmc-supply = <&mt6323_vemc3v3_reg>;
319 + vqmmc-supply = <&mt6323_vio18_reg>;
320 + non-removable;
321 +};
322 +
323 +&mmc1 {
324 + status = "okay";
325 + pinctrl-names = "default", "state_uhs";
326 + pinctrl-0 = <&mmc1_pins_default>;
327 + pinctrl-1 = <&mmc1_pins_uhs>;
328 + bus-width = <4>;
329 + max-frequency = <50000000>;
330 + cap-sd-highspeed;
331 + sd-uhs-sdr25;
332 +// cd-gpios = <&pio 132 0>;
333 + vmmc-supply = <&mt6323_vmch_reg>;
334 + vqmmc-supply = <&mt6323_vmc_reg>;
335 +};
336 +
337 +&pio {
338 + mmc0_pins_default: mmc0default {
339 + pins_cmd_dat {
340 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
341 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
342 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
343 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
344 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
345 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
346 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
347 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
348 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
349 + input-enable;
350 + bias-pull-up;
351 + };
352 +
353 + pins_clk {
354 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
355 + bias-pull-down;
356 + };
357 +
358 + pins_rst {
359 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
360 + bias-pull-up;
361 + };
362 + };
363 +
364 + mmc0_pins_uhs: mmc0 {
365 + pins_cmd_dat {
366 + pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
367 + <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
368 + <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
369 + <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
370 + <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
371 + <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
372 + <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
373 + <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
374 + <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
375 + input-enable;
376 + drive-strength = <MTK_DRIVE_2mA>;
377 + bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
378 + };
379 +
380 + pins_clk {
381 + pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
382 + drive-strength = <MTK_DRIVE_2mA>;
383 + bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
384 + };
385 +
386 + pins_rst {
387 + pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
388 + bias-pull-up;
389 + };
390 + };
391 +
392 + mmc1_pins_default: mmc1default {
393 + pins_cmd_dat {
394 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
395 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
396 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
397 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
398 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
399 + input-enable;
400 + drive-strength = <MTK_DRIVE_4mA>;
401 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
402 + };
403 +
404 + pins_clk {
405 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
406 + bias-pull-down;
407 + drive-strength = <MTK_DRIVE_4mA>;
408 + };
409 +
410 +// pins_insert {
411 +// pinmux = <MT8173_PIN_132_I2S0_DATA1_FUNC_GPIO132>;
412 +// bias-pull-up;
413 +// };
414 + };
415 +
416 + mmc1_pins_uhs: mmc1 {
417 + pins_cmd_dat {
418 + pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
419 + <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
420 + <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
421 + <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
422 + <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
423 + input-enable;
424 + drive-strength = <MTK_DRIVE_4mA>;
425 + bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
426 + };
427 +
428 + pins_clk {
429 + pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
430 + drive-strength = <MTK_DRIVE_4mA>;
431 + bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
432 + };
433 + };
434 +
435 + eth_default: eth {
436 + pins_eth {
437 + pinmux = <MT7623_PIN_275_G2_MDC_FUNC_MDC>,
438 + <MT7623_PIN_276_G2_MDIO_FUNC_MDIO>,
439 + <MT7623_PIN_262_G2_TXEN_FUNC_G2_TXEN>,
440 + <MT7623_PIN_263_G2_TXD3_FUNC_G2_TXD3>,
441 + <MT7623_PIN_264_G2_TXD2_FUNC_G2_TXD2>,
442 + <MT7623_PIN_265_G2_TXD1_FUNC_G2_TXD1>,
443 + <MT7623_PIN_266_G2_TXD0_FUNC_G2_TXD0>,
444 + <MT7623_PIN_267_G2_TXCLK_FUNC_G2_TXC>,
445 + <MT7623_PIN_268_G2_RXCLK_FUNC_G2_RXC>,
446 + <MT7623_PIN_269_G2_RXD0_FUNC_G2_RXD0>,
447 + <MT7623_PIN_270_G2_RXD1_FUNC_G2_RXD1>,
448 + <MT7623_PIN_271_G2_RXD2_FUNC_G2_RXD2>,
449 + <MT7623_PIN_272_G2_RXD3_FUNC_G2_RXD3>,
450 + <MT7623_PIN_273_ESW_INT_FUNC_ESW_INT>,
451 + <MT7623_PIN_274_G2_RXDV_FUNC_G2_RXDV>;
452 + };
453 +
454 + pins_eth_rst {
455 + pinmux = <MT7623_PIN_15_GPIO15_FUNC_GPIO15>;
456 + output-low;
457 + };
458 + };
459 +};
460 +
461 +&usb1 {
462 + vusb33-supply = <&mt6323_vusb_reg>;
463 + vbus-supply = <&usb_p1_vbus>;
464 +// mediatek,wakeup-src = <1>;
465 + status = "okay";
466 +};
467 +
468 +&u3phy1 {
469 + status = "okay";
470 +};
471 +
472 +&pcie {
473 + status = "okay";
474 +};
475 +
476 +&eth {
477 + status = "okay";
478 +};
479 +
480 +&gmac1 {
481 + mac-address = [00 11 22 33 44 56];
482 + status = "okay";
483 +};
484 +
485 +&gmac2 {
486 + mac-address = [00 11 22 33 44 55];
487 + status = "okay";
488 +};
489 +
490 +&gsw {
491 + pinctrl-names = "default";
492 + pinctrl-0 = <&eth_default>;
493 + mediatek,reset-pin = <&pio 15 0>;
494 + status = "okay";
495 +};
496 diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
497 new file mode 100644
498 index 0000000..1ba7790
499 --- /dev/null
500 +++ b/arch/arm/boot/dts/mt7623.dtsi
501 @@ -0,0 +1,507 @@
502 +/*
503 + * Copyright (c) 2016 MediaTek Inc.
504 + * Author: John Crispin <blogic@openwrt.org>
505 + *
506 + * This program is free software; you can redistribute it and/or modify
507 + * it under the terms of the GNU General Public License version 2 as
508 + * published by the Free Software Foundation.
509 + *
510 + * This program is distributed in the hope that it will be useful,
511 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
512 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
513 + * GNU General Public License for more details.
514 + */
515 +
516 +#include <dt-bindings/interrupt-controller/irq.h>
517 +#include <dt-bindings/interrupt-controller/arm-gic.h>
518 +#include <dt-bindings/clock/mt2701-clk.h>
519 +#include <dt-bindings/power/mt2701-power.h>
520 +#include <dt-bindings/phy/phy.h>
521 +#include <dt-bindings/reset-controller/mt2701-resets.h>
522 +#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
523 +#include "skeleton64.dtsi"
524 +
525 +
526 +/ {
527 + compatible = "mediatek,mt7623";
528 + interrupt-parent = <&sysirq>;
529 +
530 + cpus {
531 + #address-cells = <1>;
532 + #size-cells = <0>;
533 +
534 + cpu@0 {
535 + device_type = "cpu";
536 + compatible = "arm,cortex-a7";
537 + reg = <0x0>;
538 + };
539 + cpu@1 {
540 + device_type = "cpu";
541 + compatible = "arm,cortex-a7";
542 + reg = <0x1>;
543 + };
544 + cpu@2 {
545 + device_type = "cpu";
546 + compatible = "arm,cortex-a7";
547 + reg = <0x2>;
548 + };
549 + cpu@3 {
550 + device_type = "cpu";
551 + compatible = "arm,cortex-a7";
552 + reg = <0x3>;
553 + };
554 + };
555 +
556 + system_clk: dummy13m {
557 + compatible = "fixed-clock";
558 + clock-frequency = <13000000>;
559 + #clock-cells = <0>;
560 + };
561 +
562 + rtc_clk: dummy32k {
563 + compatible = "fixed-clock";
564 + clock-frequency = <32000>;
565 + #clock-cells = <0>;
566 + clock-output-names = "clk32k";
567 + };
568 +
569 + clk26m: dummy26m {
570 + compatible = "fixed-clock";
571 + clock-frequency = <26000000>;
572 + #clock-cells = <0>;
573 + clock-output-names = "clk26m";
574 + };
575 +
576 + timer {
577 + compatible = "arm,armv7-timer";
578 + interrupt-parent = <&gic>;
579 + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
580 + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
581 + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
582 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
583 + };
584 +
585 + topckgen: power-controller@10000000 {
586 + compatible = "mediatek,mt7623-topckgen",
587 + "mediatek,mt2701-topckgen",
588 + "syscon";
589 + reg = <0 0x10000000 0 0x1000>;
590 + #clock-cells = <1>;
591 + };
592 +
593 + infracfg: power-controller@10001000 {
594 + compatible = "mediatek,mt7623-infracfg",
595 + "mediatek,mt2701-infracfg",
596 + "syscon";
597 + reg = <0 0x10001000 0 0x1000>;
598 + #clock-cells = <1>;
599 + #reset-cells = <1>;
600 + };
601 +
602 + pericfg: pericfg@10003000 {
603 + compatible = "mediatek,mt7623-pericfg",
604 + "mediatek,mt2701-pericfg",
605 + "syscon";
606 + reg = <0 0x10003000 0 0x1000>;
607 + #clock-cells = <1>;
608 + #reset-cells = <1>;
609 + };
610 +
611 + pio: pinctrl@10005000 {
612 + compatible = "mediatek,mt7623-pinctrl";
613 + reg = <0 0x1000b000 0 0x1000>;
614 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
615 + pins-are-numbered;
616 + gpio-controller;
617 + #gpio-cells = <2>;
618 + interrupt-controller;
619 + interrupt-parent = <&gic>;
620 + #interrupt-cells = <2>;
621 + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
622 + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
623 + };
624 +
625 + syscfg_pctl_a: syscfg@10005000 {
626 + compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
627 + reg = <0 0x10005000 0 0x1000>;
628 + };
629 +
630 + scpsys: scpsys@10006000 {
631 + #power-domain-cells = <1>;
632 + compatible = "mediatek,mt7623-scpsys",
633 + "mediatek,mt2701-scpsys";
634 + reg = <0 0x10006000 0 0x1000>;
635 + infracfg = <&infracfg>;
636 + clocks = <&clk26m>,
637 + <&topckgen CLK_TOP_MM_SEL>;
638 + clock-names = "mfg", "mm";
639 + };
640 +
641 + watchdog: watchdog@10007000 {
642 + compatible = "mediatek,mt7623-wdt",
643 + "mediatek,mt6589-wdt";
644 + reg = <0 0x10007000 0 0x100>;
645 + };
646 +
647 + timer: timer@10008000 {
648 + compatible = "mediatek,mt7623-timer",
649 + "mediatek,mt6577-timer";
650 + reg = <0 0x10008000 0 0x80>;
651 + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
652 + clocks = <&system_clk>, <&rtc_clk>;
653 + clock-names = "system-clk", "rtc-clk";
654 + };
655 +
656 + pwrap: pwrap@1000d000 {
657 + compatible = "mediatek,mt7623-pwrap",
658 + "mediatek,mt2701-pwrap";
659 + reg = <0 0x1000d000 0 0x1000>;
660 + reg-names = "pwrap";
661 + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
662 + resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
663 + reset-names = "pwrap";
664 + clocks = <&infracfg CLK_INFRA_PMICSPI>,
665 + <&infracfg CLK_INFRA_PMICWRAP>;
666 + clock-names = "spi", "wrap";
667 + };
668 +
669 + sysirq: interrupt-controller@10200100 {
670 + compatible = "mediatek,mt7623-sysirq",
671 + "mediatek,mt6577-sysirq";
672 + interrupt-controller;
673 + #interrupt-cells = <3>;
674 + interrupt-parent = <&gic>;
675 + reg = <0 0x10200100 0 0x1c>;
676 + };
677 +
678 + apmixedsys: apmixedsys@10209000 {
679 + compatible = "mediatek,mt7623-apmixedsys",
680 + "mediatek,mt2701-apmixedsys";
681 + reg = <0 0x10209000 0 0x1000>;
682 + #clock-cells = <1>;
683 + };
684 +
685 + gic: interrupt-controller@10211000 {
686 + compatible = "arm,cortex-a7-gic";
687 + interrupt-controller;
688 + #interrupt-cells = <3>;
689 + interrupt-parent = <&gic>;
690 + reg = <0 0x10211000 0 0x1000>,
691 + <0 0x10212000 0 0x1000>,
692 + <0 0x10214000 0 0x2000>,
693 + <0 0x10216000 0 0x2000>;
694 + };
695 +
696 + i2c0: i2c@11007000 {
697 + compatible = "mediatek,mt7623-i2c",
698 + "mediatek,mt6577-i2c";
699 + reg = <0 0x11007000 0 0x70>,
700 + <0 0x11000200 0 0x80>;
701 + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
702 + clock-div = <16>;
703 + clocks = <&pericfg CLK_PERI_I2C0>,
704 + <&pericfg CLK_PERI_AP_DMA>;
705 + clock-names = "main", "dma";
706 + #address-cells = <1>;
707 + #size-cells = <0>;
708 + status = "disabled";
709 + };
710 +
711 + i2c1: i2c@11008000 {
712 + compatible = "mediatek,mt7623-i2c",
713 + "mediatek,mt6577-i2c";
714 + reg = <0 0x11008000 0 0x70>,
715 + <0 0x11000280 0 0x80>;
716 + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
717 + clock-div = <16>;
718 + clocks = <&pericfg CLK_PERI_I2C1>,
719 + <&pericfg CLK_PERI_AP_DMA>;
720 + clock-names = "main", "dma";
721 + #address-cells = <1>;
722 + #size-cells = <0>;
723 + status = "disabled";
724 + };
725 +
726 + i2c2: i2c@11009000 {
727 + compatible = "mediatek,mt7623-i2c",
728 + "mediatek,mt6577-i2c";
729 + reg = <0 0x11009000 0 0x70>,
730 + <0 0x11000300 0 0x80>;
731 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
732 + clock-div = <16>;
733 + clocks = <&pericfg CLK_PERI_I2C2>,
734 + <&pericfg CLK_PERI_AP_DMA>;
735 + clock-names = "main", "dma";
736 + #address-cells = <1>;
737 + #size-cells = <0>;
738 + status = "disabled";
739 + };
740 +
741 + uart0: serial@11002000 {
742 + compatible = "mediatek,mt7623-uart",
743 + "mediatek,mt6577-uart";
744 + reg = <0 0x11002000 0 0x400>;
745 + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
746 + clocks = <&pericfg CLK_PERI_UART0_SEL>,
747 + <&pericfg CLK_PERI_UART0>;
748 + clock-names = "baud", "bus";
749 + status = "disabled";
750 + };
751 +
752 + uart1: serial@11003000 {
753 + compatible = "mediatek,mt7623-uart",
754 + "mediatek,mt6577-uart";
755 + reg = <0 0x11003000 0 0x400>;
756 + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
757 + clocks = <&pericfg CLK_PERI_UART1_SEL>,
758 + <&pericfg CLK_PERI_UART1>;
759 + clock-names = "baud", "bus";
760 + status = "disabled";
761 + };
762 +
763 + uart2: serial@11004000 {
764 + compatible = "mediatek,mt7623-uart",
765 + "mediatek,mt6577-uart";
766 + reg = <0 0x11004000 0 0x400>;
767 + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
768 + clocks = <&pericfg CLK_PERI_UART2_SEL>,
769 + <&pericfg CLK_PERI_UART2>;
770 + clock-names = "baud", "bus";
771 + status = "disabled";
772 + };
773 +
774 + uart3: serial@11005000 {
775 + compatible = "mediatek,mt7623-uart",
776 + "mediatek,mt6577-uart";
777 + reg = <0 0x11005000 0 0x400>;
778 + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
779 + clocks = <&pericfg CLK_PERI_UART3_SEL>,
780 + <&pericfg CLK_PERI_UART3>;
781 + clock-names = "baud", "bus";
782 + status = "disabled";
783 + };
784 +
785 + spi: spi@1100a000 {
786 + compatible = "mediatek,mt7623-spi", "mediatek,mt6589-spi";
787 + reg = <0 0x1100a000 0 0x1000>;
788 + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
789 + clocks = <&pericfg CLK_PERI_SPI0>;
790 + clock-names = "main";
791 +
792 + status = "disabled";
793 + };
794 +
795 + mmc0: mmc@11230000 {
796 + compatible = "mediatek,mt7623-mmc",
797 + "mediatek,mt8135-mmc";
798 + reg = <0 0x11230000 0 0x1000>;
799 + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
800 + clocks = <&pericfg CLK_PERI_MSDC30_0>,
801 + <&topckgen CLK_TOP_MSDC30_0_SEL>;
802 + clock-names = "source", "hclk";
803 + status = "disabled";
804 + };
805 +
806 + mmc1: mmc@11240000 {
807 + compatible = "mediatek,mt7623-mmc",
808 + "mediatek,mt8135-mmc";
809 + reg = <0 0x11240000 0 0x1000>;
810 + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>;
811 + clocks = <&pericfg CLK_PERI_MSDC30_1>,
812 + <&topckgen CLK_TOP_MSDC30_1_SEL>;
813 + clock-names = "source", "hclk";
814 + status = "disabled";
815 + };
816 +
817 + usb1: usb@1a1c0000 {
818 + compatible = "mediatek,mt2701-xhci",
819 + "mediatek,mt8173-xhci";
820 + reg = <0 0x1a1c0000 0 0x1000>,
821 + <0 0x1a1c4700 0 0x0100>;
822 + interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
823 + clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
824 + <&topckgen CLK_TOP_ETHIF_SEL>;
825 + clock-names = "sys_ck", "ethif";
826 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
827 + phys = <&phy_port0 PHY_TYPE_USB3>;
828 + status = "disabled";
829 + };
830 +
831 + u3phy1: usb-phy@1a1c4000 {
832 + compatible = "mediatek,mt2701-u3phy",
833 + "mediatek,mt8173-u3phy";
834 + reg = <0 0x1a1c4000 0 0x0700>;
835 + clocks = <&clk26m>;
836 + clock-names = "u3phya_ref";
837 + #phy-cells = <1>;
838 + #address-cells = <2>;
839 + #size-cells = <2>;
840 + ranges;
841 + status = "disabled";
842 +
843 + phy_port0: phy_port0: port@1a1c4800 {
844 + reg = <0 0x1a1c4800 0 0x800>;
845 + #phy-cells = <1>;
846 + status = "okay";
847 + };
848 + };
849 +
850 + usb2: usb@1a240000 {
851 + compatible = "mediatek,mt2701-xhci",
852 + "mediatek,mt8173-xhci";
853 + reg = <0 0x1a240000 0 0x1000>,
854 + <0 0x1a244700 0 0x0100>;
855 + interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
856 + clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
857 + <&topckgen CLK_TOP_ETHIF_SEL>;
858 + clock-names = "sys_ck", "ethif";
859 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
860 + phys = <&u3phy2 0>;
861 + status = "disabled";
862 + };
863 +
864 + u3phy2: usb-phy@1a244000 {
865 + compatible = "mediatek,mt2701-u3phy",
866 + "mediatek,mt8173-u3phy";
867 + reg = <0 0x1a244000 0 0x0700>,
868 + <0 0x1a244800 0 0x0800>;
869 + clocks = <&clk26m>;
870 + clock-names = "u3phya_ref";
871 + #phy-cells = <1>;
872 + status = "disabled";
873 + };
874 +
875 + hifsys: clock-controller@1a000000 {
876 + compatible = "mediatek,mt7623-hifsys",
877 + "mediatek,mt2701-hifsys",
878 + "syscon";
879 + reg = <0 0x1a000000 0 0x1000>;
880 + #clock-cells = <1>;
881 + #reset-cells = <1>;
882 + };
883 +
884 + pcie: pcie@1a140000 {
885 + compatible = "mediatek,mt7623-pcie";
886 + device_type = "pci";
887 + reg = <0 0x1a140000 0 0x8000>, /* PCI-Express registers */
888 + <0 0x1a149000 0 0x1000>, /* PCI-Express PHY0 */
889 + <0 0x1a14a000 0 0x1000>, /* PCI-Express PHY1 */
890 + <0 0x1a244000 0 0x1000>; /* PCI-Express PHY2 */
891 + reg-names = "pcie", "pcie phy0", "pcie phy1", "pcie phy2";
892 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
893 + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
894 + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
895 + interrupt-names = "pcie0", "pcie1", "pcie2";
896 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
897 + clock-names = "pcie";
898 + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
899 + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
900 + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
901 + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
902 + reset-names = "pcie0", "pcie1", "pcie2";
903 +
904 + mediatek,hifsys = <&hifsys>;
905 +
906 + bus-range = <0x00 0xff>;
907 + #address-cells = <3>;
908 + #size-cells = <2>;
909 +
910 + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* io space */
911 + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* pci memory */
912 +
913 + status = "disabled";
914 +
915 + pcie@1,0 {
916 + device_type = "pci";
917 + reg = <0x0800 0 0 0 0>;
918 +
919 + #address-cells = <3>;
920 + #size-cells = <2>;
921 + ranges;
922 + };
923 +
924 + pcie@2,0{
925 + device_type = "pci";
926 + reg = <0x1000 0 0 0 0>;
927 +
928 + #address-cells = <3>;
929 + #size-cells = <2>;
930 + ranges;
931 + };
932 +
933 + pcie@3,0{
934 + device_type = "pci";
935 + reg = <0x1800 0 0 0 0>;
936 +
937 + #address-cells = <3>;
938 + #size-cells = <2>;
939 + ranges;
940 + };
941 + };
942 +
943 + ethsys: syscon@1b000000 {
944 + #address-cells = <1>;
945 + #size-cells = <1>;
946 + compatible = "mediatek,mt2701-ethsys", "syscon";
947 + reg = <0 0x1b000000 0 0x1000>;
948 + #clock-cells = <1>;
949 + };
950 +
951 + eth: ethernet@1b100000 {
952 + compatible = "mediatek,mt7623-eth";
953 + reg = <0 0x1b100000 0 0x10000>;
954 +
955 + clocks = <&topckgen CLK_TOP_ETHIF_SEL>;
956 + clock-names = "ethif";
957 + interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>;
958 + power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
959 +
960 + mediatek,ethsys = <&ethsys>;
961 + mediatek,switch = <&gsw>;
962 +
963 + #address-cells = <1>;
964 + #size-cells = <0>;
965 +
966 + status = "disabled";
967 +
968 + gmac1: mac@0 {
969 + compatible = "mediatek,eth-mac";
970 + reg = <0>;
971 +
972 + status = "disabled";
973 + };
974 +
975 + gmac2: mac@1 {
976 + compatible = "mediatek,eth-mac";
977 + reg = <1>;
978 +
979 + status = "disabled";
980 + };
981 +
982 + mdio-bus {
983 + #address-cells = <1>;
984 + #size-cells = <0>;
985 +
986 + phy1f: ethernet-phy@1f {
987 + reg = <0x1f>;
988 + phy-mode = "rgmii";
989 + };
990 + };
991 + };
992 +
993 + gsw: switch@1b100000 {
994 + compatible = "mediatek,mt7623-gsw";
995 + reg = <0 0x1b110000 0 0x300000>;
996 + interrupt-parent = <&pio>;
997 + interrupts = <168 IRQ_TYPE_EDGE_RISING>;
998 + clocks = <&apmixedsys CLK_APMIXED_TRGPLL>,
999 + <&ethsys CLK_ETHSYS_ESW>,
1000 + <&ethsys CLK_ETHSYS_GP2>,
1001 + <&ethsys CLK_ETHSYS_GP1>;
1002 + clock-names = "trgpll", "esw", "gp2", "gp1";
1003 + mt7530-supply = <&mt6323_vpa_reg>;
1004 + mediatek,pctl-regmap = <&syscfg_pctl_a>;
1005 + mediatek,ethsys = <&ethsys>;
1006 + status = "disabled";
1007 + };
1008 +};
1009 diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
1010 index 37dd438..7fb605e 100644
1011 --- a/arch/arm/mach-mediatek/Kconfig
1012 +++ b/arch/arm/mach-mediatek/Kconfig
1013 @@ -21,6 +21,10 @@ config MACH_MT6592
1014 bool "MediaTek MT6592 SoCs support"
1015 default ARCH_MEDIATEK
1016
1017 +config MACH_MT7623
1018 + bool "MediaTek MT7623 SoCs support"
1019 + default ARCH_MEDIATEK
1020 +
1021 config MACH_MT8127
1022 bool "MediaTek MT8127 SoCs support"
1023 default ARCH_MEDIATEK
1024 diff --git a/arch/arm/mach-mediatek/mediatek.c b/arch/arm/mach-mediatek/mediatek.c
1025 index d019a08..bcfca37 100644
1026 --- a/arch/arm/mach-mediatek/mediatek.c
1027 +++ b/arch/arm/mach-mediatek/mediatek.c
1028 @@ -46,6 +46,7 @@ static void __init mediatek_timer_init(void)
1029 static const char * const mediatek_board_dt_compat[] = {
1030 "mediatek,mt6589",
1031 "mediatek,mt6592",
1032 + "mediatek,mt7623",
1033 "mediatek,mt8127",
1034 "mediatek,mt8135",
1035 NULL,
1036 --
1037 1.7.10.4
1038
OpenWrt Source Repository