target/linux/mediatek/patches-5.15/802-phy-phy-mtk-tphy-add-auto-load-valid-check-mechanism.patch

   1 From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
   2 From: Zhanyong Wang <zhanyong.wang@mediatek.com>
   3 Date: Tue, 25 Jan 2022 19:03:34 +0800
   4 Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
   5  support
   6
   7 add auto-load-valid check mechanism support
   8
   9 Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
  10 ---
  11  drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
  12  1 file changed, 64 insertions(+), 3 deletions(-)
  13
  14 --- a/drivers/phy/mediatek/phy-mtk-tphy.c
  15 +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
  16 @@ -376,9 +376,13 @@ struct mtk_phy_instance {
  17         u32 type_sw_reg;
  18         u32 type_sw_index;
  19         u32 efuse_sw_en;
  20 +       bool efuse_alv_en;
  21 +       u32 efuse_autoloadvalid;
  22         u32 efuse_intr;
  23         u32 efuse_tx_imp;
  24         u32 efuse_rx_imp;
  25 +       bool efuse_alv_ln1_en;
  26 +       u32 efuse_ln1_autoloadvalid;
  27         u32 efuse_intr_ln1;
  28         u32 efuse_tx_imp_ln1;
  29         u32 efuse_rx_imp_ln1;
  30 @@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy
  31  {
  32         struct device *dev = &instance->phy->dev;
  33         int ret = 0;
  34 +       bool alv = false;
  35
  36         /* tphy v1 doesn't support sw efuse, skip it */
  37         if (!tphy->pdata->sw_efuse_supported) {
  38 @@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy
  39
  40         switch (instance->type) {
  41         case PHY_TYPE_USB2:
  42 +               alv = of_property_read_bool(dev->of_node, "auto_load_valid");
  43 +               if (alv) {
  44 +                       instance->efuse_alv_en = alv;
  45 +                       ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
  46 +                                                       &instance->efuse_autoloadvalid);
  47 +                       if (ret) {
  48 +                               dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
  49 +                               break;
  50 +                       }
  51 +                       dev_info(dev,
  52 +                               "u2 auto load valid efuse: ENABLE with value: %u\n",
  53 +                               instance->efuse_autoloadvalid);
  54 +               }
  55 +
  56                 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
  57                 if (ret) {
  58                         dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
  59 @@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy
  60
  61         case PHY_TYPE_USB3:
  62         case PHY_TYPE_PCIE:
  63 +               alv = of_property_read_bool(dev->of_node, "auto_load_valid");
  64 +               if (alv) {
  65 +                       instance->efuse_alv_en = alv;
  66 +                       ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
  67 +                                                       &instance->efuse_autoloadvalid);
  68 +                       if (ret) {
  69 +                               dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
  70 +                               break;
  71 +                       }
  72 +                       dev_info(dev,
  73 +                               "u3 auto load valid efuse: ENABLE with value: %u\n",
  74 +                               instance->efuse_autoloadvalid);
  75 +               }
  76 +
  77                 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
  78                 if (ret) {
  79                         dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
  80 @@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy
  81                 if (tphy->pdata->version != MTK_PHY_V4)
  82                         break;
  83
  84 +               alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
  85 +               if (alv) {
  86 +                       instance->efuse_alv_ln1_en = alv;
  87 +                       ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
  88 +                                                       &instance->efuse_ln1_autoloadvalid);
  89 +                       if (ret) {
  90 +                               dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
  91 +                               break;
  92 +                       }
  93 +                       dev_info(dev,
  94 +                               "pcie auto load valid efuse: ENABLE with value: %u\n",
  95 +                               instance->efuse_ln1_autoloadvalid);
  96 +               }
  97 +
  98                 ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
  99                 if (ret) {
 100                         dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
 101 @@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy
 102
 103         switch (instance->type) {
 104         case PHY_TYPE_USB2:
 105 +               if (instance->efuse_alv_en &&
 106 +                   instance->efuse_autoloadvalid == 1)
 107 +                       break;
 108 +
 109                 tmp = readl(u2_banks->misc + U3P_MISC_REG1);
 110                 tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
 111                 writel(tmp, u2_banks->misc + U3P_MISC_REG1);
 112 @@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy
 113                 writel(tmp, u2_banks->com + U3P_USBPHYACR1);
 114                 break;
 115         case PHY_TYPE_USB3:
 116 +               if (instance->efuse_alv_en &&
 117 +                   instance->efuse_autoloadvalid == 1)
 118 +                       break;
 119 +
 120                 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
 121                 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
 122                 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
 123 @@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy
 124
 125                 break;
 126         case PHY_TYPE_PCIE:
 127 +               if (instance->efuse_alv_en &&
 128 +                   instance->efuse_autoloadvalid == 1)
 129 +                       break;
 130 +
 131                 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
 132                 tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
 133                 writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
 134 @@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy
 135                 tmp &= ~P3A_RG_IEXT_INTR;
 136                 tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
 137                 writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
 138 -               if (!instance->efuse_intr_ln1 &&
 139 -                   !instance->efuse_rx_imp_ln1 &&
 140 -                   !instance->efuse_tx_imp_ln1)
 141 +
 142 +               if ((!instance->efuse_intr_ln1 &&
 143 +                    !instance->efuse_rx_imp_ln1 &&
 144 +                    !instance->efuse_tx_imp_ln1) ||
 145 +                   (instance->efuse_alv_ln1_en &&
 146 +                    instance->efuse_ln1_autoloadvalid == 1))
 147                         break;
 148
 149                 tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);