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mediatek: fix hardware flow offload
[openwrt/staging/chunkeey.git] / target / linux / mediatek / patches-5.4 / 0999-hnat.patch
1 --- a/drivers/net/ethernet/mediatek/Kconfig
2 +++ b/drivers/net/ethernet/mediatek/Kconfig
3 @@ -15,4 +15,8 @@ config NET_MEDIATEK_SOC
4 This driver supports the gigabit ethernet MACs in the
5 MediaTek SoC family.
6
7 +config NET_MEDIATEK_OFFLOAD
8 + def_bool NET_MEDIATEK_SOC
9 + depends on NET_MEDIATEK_SOC
10 +
11 endif #NET_VENDOR_MEDIATEK
12 --- a/drivers/net/ethernet/mediatek/Makefile
13 +++ b/drivers/net/ethernet/mediatek/Makefile
14 @@ -5,3 +5,4 @@
15
16 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
17 mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
18 +mtk_eth-$(CONFIG_NET_MEDIATEK_OFFLOAD) += mtk_offload.o mtk_debugfs.o
19 --- /dev/null
20 +++ b/drivers/net/ethernet/mediatek/mtk_debugfs.c
21 @@ -0,0 +1,117 @@
22 +/* This program is free software; you can redistribute it and/or modify
23 + * it under the terms of the GNU General Public License as published by
24 + * the Free Software Foundation; version 2 of the License
25 + *
26 + * This program is distributed in the hope that it will be useful,
27 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
28 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 + * GNU General Public License for more details.
30 + *
31 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
32 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
33 + */
34 +
35 +#include "mtk_offload.h"
36 +
37 +static const char *mtk_foe_entry_state_str[] = {
38 + "INVALID",
39 + "UNBIND",
40 + "BIND",
41 + "FIN"
42 +};
43 +
44 +static const char *mtk_foe_packet_type_str[] = {
45 + "IPV4_HNAPT",
46 + "IPV4_HNAT",
47 + "IPV6_1T_ROUTE",
48 + "IPV4_DSLITE",
49 + "IPV6_3T_ROUTE",
50 + "IPV6_5T_ROUTE",
51 + "IPV6_6RD",
52 +};
53 +
54 +#define IPV4_HNAPT 0
55 +#define IPV4_HNAT 1
56 +#define IS_IPV4_HNAPT(x) (((x)->bfib1.pkt_type == IPV4_HNAPT) ? 1: 0)
57 +struct mtk_eth *_eth;
58 +#define es(entry) (mtk_foe_entry_state_str[entry->bfib1.state])
59 +//#define ei(entry, end) (MTK_PPE_TBL_SZ - (int)(end - entry))
60 +#define ei(entry, end) (MTK_PPE_ENTRY_CNT - (int)(end - entry))
61 +#define pt(entry) (mtk_foe_packet_type_str[entry->ipv4_hnapt.bfib1.pkt_type])
62 +
63 +static int mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private)
64 +{
65 + struct mtk_eth *eth = _eth;
66 + struct mtk_foe_entry *entry, *end;
67 + int i = 0;
68 +
69 + entry = eth->foe_table;
70 + end = eth->foe_table + MTK_PPE_ENTRY_CNT;
71 +
72 + while (entry < end) {
73 + if (!entry->bfib1.state) {
74 +
75 + } else if (IS_IPV4_HNAPT(entry)) {
76 + __be32 saddr = htonl(entry->ipv4_hnapt.sip);
77 + __be32 daddr = htonl(entry->ipv4_hnapt.dip);
78 + __be32 nsaddr = htonl(entry->ipv4_hnapt.new_sip);
79 + __be32 ndaddr = htonl(entry->ipv4_hnapt.new_dip);
80 + unsigned char h_dest[ETH_ALEN];
81 + unsigned char h_source[ETH_ALEN];
82 +
83 + *((u32*) h_source) = swab32(entry->ipv4_hnapt.smac_hi);
84 + *((u16*) &h_source[4]) = swab16(entry->ipv4_hnapt.smac_lo);
85 + *((u32*) h_dest) = swab32(entry->ipv4_hnapt.dmac_hi);
86 + *((u16*) &h_dest[4]) = swab16(entry->ipv4_hnapt.dmac_lo);
87 + seq_printf(m,
88 + "(%x)0x%05x|state=%s|type=%s|"
89 + "%pI4:%d->%pI4:%d=>%pI4:%d->%pI4:%d|%pM=>%pM|"
90 + "etype=0x%04x|info1=0x%x|info2=0x%x|"
91 + "vlan1=%d|vlan2=%d\n",
92 + i,
93 + ei(entry, end), es(entry), pt(entry),
94 + &saddr, entry->ipv4_hnapt.sport,
95 + &daddr, entry->ipv4_hnapt.dport,
96 + &nsaddr, entry->ipv4_hnapt.new_sport,
97 + &ndaddr, entry->ipv4_hnapt.new_dport, h_source,
98 + h_dest, ntohs(entry->ipv4_hnapt.etype),
99 + entry->ipv4_hnapt.info_blk1,
100 + entry->ipv4_hnapt.info_blk2,
101 + entry->ipv4_hnapt.vlan1,
102 + entry->ipv4_hnapt.vlan2);
103 + } else
104 + seq_printf(m, "0x%05x state=%s\n",
105 + ei(entry, end), es(entry));
106 + entry++;
107 + i++;
108 + }
109 +
110 + return 0;
111 +}
112 +
113 +static int mtk_ppe_debugfs_foe_open(struct inode *inode, struct file *file)
114 +{
115 + return single_open(file, mtk_ppe_debugfs_foe_show, file->private_data);
116 +}
117 +
118 +static const struct file_operations mtk_ppe_debugfs_foe_fops = {
119 + .open = mtk_ppe_debugfs_foe_open,
120 + .read = seq_read,
121 + .llseek = seq_lseek,
122 + .release = single_release,
123 +};
124 +
125 +int mtk_ppe_debugfs_init(struct mtk_eth *eth)
126 +{
127 + struct dentry *root;
128 +
129 + _eth = eth;
130 +
131 + root = debugfs_create_dir("mtk_ppe", NULL);
132 + if (!root)
133 + return -ENOMEM;
134 +
135 + debugfs_create_file("all_entry", S_IRUGO, root, eth, &mtk_ppe_debugfs_foe_fops);
136 +
137 + return 0;
138 +}
139 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
140 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
141 @@ -19,6 +19,8 @@
142 #include <linux/interrupt.h>
143 #include <linux/pinctrl/devinfo.h>
144 #include <linux/phylink.h>
145 +#include <linux/netfilter.h>
146 +#include <net/netfilter/nf_flow_table.h>
147 #include <net/dsa.h>
148
149 #include "mtk_eth_soc.h"
150 @@ -1327,8 +1329,16 @@ static int mtk_poll_rx(struct napi_struc
151 (trxd.rxd2 & RX_DMA_VTAG))
152 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
153 RX_DMA_VID(trxd.rxd3));
154 - skb_record_rx_queue(skb, 0);
155 - napi_gro_receive(napi, skb);
156 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
157 + if (mtk_offload_check_rx(eth, skb, trxd.rxd4) == 0) {
158 +#endif
159 + skb_record_rx_queue(skb, 0);
160 + napi_gro_receive(napi, skb);
161 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
162 + } else {
163 + dev_kfree_skb(skb);
164 + }
165 +#endif
166
167 skip_rx:
168 ring->data[idx] = new_data;
169 @@ -2292,6 +2302,9 @@ static int mtk_open(struct net_device *d
170 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
171 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
172 refcount_set(&eth->dma_refcnt, 1);
173 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
174 + mtk_ppe_probe(eth);
175 +#endif
176 }
177 else
178 refcount_inc(&eth->dma_refcnt);
179 @@ -2355,6 +2368,9 @@ static int mtk_stop(struct net_device *d
180
181 mtk_dma_free(eth);
182
183 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
184 + mtk_ppe_remove(eth);
185 +#endif
186 return 0;
187 }
188
189 @@ -2853,6 +2869,27 @@ static int mtk_set_rxnfc(struct net_devi
190 return ret;
191 }
192
193 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
194 +static int
195 +mtk_flow_offload(enum flow_offload_type type, struct flow_offload *flow,
196 + struct flow_offload_hw_path *src,
197 + struct flow_offload_hw_path *dest)
198 +{
199 + struct mtk_mac *mac = netdev_priv(src->dev);
200 + struct mtk_eth *eth = mac->hw;
201 +
202 + if (!eth->soc->offload_version)
203 + return -EINVAL;
204 +
205 + if (src->dev->base_addr != dest->dev->base_addr)
206 + return -EINVAL;
207 +
208 + mac = netdev_priv(src->dev);
209 +
210 + return mtk_flow_offload_add(eth, type, flow, src, dest);
211 +}
212 +#endif
213 +
214 static const struct ethtool_ops mtk_ethtool_ops = {
215 .get_link_ksettings = mtk_get_link_ksettings,
216 .set_link_ksettings = mtk_set_link_ksettings,
217 @@ -2884,6 +2921,9 @@ static const struct net_device_ops mtk_n
218 #ifdef CONFIG_NET_POLL_CONTROLLER
219 .ndo_poll_controller = mtk_poll_controller,
220 #endif
221 +#ifdef CONFIG_NET_MEDIATEK_OFFLOAD
222 + .ndo_flow_offload = mtk_flow_offload,
223 +#endif
224 };
225
226 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
227 @@ -3226,6 +3266,7 @@ static const struct mtk_soc_data mt7622_
228 .hw_features = MTK_HW_FEATURES,
229 .required_clks = MT7622_CLKS_BITMAP,
230 .required_pctl = false,
231 + .offload_version = MTK_OFFLOAD_V2,
232 };
233
234 static const struct mtk_soc_data mt7623_data = {
235 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
236 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
237 @@ -790,6 +790,13 @@ enum mkt_eth_capabilities {
238 MTK_MUX_U3_GMAC2_TO_QPHY | \
239 MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
240
241 +enum mtk_flow_offload_version {
242 + MTK_OFFLOAD_NONE = 0,
243 + MTK_OFFLOAD_V1,
244 + MTK_OFFLOAD_V2,
245 + MTK_OFFLOAD_V3,
246 +};
247 +
248 /* struct mtk_eth_data - This is the structure holding all differences
249 * among various plaforms
250 * @ana_rgc3: The offset for register ANA_RGC3 related to
251 @@ -807,6 +814,7 @@ struct mtk_soc_data {
252 u32 required_clks;
253 bool required_pctl;
254 netdev_features_t hw_features;
255 + enum mtk_flow_offload_version offload_version;
256 };
257
258 /* currently no SoC has more than 2 macs */
259 @@ -832,6 +840,23 @@ struct mtk_sgmii {
260 u32 ana_rgc3;
261 };
262
263 +
264 +struct mib_entry {
265 + u32 byt_cnt_l;
266 + u16 byt_cnt_h;
267 + u32 pkt_cnt_l;
268 + u8 pkt_cnt_h;
269 + u8 resv0;
270 + u32 resv1;
271 +} __packed __aligned(4);
272 +
273 +struct hnat_accounting {
274 + u64 bytes;
275 + u64 packets;
276 +};
277 +
278 +
279 +
280 /* struct mtk_eth - This is the main datasructure for holding the state
281 * of the driver
282 * @dev: The device pointer
283 @@ -917,6 +942,16 @@ struct mtk_eth {
284 u32 tx_int_status_reg;
285 u32 rx_dma_l4_valid;
286 int ip_align;
287 +
288 + struct reset_control *rst_ppe;
289 + struct mtk_foe_entry *foe_table;
290 + dma_addr_t foe_table_phys;
291 + struct flow_offload __rcu **foe_flow_table;
292 +
293 + struct mib_entry *foe_mib_cpu;
294 + dma_addr_t foe_mib_dev;
295 + struct hnat_accounting *acct;
296 + bool per_flow_accounting;
297 };
298
299 /* struct mtk_mac - the structure that holds the info about the MACs of the
300 @@ -949,6 +984,7 @@ void mtk_stats_update_mac(struct mtk_mac
301
302 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
303 u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
304 +u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned reg);
305
306 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *np,
307 u32 ana_rgc3);
308 @@ -961,4 +997,13 @@ int mtk_gmac_sgmii_path_setup(struct mtk
309 int mtk_gmac_gephy_path_setup(struct mtk_eth *eth, int mac_id);
310 int mtk_gmac_rgmii_path_setup(struct mtk_eth *eth, int mac_id);
311
312 +int mtk_ppe_probe(struct mtk_eth *eth);
313 +void mtk_ppe_remove(struct mtk_eth *eth);
314 +int mtk_flow_offload_add(struct mtk_eth *eth,
315 + enum flow_offload_type type,
316 + struct flow_offload *flow,
317 + struct flow_offload_hw_path *src,
318 + struct flow_offload_hw_path *dest);
319 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4);
320 +
321 #endif /* MTK_ETH_H */
322 --- /dev/null
323 +++ b/drivers/net/ethernet/mediatek/mtk_offload.c
324 @@ -0,0 +1,609 @@
325 +/* This program is free software; you can redistribute it and/or modify
326 + * it under the terms of the GNU General Public License as published by
327 + * the Free Software Foundation; version 2 of the License
328 + *
329 + * This program is distributed in the hope that it will be useful,
330 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
331 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
332 + * GNU General Public License for more details.
333 + *
334 + * Copyright (C) 2018 John Crispin <john@phrozen.org>
335 + */
336 +
337 +#include "mtk_offload.h"
338 +
339 +#define INVALID 0
340 +#define UNBIND 1
341 +#define BIND 2
342 +#define FIN 3
343 +
344 +#define IPV4_HNAPT 0
345 +#define IPV4_HNAT 1
346 +
347 +static u32
348 +mtk_flow_hash_v4(struct flow_offload_tuple *tuple)
349 +{
350 + u32 ports = ntohs(tuple->src_port) << 16 | ntohs(tuple->dst_port);
351 + u32 src = ntohl(tuple->dst_v4.s_addr);
352 + u32 dst = ntohl(tuple->src_v4.s_addr);
353 + u32 hash = (ports & src) | ((~ports) & dst);
354 + u32 hash_23_0 = hash & 0xffffff;
355 + u32 hash_31_24 = hash & 0xff000000;
356 +
357 + hash = ports ^ src ^ dst ^ ((hash_23_0 << 8) | (hash_31_24 >> 24));
358 + hash = ((hash & 0xffff0000) >> 16 ) ^ (hash & 0xfffff);
359 + hash &= 0x7ff;
360 + hash *= 2;;
361 +
362 + return hash;
363 +}
364 +
365 +static int
366 +mtk_foe_prepare_v4(struct mtk_foe_entry *entry,
367 + struct flow_offload_tuple *tuple,
368 + struct flow_offload_tuple *dest_tuple,
369 + struct flow_offload_hw_path *src,
370 + struct flow_offload_hw_path *dest)
371 +{
372 + int is_mcast = !!is_multicast_ether_addr(dest->eth_dest);
373 +
374 + if (tuple->l4proto == IPPROTO_UDP)
375 + entry->ipv4_hnapt.bfib1.udp = 1;
376 +
377 + entry->ipv4_hnapt.etype = htons(ETH_P_IP);
378 + entry->ipv4_hnapt.bfib1.pkt_type = IPV4_HNAPT;
379 + entry->ipv4_hnapt.iblk2.fqos = 0;
380 + entry->ipv4_hnapt.bfib1.ttl = 1;
381 + entry->ipv4_hnapt.bfib1.cah = 1;
382 + entry->ipv4_hnapt.bfib1.ka = 1;
383 + entry->ipv4_hnapt.iblk2.mcast = is_mcast;
384 + entry->ipv4_hnapt.iblk2.dscp = 0;
385 + entry->ipv4_hnapt.iblk2.port_mg = 0x3f;
386 + entry->ipv4_hnapt.iblk2.port_ag = 0x1f;
387 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
388 + entry->ipv4_hnapt.iblk2.qid = 1;
389 + entry->ipv4_hnapt.iblk2.fqos = 1;
390 +#endif
391 +#ifdef CONFIG_RALINK
392 + entry->ipv4_hnapt.iblk2.dp = 1;
393 + if ((dest->flags & FLOW_OFFLOAD_PATH_VLAN) && (dest->vlan_id > 1))
394 + entry->ipv4_hnapt.iblk2.qid += 8;
395 +#else
396 + entry->ipv4_hnapt.iblk2.dp = (dest->dev->name[3] - '0') + 1;
397 +#endif
398 +
399 + entry->ipv4_hnapt.sip = ntohl(tuple->src_v4.s_addr);
400 + entry->ipv4_hnapt.dip = ntohl(tuple->dst_v4.s_addr);
401 + entry->ipv4_hnapt.sport = ntohs(tuple->src_port);
402 + entry->ipv4_hnapt.dport = ntohs(tuple->dst_port);
403 +
404 + entry->ipv4_hnapt.new_sip = ntohl(dest_tuple->dst_v4.s_addr);
405 + entry->ipv4_hnapt.new_dip = ntohl(dest_tuple->src_v4.s_addr);
406 + entry->ipv4_hnapt.new_sport = ntohs(dest_tuple->dst_port);
407 + entry->ipv4_hnapt.new_dport = ntohs(dest_tuple->src_port);
408 +
409 + entry->bfib1.state = BIND;
410 +
411 + if (dest->flags & FLOW_OFFLOAD_PATH_PPPOE) {
412 + entry->bfib1.psn = 1;
413 + entry->ipv4_hnapt.etype = htons(ETH_P_PPP_SES);
414 + entry->ipv4_hnapt.pppoe_id = dest->pppoe_sid;
415 + }
416 +
417 + if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
418 + entry->ipv4_hnapt.vlan1 = dest->vlan_id;
419 + entry->bfib1.vlan_layer = 1;
420 +
421 + switch (dest->vlan_proto) {
422 + case htons(ETH_P_8021Q):
423 + entry->ipv4_hnapt.bfib1.vpm = 1;
424 + break;
425 + case htons(ETH_P_8021AD):
426 + entry->ipv4_hnapt.bfib1.vpm = 2;
427 + break;
428 + default:
429 + return -EINVAL;
430 + }
431 + }
432 +
433 + if (dest->flags & FLOW_OFFLOAD_PATH_DSA) {
434 + entry->bfib1.vlan_layer = 1;
435 +
436 + entry->ipv4_hnapt.bfib1.vpm = 0;
437 + entry->ipv4_hnapt.etype = BIT(dest->dsa_port);
438 +
439 + if (dest->flags & FLOW_OFFLOAD_PATH_VLAN) {
440 + if (dest->vlan_proto != htons(ETH_P_8021Q))
441 + return -EINVAL;
442 +
443 + entry->ipv4_hnapt.etype |= BIT(8);
444 + } else {
445 + entry->ipv4_hnapt.vlan1 = 0;
446 + }
447 + }
448 +
449 + return 0;
450 +}
451 +
452 +static void
453 +mtk_foe_set_mac(struct mtk_foe_entry *entry, u8 *smac, u8 *dmac)
454 +{
455 + entry->ipv4_hnapt.dmac_hi = swab32(*((u32*) dmac));
456 + entry->ipv4_hnapt.dmac_lo = swab16(*((u16*) &dmac[4]));
457 + entry->ipv4_hnapt.smac_hi = swab32(*((u32*) smac));
458 + entry->ipv4_hnapt.smac_lo = swab16(*((u16*) &smac[4]));
459 +}
460 +
461 +static int
462 +mtk_check_entry_available(struct mtk_eth *eth, u32 hash)
463 +{
464 + struct mtk_foe_entry entry = ((struct mtk_foe_entry *)eth->foe_table)[hash];
465 +
466 + return (entry.bfib1.state == BIND)? 0:1;
467 +}
468 +
469 +static void
470 +mtk_foe_write(struct mtk_eth *eth, u32 hash,
471 + struct mtk_foe_entry *entry)
472 +{
473 + struct mtk_foe_entry *table = (struct mtk_foe_entry *)eth->foe_table;
474 +
475 + memcpy(&table[hash], entry, sizeof(*entry));
476 +}
477 +
478 +int mtk_flow_offload_add(struct mtk_eth *eth,
479 + enum flow_offload_type type,
480 + struct flow_offload *flow,
481 + struct flow_offload_hw_path *src,
482 + struct flow_offload_hw_path *dest)
483 +{
484 + struct flow_offload_tuple *otuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_ORIGINAL].tuple;
485 + struct flow_offload_tuple *rtuple = &flow->tuplehash[FLOW_OFFLOAD_DIR_REPLY].tuple;
486 + u32 time_stamp = mtk_r32(eth, 0x0010) & (0x7fff);
487 + u32 ohash, rhash;
488 + struct mtk_foe_entry orig = {
489 + .bfib1.time_stamp = time_stamp,
490 + .bfib1.psn = 0,
491 + };
492 + struct mtk_foe_entry reply = {
493 + .bfib1.time_stamp = time_stamp,
494 + .bfib1.psn = 0,
495 + };
496 +
497 + if (otuple->l4proto != IPPROTO_TCP && otuple->l4proto != IPPROTO_UDP)
498 + return -EINVAL;
499 +
500 + if (type == FLOW_OFFLOAD_DEL) {
501 + flow = NULL;
502 + synchronize_rcu();
503 + return 0;
504 + }
505 +
506 + switch (otuple->l3proto) {
507 + case AF_INET:
508 + if (mtk_foe_prepare_v4(&orig, otuple, rtuple, src, dest) ||
509 + mtk_foe_prepare_v4(&reply, rtuple, otuple, dest, src))
510 + return -EINVAL;
511 +
512 + ohash = mtk_flow_hash_v4(otuple);
513 + rhash = mtk_flow_hash_v4(rtuple);
514 + break;
515 +
516 + case AF_INET6:
517 + return -EINVAL;
518 +
519 + default:
520 + return -EINVAL;
521 + }
522 +
523 + /* Two-way hash: when hash collision occurs, the hash value will be shifted to the next position. */
524 + if (!mtk_check_entry_available(eth, ohash)){
525 + if (!mtk_check_entry_available(eth, ohash + 1))
526 + return -EINVAL;
527 + ohash += 1;
528 + }
529 + if (!mtk_check_entry_available(eth, rhash)){
530 + if (!mtk_check_entry_available(eth, rhash + 1))
531 + return -EINVAL;
532 + rhash += 1;
533 + }
534 +
535 + mtk_foe_set_mac(&orig, dest->eth_src, dest->eth_dest);
536 + mtk_foe_set_mac(&reply, src->eth_src, src->eth_dest);
537 + mtk_foe_write(eth, ohash, &orig);
538 + mtk_foe_write(eth, rhash, &reply);
539 + rcu_assign_pointer(eth->foe_flow_table[ohash], flow);
540 + rcu_assign_pointer(eth->foe_flow_table[rhash], flow);
541 +
542 + return 0;
543 +}
544 +
545 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
546 +
547 +#define QDMA_TX_SCH_TX 0x1a14
548 +
549 +static void mtk_ppe_scheduler(struct mtk_eth *eth, int id, u32 rate)
550 +{
551 + int exp = 0, shift = 0;
552 + u32 reg = mtk_r32(eth, QDMA_TX_SCH_TX);
553 + u32 val = 0;
554 +
555 + if (rate)
556 + val = BIT(11);
557 +
558 + while (rate > 127) {
559 + rate /= 10;
560 + exp++;
561 + }
562 +
563 + val |= (rate & 0x7f) << 4;
564 + val |= exp & 0xf;
565 + if (id)
566 + shift = 16;
567 + reg &= ~(0xffff << shift);
568 + reg |= val << shift;
569 + mtk_w32(eth, val, QDMA_TX_SCH_TX);
570 +}
571 +
572 +#define QTX_CFG(x) (0x1800 + (x * 0x10))
573 +#define QTX_SCH(x) (0x1804 + (x * 0x10))
574 +
575 +static void mtk_ppe_queue(struct mtk_eth *eth, int id, int sched, int weight, int resv, u32 min_rate, u32 max_rate)
576 +{
577 + int max_exp = 0, min_exp = 0;
578 + u32 reg;
579 +
580 + if (id >= 16)
581 + return;
582 +
583 + reg = mtk_r32(eth, QTX_SCH(id));
584 + reg &= 0x70000000;
585 +
586 + if (sched)
587 + reg |= BIT(31);
588 +
589 + if (min_rate)
590 + reg |= BIT(27);
591 +
592 + if (max_rate)
593 + reg |= BIT(11);
594 +
595 + while (max_rate > 127) {
596 + max_rate /= 10;
597 + max_exp++;
598 + }
599 +
600 + while (min_rate > 127) {
601 + min_rate /= 10;
602 + min_exp++;
603 + }
604 +
605 + reg |= (min_rate & 0x7f) << 20;
606 + reg |= (min_exp & 0xf) << 16;
607 + reg |= (weight & 0xf) << 12;
608 + reg |= (max_rate & 0x7f) << 4;
609 + reg |= max_exp & 0xf;
610 + mtk_w32(eth, reg, QTX_SCH(id));
611 +
612 + resv &= 0xff;
613 + reg = mtk_r32(eth, QTX_CFG(id));
614 + reg &= 0xffff0000;
615 + reg |= (resv << 8) | resv;
616 + mtk_w32(eth, reg, QTX_CFG(id));
617 +}
618 +#endif
619 +
620 +static int mtk_init_foe_table(struct mtk_eth *eth)
621 +{
622 + if (eth->foe_table)
623 + return 0;
624 +
625 + eth->foe_flow_table = devm_kcalloc(eth->dev, MTK_PPE_ENTRY_CNT,
626 + sizeof(*eth->foe_flow_table),
627 + GFP_KERNEL);
628 + if (!eth->foe_flow_table)
629 + return -EINVAL;
630 +
631 + /* map the FOE table */
632 + eth->foe_table = dmam_alloc_coherent(eth->dev, MTK_PPE_TBL_SZ,
633 + &eth->foe_table_phys, GFP_KERNEL);
634 + if (!eth->foe_table) {
635 + dev_err(eth->dev, "failed to allocate foe table\n");
636 + kfree(eth->foe_flow_table);
637 + return -ENOMEM;
638 + }
639 +
640 +
641 + return 0;
642 +}
643 +
644 +static int mtk_ppe_start(struct mtk_eth *eth)
645 +{
646 + u32 foe_mib_tb_sz;
647 + u32 foe_etry_num = MTK_PPE_ENTRY_CNT;
648 +
649 + int ret;
650 +
651 + ret = mtk_init_foe_table(eth);
652 + if (ret)
653 + return ret;
654 +
655 + /* tell the PPE about the tables base address */
656 + mtk_w32(eth, eth->foe_table_phys, MTK_REG_PPE_TB_BASE);
657 +
658 + /* flush the table */
659 + memset(eth->foe_table, 0, MTK_PPE_TBL_SZ);
660 +
661 + eth->per_flow_accounting = false; //true;
662 +
663 + if (eth->per_flow_accounting) {
664 + foe_mib_tb_sz = foe_etry_num * sizeof(struct mib_entry);
665 + eth->foe_mib_cpu = dma_alloc_coherent(eth->dev, foe_mib_tb_sz,
666 + &eth->foe_mib_dev, GFP_KERNEL);
667 + if (!eth->foe_mib_cpu)
668 + return -1;
669 + mtk_w32(eth, eth->foe_mib_dev, MTK_REG_PPE_MIB_TB_BASE);
670 + memset(eth->foe_mib_cpu, 0, foe_mib_tb_sz);
671 +
672 + eth->acct =
673 + kzalloc(foe_etry_num * sizeof(struct hnat_accounting),
674 + GFP_KERNEL);
675 + if (!eth->acct)
676 + return -1;
677 + }
678 +
679 + /* setup hashing */
680 + mtk_m32(eth,
681 + MTK_PPE_TB_CFG_HASH_MODE_MASK | MTK_PPE_TB_CFG_TBL_SZ_MASK,
682 + MTK_PPE_TB_CFG_HASH_MODE1 | MTK_PPE_TB_CFG_TBL_SZ_4K,
683 + MTK_REG_PPE_TB_CFG);
684 +
685 + /* set the default hashing seed */
686 + mtk_w32(eth, MTK_PPE_HASH_SEED, MTK_REG_PPE_HASH_SEED);
687 +
688 + /* each foe entry is 80bytes and is setup by cpu forwarding*/
689 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_TB_CFG_ENTRY_SZ_MASK |
690 + MTK_PPE_TB_CFG_SMA_MASK,
691 + MTK_PPE_TB_CFG_ENTRY_SZ_64B | MTK_PPE_TB_CFG_SMA_FWD_CPU,
692 + MTK_REG_PPE_TB_CFG);
693 +
694 + /* set ip proto */
695 + //writel(0xFFFFFFFF, host->ppe_base + PPE_IP_PROT_CHK);
696 + mtk_w32(eth, 0xFFFFFFFF, MTK_REG_PPE_IP_PROT_CHK);
697 +
698 + /* setup caching */
699 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 1);
700 + mtk_m32(eth, 1, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
701 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_X_MODE, 0);
702 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
703 + // cr_set_field(host->ppe_base + PPE_CAH_CTRL, CAH_EN, 1);
704 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE, MTK_PPE_CAH_CTRL_EN,
705 + MTK_REG_PPE_CAH_CTRL);
706 +
707 + /* enable FOE */
708 + /* cr_set_bits(host->ppe_base + PPE_FLOW_CFG,
709 + BIT_UDP_IP4F_NAT_EN | BIT_IPV4_NAT_EN | BIT_IPV4_NAPT_EN |
710 + BIT_IPV4_NAT_FRAG_EN | BIT_IPV4_HASH_GREK |
711 + BIT_IPV4_DSL_EN | BIT_IPV6_6RD_EN |
712 + BIT_IPV6_3T_ROUTE_EN | BIT_IPV6_5T_ROUTE_EN); */
713 + mtk_m32(eth, 0, MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
714 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
715 + MTK_PPE_FLOW_CFG_IPV4_GREK_EN,
716 + MTK_REG_PPE_FLOW_CFG);
717 +
718 + mtk_w32(eth, 0x000a7780, MTK_REG_PPE_FLOW_CFG);
719 +
720 + /* setup flow entry un/bind aging */
721 + // cr_set_field(host->ppe_base + PPE_TB_CFG, NTU_AGE, 1);
722 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UNBD_AGE, 1);
723 + // cr_set_field(host->ppe_base + PPE_TB_CFG, TCP_AGE, 1);
724 + // cr_set_field(host->ppe_base + PPE_TB_CFG, UDP_AGE, 1);
725 + // cr_set_field(host->ppe_base + PPE_TB_CFG, FIN_AGE, 1);
726 + mtk_m32(eth, 0,
727 + MTK_PPE_TB_CFG_UNBD_AGE | MTK_PPE_TB_CFG_NTU_AGE |
728 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
729 + MTK_PPE_TB_CFG_TCP_AGE,
730 + MTK_REG_PPE_TB_CFG);
731 +
732 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_MNP, 1000);
733 + // cr_set_field(host->ppe_base + PPE_UNB_AGE, UNB_DLTA, 3);
734 + mtk_m32(eth, MTK_PPE_UNB_AGE_MNP_MASK | MTK_PPE_UNB_AGE_DLTA_MASK,
735 + MTK_PPE_UNB_AGE_MNP | MTK_PPE_UNB_AGE_DLTA,
736 + MTK_REG_PPE_UNB_AGE);
737 +
738 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, UDP_DLTA, 12);
739 + // cr_set_field(host->ppe_base + PPE_BND_AGE_0, NTU_DLTA, 1);
740 + mtk_m32(eth, MTK_PPE_BND_AGE0_NTU_DLTA_MASK |
741 + MTK_PPE_BND_AGE0_UDP_DLTA_MASK,
742 + MTK_PPE_BND_AGE0_NTU_DLTA | MTK_PPE_BND_AGE0_UDP_DLTA,
743 + MTK_REG_PPE_BND_AGE0);
744 + mtk_w32(eth, 0x0001000c, MTK_REG_PPE_BND_AGE0);
745 +
746 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, FIN_DLTA, 1);
747 + // cr_set_field(host->ppe_base + PPE_BND_AGE_1, TCP_DLTA, 7);
748 + mtk_m32(eth, MTK_PPE_BND_AGE1_FIN_DLTA_MASK |
749 + MTK_PPE_BND_AGE1_TCP_DLTA_MASK,
750 + MTK_PPE_BND_AGE1_FIN_DLTA | MTK_PPE_BND_AGE1_TCP_DLTA,
751 + MTK_REG_PPE_BND_AGE1);
752 + mtk_w32(eth, 0x00010007, MTK_REG_PPE_BND_AGE1);
753 +
754 + /* setup flow entry keep alive */
755 + // cr_set_field(host->ppe_base + PPE_TB_CFG, SCAN_MODE, 2);
756 + // cr_set_field(host->ppe_base + PPE_TB_CFG, KA_CFG, 3);
757 + mtk_m32(eth, MTK_PPE_TB_CFG_KA_MASK | MTK_PPE_TB_CFG_SCAN_MODE_MASK,
758 + MTK_PPE_TB_CFG_KA | MTK_PPE_TB_CFG_SCAN_MODE,
759 + MTK_REG_PPE_TB_CFG);
760 + // cr_set_field(host->ppe_base + PPE_KA, KA_T, 1);
761 + // cr_set_field(host->ppe_base + PPE_KA, TCP_KA, 1);
762 + // cr_set_field(host->ppe_base + PPE_KA, UDP_KA, 1);
763 + mtk_w32(eth, MTK_PPE_KA_UDP | MTK_PPE_KA_TCP | MTK_PPE_KA_T, MTK_REG_PPE_KA);
764 +
765 + /* setup flow entry rate limit */
766 + mtk_w32(eth, (0x3fff << 16) | 0x3fff, MTK_REG_PPE_BIND_LMT_0);
767 + mtk_w32(eth, 0x2000000 | MTK_PPE_NTU_KA | 0x3fff, MTK_REG_PPE_BIND_LMT_1);
768 + /* 30 packets per second */
769 + mtk_m32(eth, MTK_PPE_BNDR_RATE_MASK, 0x1e, MTK_REG_PPE_BNDR);
770 +
771 + /* enable the PPE */
772 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_EN, MTK_REG_PPE_GLO_CFG);
773 +
774 + /* set the default forwarding port to PDMA */
775 + mtk_w32(eth, 0x0, MTK_REG_PPE_DFT_CPORT);
776 +
777 + /* disallow packets with TTL=0 */
778 + mtk_m32(eth, 0, MTK_PPE_GLO_CFG_TTL0_DROP, MTK_REG_PPE_GLO_CFG);
779 +
780 + /*enable ppe mib counter*/
781 + if (eth->per_flow_accounting) {
782 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CFG);
783 + mtk_w32(eth, 0x3, MTK_REG_PPE_MIB_CAH_CTRL);
784 + }
785 +
786 + /* send all traffic from gmac to the ppe */
787 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(0));
788 + mtk_m32(eth, 0xffff, 0x4444, MTK_GDMA_FWD_CFG(1));
789 +
790 + mtk_w32(eth, 0x00027fb4, MTK_REG_PPE_TB_CFG);
791 +
792 + dev_info(eth->dev, "PPE started\n");
793 +
794 +#ifdef CONFIG_NET_MEDIATEK_HW_QOS
795 + mtk_ppe_scheduler(eth, 0, 500000);
796 + mtk_ppe_scheduler(eth, 1, 500000);
797 + mtk_ppe_queue(eth, 0, 0, 7, 32, 250000, 0);
798 + mtk_ppe_queue(eth, 1, 0, 7, 32, 250000, 0);
799 + mtk_ppe_queue(eth, 8, 1, 7, 32, 250000, 0);
800 + mtk_ppe_queue(eth, 9, 1, 7, 32, 250000, 0);
801 +#endif
802 +
803 + return 0;
804 +}
805 +
806 +static int mtk_ppe_busy_wait(struct mtk_eth *eth)
807 +{
808 + unsigned long t_start = jiffies;
809 + u32 r = 0;
810 +
811 + while (1) {
812 + r = mtk_r32(eth, MTK_REG_PPE_GLO_CFG);
813 + if (!(r & MTK_PPE_GLO_CFG_BUSY))
814 + return 0;
815 + if (time_after(jiffies, t_start + HZ))
816 + break;
817 + usleep_range(10, 20);
818 + }
819 +
820 + dev_err(eth->dev, "ppe: table busy timeout - resetting\n");
821 + reset_control_reset(eth->rst_ppe);
822 +
823 + return -ETIMEDOUT;
824 +}
825 +
826 +static int mtk_ppe_stop(struct mtk_eth *eth)
827 +{
828 + u32 r1 = 0, r2 = 0;
829 + int i;
830 +
831 + /* discard all traffic while we disable the PPE */
832 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(0));
833 + mtk_m32(eth, 0xffff, 0x7777, MTK_GDMA_FWD_CFG(1));
834 +
835 + if (mtk_ppe_busy_wait(eth))
836 + return -ETIMEDOUT;
837 +
838 + /* invalidate all flow table entries */
839 + for (i = 0; i < MTK_PPE_ENTRY_CNT; i++)
840 + eth->foe_table[i].bfib1.state = FOE_STATE_INVALID;
841 +
842 + /* disable caching */
843 + mtk_m32(eth, 0, MTK_PPE_CAH_CTRL_X_MODE, MTK_REG_PPE_CAH_CTRL);
844 + mtk_m32(eth, MTK_PPE_CAH_CTRL_X_MODE | MTK_PPE_CAH_CTRL_EN, 0,
845 + MTK_REG_PPE_CAH_CTRL);
846 +
847 + /* flush cache has to be ahead of hnat diable --*/
848 + mtk_m32(eth, MTK_PPE_GLO_CFG_EN, 0, MTK_REG_PPE_GLO_CFG);
849 +
850 + /* disable FOE */
851 + mtk_m32(eth,
852 + MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN |
853 + MTK_PPE_FLOW_CFG_IPV4_NAPT_EN | MTK_PPE_FLOW_CFG_IPV4_NAT_EN |
854 + MTK_PPE_FLOW_CFG_FUC_FOE | MTK_PPE_FLOW_CFG_FMC_FOE,
855 + 0, MTK_REG_PPE_FLOW_CFG);
856 +
857 + /* disable FOE aging */
858 + mtk_m32(eth, 0,
859 + MTK_PPE_TB_CFG_FIN_AGE | MTK_PPE_TB_CFG_UDP_AGE |
860 + MTK_PPE_TB_CFG_TCP_AGE | MTK_PPE_TB_CFG_UNBD_AGE |
861 + MTK_PPE_TB_CFG_NTU_AGE, MTK_REG_PPE_TB_CFG);
862 +
863 + r1 = mtk_r32(eth, 0x100);
864 + r2 = mtk_r32(eth, 0x10c);
865 +
866 + dev_info(eth->dev, "0x100 = 0x%x, 0x10c = 0x%x\n", r1, r2);
867 +
868 + if (((r1 & 0xff00) >> 0x8) >= (r1 & 0xff) ||
869 + ((r1 & 0xff00) >> 0x8) >= (r2 & 0xff)) {
870 + dev_info(eth->dev, "reset pse\n");
871 + mtk_w32(eth, 0x1, 0x4);
872 + }
873 +
874 + /* set the foe entry base address to 0 */
875 + mtk_w32(eth, 0, MTK_REG_PPE_TB_BASE);
876 +
877 + if (mtk_ppe_busy_wait(eth))
878 + return -ETIMEDOUT;
879 +
880 + /* send all traffic back to the DMA engine */
881 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(0));
882 + mtk_m32(eth, 0xffff, 0x0, MTK_GDMA_FWD_CFG(1));
883 + return 0;
884 +}
885 +
886 +static void mtk_offload_keepalive(struct mtk_eth *eth, unsigned int hash)
887 +{
888 + struct flow_offload *flow;
889 +
890 + rcu_read_lock();
891 + flow = rcu_dereference(eth->foe_flow_table[hash]);
892 + if (flow)
893 + flow->timeout = jiffies + 30 * HZ;
894 + rcu_read_unlock();
895 +}
896 +
897 +int mtk_offload_check_rx(struct mtk_eth *eth, struct sk_buff *skb, u32 rxd4)
898 +{
899 + unsigned int hash;
900 +
901 + switch (FIELD_GET(MTK_RXD4_CPU_REASON, rxd4)) {
902 + case MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR:
903 + case MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR:
904 + case MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR:
905 + hash = FIELD_GET(MTK_RXD4_FOE_ENTRY, rxd4);
906 + mtk_offload_keepalive(eth, hash);
907 + return -1;
908 + case MTK_CPU_REASON_PACKET_SAMPLING:
909 + return -1;
910 + default:
911 + return 0;
912 + }
913 +}
914 +
915 +int mtk_ppe_probe(struct mtk_eth *eth)
916 +{
917 + int err;
918 +
919 + err = mtk_ppe_start(eth);
920 + if (err)
921 + return err;
922 +
923 + err = mtk_ppe_debugfs_init(eth);
924 + if (err)
925 + return err;
926 +
927 + return 0;
928 +}
929 +
930 +void mtk_ppe_remove(struct mtk_eth *eth)
931 +{
932 + mtk_ppe_stop(eth);
933 +}
934 --- /dev/null
935 +++ b/drivers/net/ethernet/mediatek/mtk_offload.h
936 @@ -0,0 +1,298 @@
937 +/* This program is free software; you can redistribute it and/or modify
938 + * it under the terms of the GNU General Public License as published by
939 + * the Free Software Foundation; version 2 of the License
940 + *
941 + * This program is distributed in the hope that it will be useful,
942 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
943 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
944 + * GNU General Public License for more details.
945 + *
946 + * Copyright (C) 2014-2016 Sean Wang <sean.wang@mediatek.com>
947 + * Copyright (C) 2016-2017 John Crispin <blogic@openwrt.org>
948 + */
949 +
950 +#include <linux/dma-mapping.h>
951 +#include <linux/delay.h>
952 +#include <linux/if.h>
953 +#include <linux/io.h>
954 +#include <linux/module.h>
955 +#include <linux/of_device.h>
956 +#include <linux/platform_device.h>
957 +#include <linux/reset.h>
958 +#include <linux/netfilter.h>
959 +#include <linux/netdevice.h>
960 +#include <net/netfilter/nf_flow_table.h>
961 +#include <linux/debugfs.h>
962 +#include <linux/etherdevice.h>
963 +#include <linux/bitfield.h>
964 +
965 +#include "mtk_eth_soc.h"
966 +
967 +#ifdef CONFIG_RALINK
968 +/* ramips compat */
969 +#define mtk_eth fe_priv
970 +#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
971 +#define mtk_m32 fe_m32
972 +
973 +static inline u32
974 +mtk_r32(struct mtk_eth *eth, u32 reg)
975 +{
976 + return fe_r32(reg);
977 +}
978 +
979 +static inline void
980 +mtk_w32(struct mtk_eth *eth, u32 val, u32 reg)
981 +{
982 + fe_w32(val, reg);
983 +}
984 +#endif
985 +
986 +#define MTK_REG_PPE_GLO_CFG 0xe00
987 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
988 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
989 +#define MTK_PPE_GLO_CFG_EN BIT(0)
990 +
991 +#define MTK_REG_PPE_FLOW_CFG 0xe04
992 +#define MTK_PPE_FLOW_CFG_IPV4_GREK_EN BIT(19)
993 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_FRAG_EN BIT(17)
994 +#define MTK_PPE_FLOW_CFG_IPV4_NAPT_EN BIT(13)
995 +#define MTK_PPE_FLOW_CFG_IPV4_NAT_EN BIT(12)
996 +#define MTK_PPE_FLOW_CFG_FUC_FOE BIT(2)
997 +#define MTK_PPE_FLOW_CFG_FMC_FOE BIT(1)
998 +
999 +#define MTK_REG_PPE_IP_PROT_CHK 0xe08
1000 +
1001 +#define MTK_REG_PPE_TB_BASE 0xe20
1002 +
1003 +#define MTK_REG_PPE_BNDR 0xe28
1004 +#define MTK_PPE_BNDR_RATE_MASK 0xffff
1005 +
1006 +#define MTK_REG_PPE_BIND_LMT_0 0xe2C
1007 +
1008 +#define MTK_REG_PPE_BIND_LMT_1 0xe30
1009 +#define MTK_PPE_NTU_KA BIT(16)
1010 +
1011 +#define MTK_REG_PPE_KA 0xe34
1012 +#define MTK_PPE_KA_T BIT(0)
1013 +#define MTK_PPE_KA_TCP BIT(16)
1014 +#define MTK_PPE_KA_UDP BIT(24)
1015 +
1016 +#define MTK_REG_PPE_UNB_AGE 0xe38
1017 +#define MTK_PPE_UNB_AGE_MNP_MASK (0xffff << 16)
1018 +#define MTK_PPE_UNB_AGE_MNP (1000 << 16)
1019 +#define MTK_PPE_UNB_AGE_DLTA_MASK 0xff
1020 +#define MTK_PPE_UNB_AGE_DLTA 3
1021 +
1022 +#define MTK_REG_PPE_BND_AGE0 0xe3c
1023 +#define MTK_PPE_BND_AGE0_NTU_DLTA_MASK (0xffff << 16)
1024 +#define MTK_PPE_BND_AGE0_NTU_DLTA (5 << 16)
1025 +#define MTK_PPE_BND_AGE0_UDP_DLTA_MASK 0xffff
1026 +#define MTK_PPE_BND_AGE0_UDP_DLTA 5
1027 +
1028 +#define MTK_REG_PPE_BND_AGE1 0xe40
1029 +#define MTK_PPE_BND_AGE1_FIN_DLTA_MASK (0xffff << 16)
1030 +#define MTK_PPE_BND_AGE1_FIN_DLTA (5 << 16)
1031 +#define MTK_PPE_BND_AGE1_TCP_DLTA_MASK 0xffff
1032 +#define MTK_PPE_BND_AGE1_TCP_DLTA 5
1033 +
1034 +#define MTK_REG_PPE_DFT_CPORT 0xe48
1035 +
1036 +#define MTK_REG_PPE_TB_CFG 0xe1c
1037 +#define MTK_PPE_TB_CFG_X_MODE_MASK (3 << 18)
1038 +#define MTK_PPE_TB_CFG_HASH_MODE1 BIT(14)
1039 +#define MTK_PPE_TB_CFG_HASH_MODE_MASK (0x3 << 14)
1040 +#define MTK_PPE_TB_CFG_KA (3 << 12)
1041 +#define MTK_PPE_TB_CFG_KA_MASK (0x3 << 12)
1042 +#define MTK_PPE_TB_CFG_SCAN_MODE (2 << 16)
1043 +#define MTK_PPE_TB_CFG_SCAN_MODE_MASK (0x3 << 16)
1044 +#define MTK_PPE_TB_CFG_FIN_AGE BIT(11)
1045 +#define MTK_PPE_TB_CFG_UDP_AGE BIT(10)
1046 +#define MTK_PPE_TB_CFG_TCP_AGE BIT(9)
1047 +#define MTK_PPE_TB_CFG_UNBD_AGE BIT(8)
1048 +#define MTK_PPE_TB_CFG_NTU_AGE BIT(7)
1049 +#define MTK_PPE_TB_CFG_SMA_FWD_CPU (0x3 << 4)
1050 +#define MTK_PPE_TB_CFG_SMA_MASK (0x3 << 4)
1051 +#define MTK_PPE_TB_CFG_ENTRY_SZ_64B 0
1052 +#define MTK_PPE_TB_CFG_ENTRY_SZ_80B 1
1053 +#define MTK_PPE_TB_CFG_ENTRY_SZ_MASK BIT(3)
1054 +#define MTK_PPE_TB_CFG_TBL_SZ_4K 4
1055 +#define MTK_PPE_TB_CFG_TBL_SZ_MASK 0x7
1056 +
1057 +#define MTK_REG_PPE_HASH_SEED 0xe44
1058 +#define MTK_PPE_HASH_SEED 0x12345678
1059 +
1060 +
1061 +#define MTK_REG_PPE_CAH_CTRL 0xf20
1062 +#define MTK_PPE_CAH_CTRL_X_MODE BIT(9)
1063 +#define MTK_PPE_CAH_CTRL_EN BIT(0)
1064 +
1065 +#define MTK_REG_PPE_MIB_CFG 0xf34
1066 +#define MTK_REG_PPE_MIB_TB_BASE 0xf38
1067 +#define MTK_REG_PPE_MIB_CAH_CTRL 0Xf50
1068 +
1069 +
1070 +struct mtk_foe_unbind_info_blk {
1071 + u32 time_stamp:8;
1072 + u32 pcnt:16; /* packet count */
1073 + u32 preb:1;
1074 + u32 pkt_type:3;
1075 + u32 state:2;
1076 + u32 udp:1;
1077 + u32 sta:1; /* static entry */
1078 +} __attribute__ ((packed));
1079 +
1080 +struct mtk_foe_bind_info_blk {
1081 + u32 time_stamp:15;
1082 + u32 ka:1; /* keep alive */
1083 + u32 vlan_layer:3;
1084 + u32 psn:1; /* egress packet has PPPoE session */
1085 +#ifdef CONFIG_RALINK
1086 + u32 vpm:2; /* 0:ethertype remark, 1:0x8100(CR default) */
1087 +#else
1088 + u32 vpm:1; /* 0:ethertype remark, 1:0x8100(CR default) */
1089 + u32 ps:1; /* packet sampling */
1090 +#endif
1091 + u32 cah:1; /* cacheable flag */
1092 + u32 rmt:1; /* remove tunnel ip header (6rd/dslite only) */
1093 + u32 ttl:1;
1094 + u32 pkt_type:3;
1095 + u32 state:2;
1096 + u32 udp:1;
1097 + u32 sta:1; /* static entry */
1098 +} __attribute__ ((packed));
1099 +
1100 +struct mtk_foe_info_blk2 {
1101 + u32 qid:4; /* QID in Qos Port */
1102 + u32 fqos:1; /* force to PSE QoS port */
1103 + u32 dp:3; /* force to PSE port x
1104 + 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP */
1105 + u32 mcast:1; /* multicast this packet to CPU */
1106 + u32 pcpl:1; /* OSBN */
1107 + u32 mlen:1; /* 0:post 1:pre packet length in meter */
1108 + u32 alen:1; /* 0:post 1:pre packet length in accounting */
1109 + u32 port_mg:6; /* port meter group */
1110 + u32 port_ag:6; /* port account group */
1111 + u32 dscp:8; /* DSCP value */
1112 +} __attribute__ ((packed));
1113 +
1114 +/* info blk2 for WHNAT */
1115 +struct hnat_info_blk2_whnat {
1116 + u32 qid : 4; /* QID[3:0] in Qos Port */
1117 + u32 fqos : 1; /* force to PSE QoS port */
1118 + u32 dp : 3; /* force to PSE port x
1119 + * 0:PSE,1:GSW, 2:GMAC,4:PPE,5:QDMA,7=DROP
1120 + */
1121 + u32 mcast : 1; /* multicast this packet to CPU */
1122 + u32 pcpl : 1; /* OSBN */
1123 + u32 mibf : 1; /* 0:off 1:on PPE MIB counter */
1124 + u32 alen : 1; /* 0:post 1:pre packet length in accounting */
1125 + u32 qid2 : 2; /* QID[5:4] in Qos Port */
1126 + u32 resv : 2;
1127 + u32 wdmaid : 1; /* 0:to pcie0 dev 1:to pcie1 dev */
1128 + u32 winfoi : 1; /* 0:off 1:on Wi-Fi hwnat support */
1129 + u32 port_ag : 6; /* port account group */
1130 + u32 dscp : 8; /* DSCP value */
1131 +} __attribute__ ((packed));
1132 +
1133 +struct hnat_winfo {
1134 + u32 bssid : 6; /* WiFi Bssidx */
1135 + u32 wcid : 8; /* WiFi wtable Idx */
1136 + u32 rxid : 2; /* WiFi Ring idx */
1137 +} __attribute__ ((packed));
1138 +
1139 +struct mtk_foe_ipv4_hnapt {
1140 + union {
1141 + struct mtk_foe_bind_info_blk bfib1;
1142 + struct mtk_foe_unbind_info_blk udib1;
1143 + u32 info_blk1;
1144 + };
1145 + u32 sip;
1146 + u32 dip;
1147 + u16 dport;
1148 + u16 sport;
1149 + union {
1150 + struct mtk_foe_info_blk2 iblk2;
1151 + struct hnat_info_blk2_whnat iblk2w;
1152 + u32 info_blk2;
1153 + };
1154 + u32 new_sip;
1155 + u32 new_dip;
1156 + u16 new_dport;
1157 + u16 new_sport;
1158 + u32 resv1;
1159 + u32 resv2;
1160 + u32 resv3:26;
1161 + u32 act_dp:6; /* UDF */
1162 + u16 vlan1;
1163 + u16 etype;
1164 + u32 dmac_hi;
1165 + union {
1166 + struct hnat_winfo winfo;
1167 + u16 vlan2;
1168 + };
1169 + u16 dmac_lo;
1170 + u32 smac_hi;
1171 + u16 pppoe_id;
1172 + u16 smac_lo;
1173 +} __attribute__ ((packed));
1174 +
1175 +struct mtk_foe_entry {
1176 + union {
1177 + struct mtk_foe_unbind_info_blk udib1;
1178 + struct mtk_foe_bind_info_blk bfib1;
1179 + struct mtk_foe_ipv4_hnapt ipv4_hnapt;
1180 + };
1181 +};
1182 +
1183 +enum mtk_foe_entry_state {
1184 + FOE_STATE_INVALID = 0,
1185 + FOE_STATE_UNBIND = 1,
1186 + FOE_STATE_BIND = 2,
1187 + FOE_STATE_FIN = 3
1188 +};
1189 +
1190 +
1191 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
1192 +#define MTK_RXD4_CPU_REASON GENMASK(18, 14)
1193 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
1194 +#define MTK_RXD4_ALG GENMASK(31, 22)
1195 +
1196 +enum mtk_foe_cpu_reason {
1197 + MTK_CPU_REASON_TTL_EXCEEDED = 0x02,
1198 + MTK_CPU_REASON_OPTION_HEADER = 0x03,
1199 + MTK_CPU_REASON_NO_FLOW = 0x07,
1200 + MTK_CPU_REASON_IPV4_FRAG = 0x08,
1201 + MTK_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
1202 + MTK_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
1203 + MTK_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
1204 + MTK_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
1205 + MTK_CPU_REASON_UN_HIT = 0x0d,
1206 + MTK_CPU_REASON_HIT_UNBIND = 0x0e,
1207 + MTK_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
1208 + MTK_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
1209 + MTK_CPU_REASON_HIT_TTL_1 = 0x11,
1210 + MTK_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
1211 + MTK_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
1212 + MTK_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
1213 + MTK_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
1214 + MTK_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
1215 + MTK_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
1216 + MTK_CPU_REASON_MULTICAST_TO_CPU = 0x18,
1217 + MTK_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
1218 + MTK_CPU_REASON_HIT_PRE_BIND = 0x1a,
1219 + MTK_CPU_REASON_PACKET_SAMPLING = 0x1b,
1220 + MTK_CPU_REASON_EXCEED_MTU = 0x1c,
1221 + MTK_CPU_REASON_PPE_BYPASS = 0x1e,
1222 + MTK_CPU_REASON_INVALID = 0x1f,
1223 +};
1224 +
1225 +
1226 +/* our table size is 4K */
1227 +#define MTK_PPE_ENTRY_CNT 0x4000
1228 +#define MTK_PPE_TBL_SZ \
1229 + (MTK_PPE_ENTRY_CNT * sizeof(struct mtk_foe_entry))
1230 +
1231 +int mtk_ppe_debugfs_init(struct mtk_eth *eth);
1232 +
1233 +
1234 +
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