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[openwrt/svn-archive/archive.git] / target / linux / mpc83xx / patches-3.3 / 200-powerpc-add-rbppc-support.patch
1 --- a/arch/powerpc/boot/Makefile
2 +++ b/arch/powerpc/boot/Makefile
3 @@ -76,7 +76,7 @@ src-plat := of.c cuboot-52xx.c cuboot-82
4 cuboot-pq2.c cuboot-sequoia.c treeboot-walnut.c \
5 cuboot-bamboo.c cuboot-mpc7448hpc2.c cuboot-taishan.c \
6 fixed-head.S ep88xc.c ep405.c cuboot-c2k.c \
7 - cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c \
8 + cuboot-katmai.c cuboot-rainier.c redboot-8xx.c ep8248e.c rb600.c rb333.c \
9 cuboot-warp.c cuboot-85xx-cpm2.c cuboot-yosemite.c simpleboot.c \
10 virtex405-head.S virtex.c redboot-83xx.c cuboot-sam440ep.c \
11 cuboot-acadia.c cuboot-amigaone.c cuboot-kilauea.c \
12 @@ -242,6 +242,8 @@ image-$(CONFIG_MPC834x_ITX) += cuImage.
13 image-$(CONFIG_MPC834x_MDS) += cuImage.mpc834x_mds
14 image-$(CONFIG_MPC836x_MDS) += cuImage.mpc836x_mds
15 image-$(CONFIG_ASP834x) += dtbImage.asp834x-redboot
16 +image-$(CONFIG_RB_PPC) += dtbImage.rb600 \
17 + dtbImage.rb333
18
19 # Board ports in arch/powerpc/platform/85xx/Kconfig
20 image-$(CONFIG_MPC8540_ADS) += cuImage.mpc8540ads
21 --- /dev/null
22 +++ b/arch/powerpc/boot/dts/rb600.dts
23 @@ -0,0 +1,283 @@
24 +/*
25 + * RouterBOARD 600 series Device Tree Source
26 + *
27 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
28 + *
29 + * This program is free software; you can redistribute it and/or modify it
30 + * under the terms of the GNU General Public License as published by the
31 + * Free Software Foundation; either version 2 of the License, or (at your
32 + * option) any later version.
33 + */
34 +
35 +/dts-v1/;
36 +
37 +/ {
38 + model = "RB600";
39 + compatible = "MPC83xx";
40 + #address-cells = <1>;
41 + #size-cells = <1>;
42 +
43 + aliases {
44 + ethernet0 = &enet0;
45 + ethernet1 = &enet1;
46 + pci0 = &pci0;
47 + };
48 +
49 + chosen {
50 + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
51 + linux,stdout-path = "/soc8343@e0000000/serial@4500";
52 + };
53 +
54 + cpus {
55 + #address-cells = <1>;
56 + #size-cells = <0>;
57 +
58 + PowerPC,8343E@0 {
59 + device_type = "cpu";
60 + reg = <0x0>;
61 + d-cache-line-size = <0x20>;
62 + i-cache-line-size = <0x20>;
63 + d-cache-size = <0x8000>;
64 + i-cache-size = <0x8000>;
65 + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
66 + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
67 + };
68 + };
69 +
70 + memory {
71 + device_type = "memory";
72 + reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
73 + };
74 +
75 + cf@f9200000 {
76 + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
77 + interrupt-at-level = <0x0>;
78 + interrupt-parent = <&ipic>;
79 + interrupts = <0x16 0x8>;
80 + lbc_extra_divider = <0x1>;
81 + reg = <0xf9200000 0x200000>;
82 + device_type = "rb,cf";
83 + };
84 +
85 + cf@f9000000 {
86 + lb-timings = <0x5dc 0x3e8 0x1194 0x5dc 0x2af8>;
87 + interrupt-at-level = <0x0>;
88 + interrupt-parent = <&ipic>;
89 + interrupts = <0x14 0x8>;
90 + lbc_extra_divider = <0x1>;
91 + reg = <0xf9000000 0x200000>;
92 + device_type = "rb,cf";
93 + };
94 +
95 + flash {
96 + reg = <0xff800000 0x20000>;
97 + };
98 +
99 + nnand {
100 + reg = <0xf0000000 0x1000>;
101 + };
102 +
103 + nand {
104 + ale = <&gpio 0x6>;
105 + cle = <&gpio 0x5>;
106 + nce = <&gpio 0x4>;
107 + rdy = <&gpio 0x3>;
108 + reg = <0xf8000000 0x1000>;
109 + device_type = "rb,nand";
110 + };
111 +
112 + fancon {
113 + interrupt-parent = <&ipic>;
114 + interrupts = <0x17 0x8>;
115 + sense = <&gpio 0x7>;
116 + fan_on = <&gpio 0x9>;
117 + };
118 +
119 + pci0: pci@e0008500 {
120 + device_type = "pci";
121 + compatible = "fsl,mpc8349-pci";
122 + reg = <0xe0008500 0x100 0xe0008300 0x8>;
123 + #address-cells = <3>;
124 + #size-cells = <2>;
125 + #interrupt-cells = <1>;
126 + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
127 + bus-range = <0x0 0x0>;
128 + interrupt-map = <
129 + 0x5800 0x0 0x0 0x1 &ipic 0x15 0x8
130 + 0x6000 0x0 0x0 0x1 &ipic 0x30 0x8
131 + 0x6000 0x0 0x0 0x2 &ipic 0x11 0x8
132 + 0x6800 0x0 0x0 0x1 &ipic 0x11 0x8
133 + 0x6800 0x0 0x0 0x2 &ipic 0x12 0x8
134 + 0x7000 0x0 0x0 0x1 &ipic 0x12 0x8
135 + 0x7000 0x0 0x0 0x2 &ipic 0x13 0x8
136 + 0x7800 0x0 0x0 0x1 &ipic 0x13 0x8
137 + 0x7800 0x0 0x0 0x2 &ipic 0x30 0x8
138 + 0x8000 0x0 0x0 0x1 &ipic 0x30 0x8
139 + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
140 + 0x8000 0x0 0x0 0x3 &ipic 0x11 0x8
141 + 0x8000 0x0 0x0 0x4 &ipic 0x13 0x8
142 + 0xa000 0x0 0x0 0x1 &ipic 0x30 0x8
143 + 0xa000 0x0 0x0 0x2 &ipic 0x11 0x8
144 + 0xa000 0x0 0x0 0x3 &ipic 0x12 0x8
145 + 0xa000 0x0 0x0 0x4 &ipic 0x13 0x8
146 + 0xa800 0x0 0x0 0x1 &ipic 0x11 0x8
147 + 0xa800 0x0 0x0 0x2 &ipic 0x12 0x8
148 + 0xa800 0x0 0x0 0x3 &ipic 0x13 0x8
149 + 0xa800 0x0 0x0 0x4 &ipic 0x30 0x8>;
150 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
151 + interrupt-parent = <&ipic>;
152 + };
153 +
154 + soc8343@e0000000 {
155 + #address-cells = <1>;
156 + #size-cells = <1>;
157 + device_type = "soc";
158 + compatible = "simple-bus";
159 + ranges = <0x0 0xe0000000 0x100000>;
160 + reg = <0xe0000000 0x200>;
161 + bus-frequency = <0x1>;
162 +
163 + led {
164 + user_led = <0x400 0x8>;
165 + };
166 +
167 + beeper {
168 + reg = <0x500 0x100>;
169 + };
170 +
171 + gpio: gpio@0 {
172 + reg = <0xc08 0x4>;
173 + device-id = <0x0>;
174 + compatible = "gpio";
175 + device_type = "gpio";
176 + };
177 +
178 + dma@82a8 {
179 + #address-cells = <1>;
180 + #size-cells = <1>;
181 + compatible = "fsl,mpc8349-dma", "fsl,elo-dma";
182 + reg = <0x82a8 4>;
183 + ranges = <0 0x8100 0x1a8>;
184 + interrupt-parent = <&ipic>;
185 + interrupts = <71 8>;
186 + cell-index = <0>;
187 + dma-channel@0 {
188 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
189 + reg = <0 0x80>;
190 + cell-index = <0>;
191 + interrupt-parent = <&ipic>;
192 + interrupts = <71 8>;
193 + };
194 + dma-channel@80 {
195 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
196 + reg = <0x80 0x80>;
197 + cell-index = <1>;
198 + interrupt-parent = <&ipic>;
199 + interrupts = <71 8>;
200 + };
201 + dma-channel@100 {
202 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
203 + reg = <0x100 0x80>;
204 + cell-index = <2>;
205 + interrupt-parent = <&ipic>;
206 + interrupts = <71 8>;
207 + };
208 + dma-channel@180 {
209 + compatible = "fsl,mpc8349-dma-channel", "fsl,elo-dma-channel";
210 + reg = <0x180 0x28>;
211 + cell-index = <3>;
212 + interrupt-parent = <&ipic>;
213 + interrupts = <71 8>;
214 + };
215 + };
216 +
217 + enet0: ethernet@25000 {
218 + #address-cells = <1>;
219 + #size-cells = <1>;
220 + cell-index = <0>;
221 + phy-handle = <&phy0>;
222 + tbi-handle = <&tbi0>;
223 + interrupt-parent = <&ipic>;
224 + interrupts = <0x23 0x8 0x24 0x8 0x25 0x8>;
225 + local-mac-address = [00 00 00 00 00 00];
226 + reg = <0x25000 0x1000>;
227 + ranges = <0x0 0x25000 0x1000>;
228 + compatible = "gianfar";
229 + model = "TSEC";
230 + device_type = "network";
231 +
232 + mdio@520 {
233 + #address-cells = <1>;
234 + #size-cells = <0>;
235 + compatible = "fsl,gianfar-tbi";
236 + reg = <0x520 0x20>;
237 +
238 + tbi0: tbi-phy@11 {
239 + reg = <0x11>;
240 + device_type = "tbi-phy";
241 + };
242 + };
243 + };
244 +
245 + enet1: ethernet@24000 {
246 + #address-cells = <1>;
247 + #size-cells = <1>;
248 + cell-index = <1>;
249 + phy-handle = <&phy1>;
250 + tbi-handle = <&tbi1>;
251 + interrupt-parent = <&ipic>;
252 + interrupts = <0x20 0x8 0x21 0x8 0x22 0x8>;
253 + local-mac-address = [00 00 00 00 00 00];
254 + reg = <0x24000 0x1000>;
255 + ranges = <0x0 0x24000 0x1000>;
256 + compatible = "gianfar";
257 + model = "TSEC";
258 + device_type = "network";
259 +
260 + mdio@520 {
261 + #size-cells = <0x0>;
262 + #address-cells = <0x1>;
263 + reg = <0x520 0x20>;
264 + compatible = "fsl,gianfar-mdio";
265 +
266 + phy0: ethernet-phy@0 {
267 + device_type = "ethernet-phy";
268 + reg = <0x0>;
269 + };
270 +
271 + phy1: ethernet-phy@1 {
272 + device_type = "ethernet-phy";
273 + reg = <0x1>;
274 + };
275 +
276 + tbi1: tbi-phy@11 {
277 + reg = <0x11>;
278 + device_type = "tbi-phy";
279 + };
280 + };
281 + };
282 +
283 + ipic: pic@700 {
284 + interrupt-controller;
285 + #address-cells = <0>;
286 + #interrupt-cells = <2>;
287 + reg = <0x700 0x100>;
288 + device_type = "ipic";
289 + };
290 +
291 + serial@4500 {
292 + interrupt-parent = <&ipic>;
293 + interrupts = <0x9 0x8>;
294 + clock-frequency = <0xfe4f840>;
295 + reg = <0x4500 0x100>;
296 + compatible = "ns16550";
297 + device_type = "serial";
298 + };
299 +
300 + wdt@200 {
301 + reg = <0x200 0x100>;
302 + compatible = "mpc83xx_wdt";
303 + device_type = "watchdog";
304 + };
305 + };
306 +};
307 --- /dev/null
308 +++ b/arch/powerpc/boot/rb600.c
309 @@ -0,0 +1,70 @@
310 +/*
311 + * The RouterBOARD platform -- for booting RB600(A) RouterBOARDs.
312 + *
313 + * Author: Michael Guntsche <mike@it-loops.com>
314 + *
315 + * Copyright (c) 2009 Michael Guntsche
316 + *
317 + * This program is free software; you can redistribute it and/or modify it
318 + * under the terms of the GNU General Public License version 2 as published
319 + * by the Free Software Foundation.
320 + */
321 +
322 +#include "ops.h"
323 +#include "types.h"
324 +#include "io.h"
325 +#include "stdio.h"
326 +#include <libfdt.h>
327 +
328 +BSS_STACK(4*1024);
329 +
330 +u64 memsize64;
331 +const void *fw_dtb;
332 +
333 +static void rb600_fixups(void)
334 +{
335 + const u32 *reg, *timebase, *clock;
336 + int node, size;
337 +
338 + dt_fixup_memory(0, memsize64);
339 +
340 + /* Set the MAC addresses. */
341 + node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@24000");
342 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
343 + dt_fixup_mac_address_by_alias("ethernet1", (const u8 *)reg);
344 +
345 + node = fdt_path_offset(fw_dtb, "/soc8343@e0000000/ethernet@25000");
346 + reg = fdt_getprop(fw_dtb, node, "mac-address", &size);
347 + dt_fixup_mac_address_by_alias("ethernet0", (const u8 *)reg);
348 +
349 + /* Find the CPU timebase and clock frequencies. */
350 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
351 + timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
352 + clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
353 + dt_fixup_cpu_clocks(*clock, *timebase, 0);
354 +
355 +}
356 +
357 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
358 + unsigned long r6, unsigned long r7)
359 +{
360 + const u32 *reg;
361 + int node, size;
362 +
363 + fw_dtb = (const void *)r3;
364 +
365 + /* Find the memory range. */
366 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
367 + reg = fdt_getprop(fw_dtb, node, "reg", &size);
368 + memsize64 = reg[1];
369 +
370 + /* Now we have the memory size; initialize the heap. */
371 + simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
372 +
373 + /* Prepare the device tree and find the console. */
374 + fdt_init(_dtb_start);
375 + serial_console_init();
376 +
377 + /* Remaining fixups... */
378 + platform_ops.fixups = rb600_fixups;
379 +}
380 --- a/arch/powerpc/boot/wrapper
381 +++ b/arch/powerpc/boot/wrapper
382 @@ -215,7 +215,7 @@ ps3)
383 link_address=''
384 pie=
385 ;;
386 -ep88xc|ep405|ep8248e)
387 +ep88xc|ep405|ep8248e|rb600|rb333)
388 platformo="$object/fixed-head.o $object/$platform.o"
389 binary=y
390 ;;
391 --- a/arch/powerpc/platforms/83xx/Kconfig
392 +++ b/arch/powerpc/platforms/83xx/Kconfig
393 @@ -38,6 +38,15 @@ config MPC832x_RDB
394 help
395 This option enables support for the MPC8323 RDB board.
396
397 +config RB_PPC
398 + bool "MikroTik RouterBOARD 333/600 series"
399 + select DEFAULT_UIMAGE
400 + select QUICC_ENGINE
401 + select PPC_MPC832x
402 + select PPC_MPC834x
403 + help
404 + This option enables support for MikroTik RouterBOARD 333/600 series boards.
405 +
406 config MPC834x_MDS
407 bool "Freescale MPC834x MDS"
408 select DEFAULT_UIMAGE
409 --- /dev/null
410 +++ b/arch/powerpc/boot/dts/rb333.dts
411 @@ -0,0 +1,432 @@
412 +
413 +/*
414 + * RouterBOARD 333 series Device Tree Source
415 + *
416 + * Copyright 2010 Alexandros C. Couloumbis <alex@ozo.com>
417 + * Copyright 2009 Michael Guntsche <mike@it-loops.com>
418 + *
419 + * This program is free software; you can redistribute it and/or modify it
420 + * under the terms of the GNU General Public License as published by the
421 + * Free Software Foundation; either version 2 of the License, or (at your
422 + * option) any later version.
423 + *
424 + * Warning (reg_format): "reg" property in /qe@e0100000/muram@10000/data-only@0 has invalid length (8 bytes) (#address-cells == 2, #size-cells == 1)
425 + * Warning (ranges_format): "ranges" property in /qe@e0100000/muram@10000 has invalid length (12 bytes) (parent #address-cells == 1, child #address-cells == 2, #size-cells == 1)
426 + * Warning (avoid_default_addr_size): Relying on default #address-cells value for /qe@e0100000/muram@10000/data-only@0
427 + * Warning (avoid_default_addr_size): Relying on default #size-cells value for /qe@e0100000/muram@10000/data-only@0
428 + * Warning (obsolete_chosen_interrupt_controller): /chosen has obsolete "interrupt-controller" property
429 + *
430 + */
431 +
432 +
433 +/dts-v1/;
434 +
435 +/ {
436 + model = "RB333";
437 + compatible = "MPC83xx";
438 + #size-cells = <1>;
439 + #address-cells = <1>;
440 +
441 +
442 + aliases {
443 + ethernet0 = &enet0;
444 + ethernet1 = &enet1;
445 + ethernet2 = &enet2;
446 + pci0 = &pci0;
447 + };
448 +
449 +
450 + chosen {
451 + bootargs = "console=ttyS0,115200 board=mpc8323 rootfstype=squashfs,yaffs2,jffs2 root=/dev/mtdblock1 boot=1";
452 + // linux,platform = <0x8062>;
453 + // linux,initrd = <0x488000 0x0>;
454 + linux,stdout-path = "/soc8323@e0000000/serial@4500";
455 + // interrupt-controller = <&ipic>;
456 + };
457 +
458 + cpus {
459 + #cpus = <1>;
460 + #size-cells = <0>;
461 + #address-cells = <1>;
462 +
463 + PowerPC,8323E@0 {
464 + device_type = "cpu";
465 + reg = <0x0>;
466 + i-cache-size = <0x4000>;
467 + d-cache-size = <0x4000>;
468 + i-cache-line-size = <0x20>;
469 + d-cache-line-size = <0x20>;
470 + // clock-frequency = <0x13de3650>;
471 + // timebase-frequency = <0x1fc9f08>;
472 + timebase-frequency = <0x0000000>; // filled by the bootwrapper from the firmware blob
473 + clock-frequency = <0x00000000>; // filled by the bootwrapper from the firmware blob
474 + 32-bit;
475 + };
476 + };
477 +
478 + memory {
479 + device_type = "memory";
480 + reg = <0x0 0x4000000>;
481 + // reg = <0x0 0x0000000>; // filled by the bootwrapper from the firmware blob
482 + };
483 +
484 + flash {
485 + reg = <0xfe000000 0x20000>;
486 + };
487 +
488 + nand {
489 + ale = <&gpio2 0x3>;
490 + cle = <&gpio2 0x2>;
491 + nce = <&gpio2 0x1>;
492 + rdy = <&gpio2 0x0>;
493 + reg = <0xf8000000 0x1000>;
494 + device_type = "rb,nand";
495 + };
496 +
497 + nnand {
498 + reg = <0xf0000000 0x1000>;
499 + };
500 +
501 + voltage {
502 + voltage_gpio = <&gpio3 0x11>;
503 + };
504 +
505 + fancon {
506 + interrupt-parent = <&ipic>;
507 + interrupts = <0x14 0x8>;
508 + fan_on = <&gpio0 0x10>;
509 + };
510 +
511 + pci0: pci@e0008500 {
512 + device_type = "pci";
513 + // compatible = "83xx";
514 + compatible = "fsl,mpc8349-pci";
515 + reg = <0xe0008500 0x100 0xe0008300 0x8>;
516 + #address-cells = <3>;
517 + #size-cells = <2>;
518 + #interrupt-cells = <1>;
519 + // clock-frequency = <0>;
520 + ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000 0x1000000 0x0 0x0 0xd0000000 0x0 0x4000000>;
521 + bus-range = <0x0 0x0>;
522 + interrupt-map = <
523 + /* IDSEL 0x10 AD16 miniPCI slot 0 */
524 + 0x8000 0x0 0x0 0x1 &ipic 0x11 0x8
525 + 0x8000 0x0 0x0 0x2 &ipic 0x12 0x8
526 +
527 + /* IDSEL 0x11 AD17 miniPCI slot 1 */
528 + 0x8800 0x0 0x0 0x1 &ipic 0x12 0x8
529 + 0x8800 0x0 0x0 0x2 &ipic 0x13 0x8
530 +
531 + /* IDSEL 0x12 AD18 miniPCI slot 2 */
532 + 0x9000 0x0 0x0 0x1 &ipic 0x13 0x8
533 + 0x9000 0x0 0x0 0x2 &ipic 0x11 0x8>;
534 +
535 + interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
536 + interrupt-parent = <&ipic>;
537 + // interrupts = <66 0x8>;
538 + };
539 +
540 +
541 + qe@e0100000 {
542 + reg = <0xe0100000 0x480>;
543 + ranges = <0x0 0xe0100000 0x100000>;
544 + model = "QE";
545 + device_type = "qe";
546 + compatible = "fsl,qe";
547 + #size-cells = <1>;
548 + #address-cells = <1>;
549 + brg-frequency = <0>;
550 + bus-frequency = <0>;
551 + // bus-frequency = <198000000>;
552 + fsl,qe-num-riscs = <1>;
553 + fsl,qe-num-snums = <28>;
554 +
555 + qeic: qeic@80 {
556 + interrupt-controller;
557 + compatible = "fsl,qe-ic";
558 + big-endian;
559 + built-in;
560 + reg = <0x80 0x80>;
561 + #interrupt-cells = <1>;
562 + #address-cells = <0>;
563 + device_type = "qeic";
564 + interrupts = <0x20 0x8 0x21 0x8>;
565 + interrupt-parent = <&ipic>;
566 + };
567 +
568 + mdio@2120 {
569 + compatible = "ucc_geth_phy";
570 + device_type = "mdio";
571 + reg = <0x3120 0x18>;
572 + #size-cells = <0>;
573 + #address-cells = <1>;
574 +
575 + phy3: ethernet-phy@03 {
576 + // interface = <0x3>;
577 + device_type = "ethernet-phy";
578 + reg = <0x3>;
579 + };
580 +
581 + phy2: ethernet-phy@02 {
582 + // interface = <0x3>;
583 + device_type = "ethernet-phy";
584 + reg = <0x2>;
585 + };
586 +
587 + phy1: ethernet-phy@01 {
588 + // interface = <0x3>;
589 + device_type = "ethernet-phy";
590 + reg = <0x1>;
591 + };
592 + };
593 +
594 + enet0: ucc@2200 {
595 + tx-clock = <0x1a>;
596 + rx-clock = <0x1f>;
597 + mac-address = [00 0c 42 1c 29 d2];
598 + interrupt-parent = <&qeic>;
599 + interrupts = <0x22>;
600 + reg = <0x2200 0x200>;
601 + device-id = <0x3>;
602 + model = "UCC";
603 + compatible = "ucc_geth";
604 + device_type = "network";
605 + phy-handle = <&phy2>;
606 + pio-handle = <&pio3>;
607 + };
608 +
609 + enet1: ucc@3200 {
610 + tx-clock = <0x22>;
611 + rx-clock = <0x20>;
612 + mac-address = [00 0c 42 1c 29 d1];
613 + interrupt-parent = <&qeic>;
614 + interrupts = <0x23>;
615 + reg = <0x3200 0x200>;
616 + device-id = <0x4>;
617 + model = "UCC";
618 + compatible = "ucc_geth";
619 + device_type = "network";
620 + phy-handle = <&phy3>;
621 + pio-handle = <&pio4>;
622 + };
623 +
624 + enet2: ucc@3000 {
625 + tx-clock = <0x18>;
626 + rx-clock = <0x17>;
627 + mac-address = [00 0c 42 1c 29 d0];
628 + interrupt-parent = <&qeic>;
629 + interrupts = <0x21>;
630 + reg = <0x3000 0x200>;
631 + device-id = <0x2>;
632 + model = "UCC";
633 + compatible = "ucc_geth";
634 + device_type = "network";
635 + phy-handle = <&phy1>;
636 + pio-handle = <&pio2>;
637 + };
638 +
639 + spi@500 {
640 + mode = "cpu";
641 + interrupt-parent = <&qeic>;
642 + interrupts = <0x1>;
643 + reg = <0x500 0x40>;
644 + compatible = "fsl,spi";
645 + device_type = "spi";
646 + };
647 +
648 + spi@4c0 {
649 + mode = "cpu";
650 + interrupt-parent = <&qeic>;
651 + interrupts = <0x2>;
652 + reg = <0x4c0 0x40>;
653 + compatible = "fsl,spi";
654 + device_type = "spi";
655 + };
656 +
657 + muram@10000 {
658 + #address-cells = <1>;
659 + #size-cells = <1>;
660 + compatible = "fsl,qe-muram", "fsl,cpm-muram";
661 + ranges = <0x0 0x10000 0x4000>;
662 + device_type = "muram";
663 +
664 + data-only@0 {
665 + compatible = "fsl,qe-muram-data",
666 + "fsl,cpm-muram-data";
667 + reg = <0x0 0x4000>;
668 + };
669 + };
670 + };
671 +
672 +
673 + soc8323@e0000000 {
674 + bus-frequency = <0x1>;
675 + reg = <0xe0000000 0x200>;
676 + ranges = <0x0 0xe0000000 0x100000>;
677 + device_type = "soc";
678 + compatible = "simple-bus";
679 + #interrupt-cells = <0x2>;
680 + #size-cells = <1>;
681 + #address-cells = <1>;
682 +
683 + beeper {
684 + gpio = <&gpio3 0x12>;
685 + reg = <0x500 0x100>;
686 + interrupt-parent = <&ipic>;
687 + interrupts = <0x48 0x8>;
688 + };
689 +
690 + gpio3: gpio@3 {
691 + reg = <0x144c 0x4>;
692 + device-id = <0x3>;
693 + compatible = "qe_gpio";
694 + device_type = "gpio";
695 + };
696 +
697 + gpio2: gpio@2 {
698 + reg = <0x1434 0x4>;
699 + device-id = <0x2>;
700 + compatible = "qe_gpio";
701 + device_type = "gpio";
702 + };
703 +
704 + gpio0: gpio@0 {
705 + reg = <0x1404 0x4>;
706 + device-id = <0x0>;
707 + compatible = "qe_gpio";
708 + device_type = "gpio";
709 + };
710 +
711 + par_io@1400 {
712 + num-ports = <4>;
713 + device_type = "par_io";
714 + reg = <0x1400 0x100>;
715 +
716 + pio4: ucc_pin@04 {
717 + pio-map = <
718 + /* port pin dir open_drain assignment has_irq */
719 + 1 18 1 0 1 0
720 + 1 19 1 0 1 0
721 + 1 20 1 0 1 0
722 + 1 21 1 0 1 0
723 + 1 30 1 0 1 0
724 + 3 20 2 0 1 0
725 + 1 30 2 0 1 0
726 + 1 31 2 0 1 0
727 + 1 22 2 0 1 0
728 + 1 23 2 0 1 0
729 + 1 24 2 0 1 0
730 + 1 25 2 0 1 0
731 + 1 28 2 0 1 0
732 + 1 26 2 0 1 0
733 + 3 21 2 0 1 0>;
734 + };
735 +
736 + pio3: ucc_pin@03 {
737 + pio-map = <
738 + /* port pin dir open_drain assignment has_irq */
739 + 1 0 1 0 1 0
740 + 1 1 1 0 1 0
741 + 1 2 1 0 1 0
742 + 1 3 1 0 1 0
743 + 1 12 1 0 1 0
744 + 3 24 2 0 1 0
745 + 1 11 2 0 1 0
746 + 1 13 2 0 1 0
747 + 1 4 2 0 1 0
748 + 1 5 2 0 1 0
749 + 1 6 2 0 1 0
750 + 1 7 2 0 1 0
751 + 1 10 2 0 1 0
752 + 1 8 2 0 1 0
753 + 3 29 2 0 1 0>;
754 + };
755 +
756 + pio2: ucc_pin@02 {
757 + pio-map = <
758 + /* port pin dir open_drain assignment has_irq */
759 + 3 4 3 0 2 0
760 + 3 5 1 0 2 0
761 + 0 18 1 0 1 0
762 + 0 19 1 0 1 0
763 + 0 20 1 0 1 0
764 + 0 21 1 0 1 0
765 + 0 30 1 0 1 0
766 + 3 6 2 0 1 0
767 + 0 29 2 0 1 0
768 + 0 31 2 0 1 0
769 + 0 22 2 0 1 0
770 + 0 23 2 0 1 0
771 + 0 24 2 0 1 0
772 + 0 25 2 0 1 0
773 + 0 28 2 0 1 0
774 + 0 26 2 0 1 0
775 + 3 31 2 0 1 0>;
776 + };
777 + };
778 +
779 + ipic: pic@700 {
780 + device_type = "ipic";
781 + built-in;
782 + reg = <0x700 0x100>;
783 + #interrupt-cells = <0x2>;
784 + #address-cells = <0x0>;
785 + interrupt-controller;
786 + };
787 +
788 +
789 + serial@4500 {
790 + interrupt-parent = <&ipic>;
791 + interrupts = <0x9 0x8>;
792 + clock-frequency = <0x7f27c20>;
793 + reg = <0x4500 0x100>;
794 + compatible = "ns16550";
795 + device_type = "serial";
796 + };
797 +
798 + dma@82a8 {
799 + #address-cells = <1>;
800 + #size-cells = <1>;
801 + compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
802 + reg = <0x82a8 4>;
803 + ranges = <0 0x8100 0x1a8>;
804 + interrupt-parent = <&ipic>;
805 + interrupts = <71 8>;
806 + cell-index = <0>;
807 + dma-channel@0 {
808 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
809 + reg = <0 0x80>;
810 + cell-index = <0>;
811 + interrupt-parent = <&ipic>;
812 + interrupts = <71 8>;
813 + };
814 + dma-channel@80 {
815 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
816 + reg = <0x80 0x80>;
817 + cell-index = <1>;
818 + interrupt-parent = <&ipic>;
819 + interrupts = <71 8>;
820 + };
821 + dma-channel@100 {
822 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
823 + reg = <0x100 0x80>;
824 + cell-index = <2>;
825 + interrupt-parent = <&ipic>;
826 + interrupts = <71 8>;
827 + };
828 + dma-channel@180 {
829 + compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
830 + reg = <0x180 0x28>;
831 + cell-index = <3>;
832 + interrupt-parent = <&ipic>;
833 + interrupts = <71 8>;
834 + };
835 + };
836 +
837 + wdt@200 {
838 + reg = <0x200 0x100>;
839 + compatible = "mpc83xx_wdt";
840 + device_type = "watchdog";
841 + };
842 + };
843 +};
844 --- /dev/null
845 +++ b/arch/powerpc/boot/rb333.c
846 @@ -0,0 +1,73 @@
847 +/*
848 + * The RouterBOARD platform -- for booting RB333 RouterBOARDs.
849 + *
850 + * Author: Alexandros C. Couloumbis <alex@ozo.com>
851 + * Author: Michael Guntsche <mike@it-loops.com>
852 + *
853 + * Copyright (c) 2010 Alexandros C. Couloumbis
854 + * Copyright (c) 2009 Michael Guntsche
855 + *
856 + * This program is free software; you can redistribute it and/or modify it
857 + * under the terms of the GNU General Public License version 2 as published
858 + * by the Free Software Foundation.
859 + */
860 +
861 +#include "ops.h"
862 +#include "types.h"
863 +#include "io.h"
864 +#include "stdio.h"
865 +#include <libfdt.h>
866 +
867 +BSS_STACK(4*1024);
868 +
869 +u64 memsize64;
870 +const void *fw_dtb;
871 +
872 +static void rb333_fixups(void)
873 +{
874 + const u32 *timebase, *clock;
875 + int node, size;
876 + void *chosen;
877 + const char* bootargs;
878 +
879 + dt_fixup_memory(0, memsize64);
880 +
881 + /* Find the CPU timebase and clock frequencies. */
882 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "cpu", sizeof("cpu"));
883 + timebase = fdt_getprop(fw_dtb, node, "timebase-frequency", &size);
884 + clock = fdt_getprop(fw_dtb, node, "clock-frequency", &size);
885 + dt_fixup_cpu_clocks(*clock, *timebase, 0);
886 +
887 + /* Fixup chosen
888 + * The bootloader reads the kernelparm segment and adds the content to
889 + * bootargs. This is needed to specify root and other boot flags.
890 + */
891 + chosen = finddevice("/chosen");
892 + node = fdt_path_offset(fw_dtb, "/chosen");
893 + bootargs = fdt_getprop(fw_dtb, node, "bootargs", &size);
894 + setprop_str(chosen, "bootargs", bootargs);
895 +}
896 +
897 +void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
898 + unsigned long r6, unsigned long r7)
899 +{
900 + const u32 *reg;
901 + int node, size;
902 +
903 + fw_dtb = (const void *)r3;
904 +
905 + /* Find the memory range. */
906 + node = fdt_node_offset_by_prop_value(fw_dtb, -1, "device_type", "memory", sizeof("memory"));
907 + reg = fdt_getprop(fw_dtb, node, "reg", &size);
908 + memsize64 = reg[1];
909 +
910 + /* Now we have the memory size; initialize the heap. */
911 + simple_alloc_init(_end, memsize64 - (unsigned long)_end, 32, 64);
912 +
913 + /* Prepare the device tree and find the console. */
914 + fdt_init(_dtb_start);
915 + serial_console_init();
916 +
917 + /* Remaining fixups... */
918 + platform_ops.fixups = rb333_fixups;
919 +}
920 --- /dev/null
921 +++ b/arch/powerpc/platforms/83xx/rbppc.c
922 @@ -0,0 +1,388 @@
923 +/*
924 + * Copyright (C) 2010 Alexandros C. Couloumbis <alex@ozo.com>
925 + * Copyright (C) 2008-2009 Noah Fontes <nfontes@transtruct.org>
926 + * Copyright (C) 2009 Michael Guntsche <mike@it-loops.com>
927 + * Copyright (C) Mikrotik 2007
928 + *
929 + * This program is free software; you can redistribute it and/or modify it
930 + * under the terms of the GNU General Public License as published by the
931 + * Free Software Foundation; either version 2 of the License, or (at your
932 + * option) any later version.
933 + */
934 +
935 +#include <linux/delay.h>
936 +#include <linux/root_dev.h>
937 +#include <linux/initrd.h>
938 +#include <linux/interrupt.h>
939 +#include <linux/of_platform.h>
940 +#include <linux/of_device.h>
941 +#include <linux/of_platform.h>
942 +#include <linux/pci.h>
943 +#include <asm/time.h>
944 +#include <asm/ipic.h>
945 +#include <asm/udbg.h>
946 +#include <asm/qe.h>
947 +#include <asm/qe_ic.h>
948 +#include <sysdev/fsl_soc.h>
949 +#include <sysdev/fsl_pci.h>
950 +#include "mpc83xx.h"
951 +
952 +#define SYSCTL 0x100
953 +#define SICRL 0x014
954 +
955 +#define GTCFR2 0x04
956 +#define GTMDR4 0x22
957 +#define GTRFR4 0x26
958 +#define GTCNR4 0x2e
959 +#define GTVER4 0x36
960 +#define GTPSR4 0x3e
961 +
962 +#define GTCFR_BCM 0x40
963 +#define GTCFR_STP4 0x20
964 +#define GTCFR_RST4 0x10
965 +#define GTCFR_STP3 0x02
966 +#define GTCFR_RST3 0x01
967 +
968 +#define GTMDR_ORI 0x10
969 +#define GTMDR_FRR 0x08
970 +#define GTMDR_ICLK16 0x04
971 +
972 +extern int par_io_data_set(u8 port, u8 pin, u8 val);
973 +extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
974 + int assignment, int has_irq);
975 +
976 +static unsigned timer_freq;
977 +static void *gtm;
978 +
979 +static int beeper_irq;
980 +static unsigned beeper_gpio_pin[2];
981 +
982 +int rb333model = 0;
983 +
984 +irqreturn_t rbppc_timer_irq(int irq, void *ptr)
985 +{
986 + static int toggle = 0;
987 +
988 + par_io_data_set(beeper_gpio_pin[0], beeper_gpio_pin[1], toggle);
989 + toggle = !toggle;
990 +
991 + /* ack interrupt */
992 + out_be16(gtm + GTVER4, 3);
993 +
994 + return IRQ_HANDLED;
995 +}
996 +
997 +void rbppc_beep(unsigned freq)
998 +{
999 + unsigned gtmdr;
1000 +
1001 + if (freq > 5000) freq = 5000;
1002 +
1003 + if (!gtm)
1004 + return;
1005 + if (!freq) {
1006 + out_8(gtm + GTCFR2, GTCFR_STP4 | GTCFR_STP3);
1007 + return;
1008 + }
1009 +
1010 + out_8(gtm + GTCFR2, GTCFR_RST4 | GTCFR_STP3);
1011 + out_be16(gtm + GTPSR4, 255);
1012 + gtmdr = GTMDR_FRR | GTMDR_ICLK16;
1013 + if (beeper_irq != NO_IRQ) gtmdr |= GTMDR_ORI;
1014 + out_be16(gtm + GTMDR4, gtmdr);
1015 + out_be16(gtm + GTVER4, 3);
1016 +
1017 + out_be16(gtm + GTRFR4, timer_freq / 16 / 256 / freq / 2);
1018 + out_be16(gtm + GTCNR4, 0);
1019 +}
1020 +EXPORT_SYMBOL(rbppc_beep);
1021 +
1022 +static void __init rbppc_setup_arch(void)
1023 +{
1024 + struct device_node *np;
1025 +
1026 + np = of_find_node_by_type(NULL, "cpu");
1027 + if (np) {
1028 + const unsigned *fp = of_get_property(np, "clock-frequency", NULL);
1029 + loops_per_jiffy = fp ? *fp / HZ : 0;
1030 +
1031 + of_node_put(np);
1032 + }
1033 +
1034 + np = of_find_node_by_name(NULL, "serial");
1035 + if (np) {
1036 + timer_freq =
1037 + *(unsigned *) of_get_property(np, "clock-frequency", NULL);
1038 + of_node_put(np);
1039 + }
1040 +
1041 +#ifdef CONFIG_PCI
1042 + np = of_find_node_by_type(NULL, "pci");
1043 + if (np) {
1044 + mpc83xx_add_bridge(np);
1045 + }
1046 +#endif
1047 +
1048 +if (rb333model) {
1049 +
1050 +#ifdef CONFIG_QUICC_ENGINE
1051 + qe_reset();
1052 +
1053 + if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
1054 + par_io_init(np);
1055 + of_node_put(np);
1056 +
1057 + for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
1058 + par_io_of_config(np);
1059 + }
1060 +#endif
1061 +
1062 +} /* RB333 */
1063 +
1064 +}
1065 +
1066 +void __init rbppc_init_IRQ(void)
1067 +{
1068 + struct device_node *np;
1069 +
1070 + np = of_find_node_by_type(NULL, "ipic");
1071 + if (np) {
1072 + ipic_init(np, 0);
1073 + ipic_set_default_priority();
1074 + of_node_put(np);
1075 + }
1076 +
1077 +if (rb333model) {
1078 +
1079 +#ifdef CONFIG_QUICC_ENGINE
1080 + np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
1081 + if (!np) {
1082 + np = of_find_node_by_type(NULL, "qeic");
1083 + if (!np)
1084 + return;
1085 + }
1086 + qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
1087 + of_node_put(np);
1088 +#endif /* CONFIG_QUICC_ENGINE */
1089 +
1090 +} /* RB333 */
1091 +
1092 +}
1093 +
1094 +static int __init rbppc_probe(void)
1095 +{
1096 + char *model;
1097 +
1098 + model = of_get_flat_dt_prop(of_get_flat_dt_root(), "model", NULL);
1099 +
1100 + if (!model)
1101 + return 0;
1102 +
1103 + if (strcmp(model, "RB333") == 0) {
1104 + rb333model = 1;
1105 + return 1;
1106 + }
1107 +
1108 + if (strcmp(model, "RB600") == 0)
1109 + return 1;
1110 +
1111 + return 0;
1112 +}
1113 +
1114 +static void __init rbppc_beeper_init(struct device_node *beeper)
1115 +{
1116 + struct resource res;
1117 + struct device_node *gpio;
1118 + const unsigned *pin;
1119 + const unsigned *gpio_id;
1120 +
1121 + if (of_address_to_resource(beeper, 0, &res)) {
1122 + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No region specified\n", beeper->full_name);
1123 + return;
1124 + }
1125 +
1126 + pin = of_get_property(beeper, "gpio", NULL);
1127 + if (pin) {
1128 + gpio = of_find_node_by_phandle(pin[0]);
1129 +
1130 + if (!gpio) {
1131 + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: GPIO handle %x not found\n", beeper->full_name, pin[0]);
1132 + return;
1133 + }
1134 +
1135 + gpio_id = of_get_property(gpio, "device-id", NULL);
1136 + if (!gpio_id) {
1137 + printk(KERN_ERR "rbppc_beeper_init(%s): Beeper error: No device-id specified in GPIO\n", beeper->full_name);
1138 + return;
1139 + }
1140 +
1141 + beeper_gpio_pin[0] = *gpio_id;
1142 + beeper_gpio_pin[1] = pin[1];
1143 +
1144 + par_io_config_pin(*gpio_id, pin[1], 1, 0, 0, 0);
1145 + } else {
1146 + void *sysctl;
1147 +
1148 + sysctl = ioremap_nocache(get_immrbase() + SYSCTL, 0x100);
1149 + out_be32(sysctl + SICRL,
1150 + in_be32(sysctl + SICRL) | (1 << (31 - 19)));
1151 + iounmap(sysctl);
1152 + }
1153 +
1154 + gtm = ioremap_nocache(res.start, res.end - res.start + 1);
1155 +
1156 + beeper_irq = irq_of_parse_and_map(beeper, 0);
1157 + if (beeper_irq != NO_IRQ) {
1158 + int e = request_irq(beeper_irq, rbppc_timer_irq, 0, "beeper", NULL);
1159 + if (e) {
1160 + printk(KERN_ERR "rbppc_beeper_init(%s): Request of beeper irq failed!\n", beeper->full_name);
1161 + }
1162 + }
1163 +}
1164 +
1165 +#define SBIT(x) (0x80000000 >> (x))
1166 +#define DBIT(x, y) ((y) << (32 - (((x % 16) + 1) * 2)))
1167 +
1168 +#define GPIO_DIR_RB333(x) ((x) + (0x1408 >> 2))
1169 +#define GPIO_DATA_RB333(x) ((x) + (0x1404 >> 2))
1170 +
1171 +#define SICRL_RB600(x) ((x) + (0x114 >> 2))
1172 +#define GPIO_DIR_RB600(x) ((x) + (0xc00 >> 2))
1173 +#define GPIO_DATA_RB600(x) ((x) + (0xc08 >> 2))
1174 +
1175 +static void rbppc_restart(char *cmd)
1176 +{
1177 + __be32 __iomem *reg;
1178 + unsigned rb_model;
1179 + struct device_node *root;
1180 + unsigned int size;
1181 +
1182 + root = of_find_node_by_path("/");
1183 + if (root) {
1184 + const char *prop = (char *) of_get_property(root, "model", &size);
1185 + rb_model = prop[sizeof("RB") - 1] - '0';
1186 + of_node_put(root);
1187 + switch (rb_model) {
1188 + case 3:
1189 + reg = ioremap(get_immrbase(), 0x2000);
1190 + local_irq_disable();
1191 + out_be32(GPIO_DIR_RB333(reg),
1192 + (in_be32(GPIO_DIR_RB333(reg)) & ~DBIT(4, 3)) | DBIT(4, 1));
1193 + out_be32(GPIO_DATA_RB333(reg), in_be32(GPIO_DATA_RB333(reg)) & ~SBIT(4));
1194 + break;
1195 + case 6:
1196 + reg = ioremap(get_immrbase(), 0x1000);
1197 + local_irq_disable();
1198 + out_be32(SICRL_RB600(reg), in_be32(SICRL_RB600(reg)) & ~0x00800000);
1199 + out_be32(GPIO_DIR_RB600(reg), in_be32(GPIO_DIR_RB600(reg)) | SBIT(2));
1200 + out_be32(GPIO_DATA_RB600(reg), in_be32(GPIO_DATA_RB600(reg)) & ~SBIT(2));
1201 + break;
1202 + default:
1203 + mpc83xx_restart(cmd);
1204 + break;
1205 + }
1206 + }
1207 + else mpc83xx_restart(cmd);
1208 +
1209 + for (;;) ;
1210 +}
1211 +
1212 +static void rbppc_halt(void)
1213 +{
1214 + while (1);
1215 +}
1216 +
1217 +static struct of_device_id rbppc_ids[] = {
1218 + { .type = "soc", },
1219 + { .compatible = "soc", },
1220 + { .compatible = "simple-bus", },
1221 + { .type = "qe", },
1222 + { .compatible = "fsl,qe", },
1223 + { .compatible = "gianfar", },
1224 + { },
1225 +};
1226 +
1227 +static int __init rbppc_declare_of_platform_devices(void)
1228 +{
1229 + struct device_node *np;
1230 + unsigned idx;
1231 +
1232 + of_platform_bus_probe(NULL, rbppc_ids, NULL);
1233 +
1234 + np = of_find_node_by_type(NULL, "mdio");
1235 + if (np) {
1236 + unsigned len;
1237 + unsigned *res;
1238 + const unsigned *eres;
1239 + struct device_node *ep;
1240 +
1241 + ep = of_find_compatible_node(NULL, "network", "ucc_geth");
1242 + if (ep) {
1243 + eres = of_get_property(ep, "reg", &len);
1244 + res = (unsigned *) of_get_property(np, "reg", &len);
1245 + if (res && eres) {
1246 + res[0] = eres[0] + 0x120;
1247 + }
1248 + }
1249 + }
1250 +
1251 + np = of_find_node_by_name(NULL, "nand");
1252 + if (np) {
1253 + of_platform_device_create(np, "nand", NULL);
1254 + }
1255 +
1256 + idx = 0;
1257 + for_each_node_by_type(np, "rb,cf") {
1258 + char dev_name[12];
1259 + snprintf(dev_name, sizeof(dev_name), "cf.%u", idx);
1260 + of_platform_device_create(np, dev_name, NULL);
1261 + ++idx;
1262 + }
1263 +
1264 + np = of_find_node_by_name(NULL, "beeper");
1265 + if (np) {
1266 + rbppc_beeper_init(np);
1267 + }
1268 +
1269 + return 0;
1270 +}
1271 +machine_device_initcall(rb600, rbppc_declare_of_platform_devices);
1272 +
1273 +define_machine(rb600) {
1274 + .name = "MikroTik RouterBOARD 333/600 series",
1275 + .probe = rbppc_probe,
1276 + .setup_arch = rbppc_setup_arch,
1277 + .init_IRQ = rbppc_init_IRQ,
1278 + .get_irq = ipic_get_irq,
1279 + .restart = rbppc_restart,
1280 + .halt = rbppc_halt,
1281 + .time_init = mpc83xx_time_init,
1282 + .calibrate_decr = generic_calibrate_decr,
1283 +};
1284 +
1285 +static void fixup_pcibridge(struct pci_dev *dev)
1286 +{
1287 + if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1288 + /* let the kernel itself set right memory windows */
1289 + pci_write_config_word(dev, PCI_MEMORY_BASE, 0);
1290 + pci_write_config_word(dev, PCI_MEMORY_LIMIT, 0);
1291 + pci_write_config_word(dev, PCI_PREF_MEMORY_BASE, 0);
1292 + pci_write_config_word(dev, PCI_PREF_MEMORY_LIMIT, 0);
1293 + pci_write_config_byte(dev, PCI_IO_BASE, 0);
1294 + pci_write_config_byte(dev, PCI_IO_LIMIT, 4 << 4);
1295 +
1296 + pci_write_config_byte(
1297 + dev, PCI_COMMAND,
1298 + PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
1299 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
1300 + }
1301 +}
1302 +
1303 +
1304 +static void fixup_rb604(struct pci_dev *dev)
1305 +{
1306 + pci_write_config_byte(dev, 0xC0, 0x01);
1307 +}
1308 +
1309 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_pcibridge)
1310 +DECLARE_PCI_FIXUP_HEADER(0x3388, 0x0021, fixup_rb604)
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