mpc85xx: update lp5521 led-controller node for 5.10
[openwrt/openwrt.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / hiveap-330.dts
1 /*
2 * Aerohive HiveAP-330 Device Tree Source
3 *
4 * Copyright (C) 2017 Chris Blake <chrisrblake93@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 #include <dt-bindings/leds/common.h>
13
14 /include/ "fsl/p1020si-pre.dtsi"
15 / {
16 model = "Aerohive HiveAP-330";
17 compatible = "aerohive,hiveap-330";
18
19 aliases {
20 led-boot = &led_power_green;
21 led-failsafe = &led_fault_red;
22 led-running = &led_power_green;
23 led-upgrade = &led_fault_red;
24 label-mac-device = &enet0;
25 };
26
27 memory {
28 device_type = "memory";
29 };
30
31 board_lbc: lbc: localbus@ffe05000 {
32 reg = <0 0xffe05000 0 0x1000>;
33 ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
34
35 nor@0,0 {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 compatible = "cfi-flash";
39 reg = <0x0 0x0 0x4000000>;
40 bank-width = <2>;
41 device-width = <1>;
42
43 partitions {
44 compatible = "fixed-partitions";
45 #address-cells = <1>;
46 #size-cells = <1>;
47
48 firmware@0 {
49 reg = <0x0 0x3f00000>;
50 label = "firmware";
51 /*
52 * This unknown/invalid compatible prevents
53 * openwrt's mtdsplit_fit to go off a tangent if it
54 * finds a magic value inside the uncompressed kernel
55 * at a blocksized aligned place.
56 */
57 compatible = "areohive,hiveap-330-image";
58 };
59
60 partition@0 {
61 reg = <0x0 0x40000>;
62 label = "dtb";
63 };
64
65 partition@40000 {
66 compatible = "openwrt,uimage", "denx,uimage";
67 reg = <0x40000 0x3ec0000>;
68 label = "kernel";
69 };
70
71 partition@3f00000 {
72 reg = <0x3f00000 0x20000>;
73 label = "hw-info";
74 read-only;
75
76 compatible = "nvmem-cells";
77 #address-cells = <1>;
78 #size-cells = <1>;
79
80 macaddr_hwinfo_0: macaddr@0 {
81 reg = <0x0 0x6>;
82 };
83 };
84
85 partition@3f20000 {
86 reg = <0x3f20000 0x20000>;
87 label = "boot-info";
88 read-only;
89 };
90
91 partition@3f40000 {
92 reg = <0x3f40000 0x20000>;
93 label = "boot-info-backup";
94 read-only;
95 };
96
97 partition@3f60000 {
98 reg = <0x3f60000 0x20000>;
99 label = "u-boot-env";
100 };
101
102 partition@3f80000 {
103 reg = <0x3f80000 0x80000>;
104 label = "u-boot";
105 read-only;
106 };
107 };
108 };
109 };
110
111 board_soc: soc: soc@ffe00000 {
112 ranges = <0x0 0x0 0xffe00000 0x100000>;
113
114 i2c@3100 {
115 tpm@29 {
116 compatible = "atmel,at97sc3204t";
117 reg = <0x29>;
118 };
119
120 lp5521@32 {
121 compatible = "national,lp5521";
122 reg = <0x32>;
123 clock-mode = /bits/ 8 <2>;
124 #if 1
125 led_fault_red: led@0 {
126 reg = <0>;
127 chan-name = "fault:red";
128 led-cur = /bits/ 8 <0x2f>;
129 max-cur = /bits/ 8 <0x5f>;
130 color = <LED_COLOR_ID_RED>;
131 function = LED_FUNCTION_FAULT;
132 };
133 led_power_green: led@1 {
134 reg = <1>;
135 chan-name = "power:green";
136 led-cur = /bits/ 8 <0x2f>;
137 max-cur = /bits/ 8 <0x5f>;
138 color = <LED_COLOR_ID_GREEN>;
139 function = LED_FUNCTION_POWER;
140 };
141 led@2{
142 reg = <2>;
143 chan-name = "blue";
144 led-cur = /bits/ 8 <0x2f>;
145 max-cur = /bits/ 8 <0x5f>;
146 color = <LED_COLOR_ID_BLUE>;
147 };
148 #else
149 /*
150 * openwrt isn't ready to handle multi-intensity leds yet
151 * # echo 255 255 255 > /sys/class/leds/tricolor/multi_intensity
152 * # echo 255 > /sys/class/leds/tricolor/brightness
153 */
154
155 rgbled-0 {
156 function = LED_FUNCTION_POWER;
157 color = <LED_COLOR_ID_RGB>;
158 #address-cells = <1>;
159 #size-cells = <0>;
160
161 led@0 {
162 reg = <0>;
163 chan-name = "tricolor";
164 led-cur = /bits/ 8 <0x2f>;
165 max-cur = /bits/ 8 <0x5f>;
166 color = <LED_COLOR_ID_RED>;
167 };
168 led@1 {
169 reg = <1>;
170 chan-name = "tricolor";
171 led-cur = /bits/ 8 <0x2f>;
172 max-cur = /bits/ 8 <0x5f>;
173 color = <LED_COLOR_ID_GREEN>;
174 };
175 led@2{
176 reg = <2>;
177 chan-name = "tricolor";
178 led-cur = /bits/ 8 <0x2f>;
179 max-cur = /bits/ 8 <0x5f>;
180 color = <LED_COLOR_ID_BLUE>;
181 };
182 };
183 #endif
184 };
185
186 /* Most likely SoC boot config */
187 eeprom@51 {
188 compatible = "eeprom";
189 reg = <0x51>;
190 };
191 };
192
193 mdio@24000 {
194 phy0: ethernet-phy@0 {
195 interrupts = <3 1 0 0>;
196 reg = <0x1>;
197 };
198
199 phy1: ethernet-phy@1 {
200 interrupts = <2 1 0 0>;
201 reg = <0x2>;
202 };
203 };
204
205 mdio@25000 {
206 status = "disabled";
207 };
208
209 mdio@26000 {
210 status = "disabled";
211 };
212
213 enet0: ethernet@b0000 {
214 status = "okay";
215 phy-handle = <&phy0>;
216 phy-connection-type = "rgmii-id";
217 nvmem-cells = <&macaddr_hwinfo_0>;
218 nvmem-cell-names = "mac-address";
219 };
220
221 enet1: ethernet@b1000 {
222 status = "disabled";
223 };
224
225 enet2: ethernet@b2000 {
226 status = "okay";
227 phy-handle = <&phy1>;
228 phy-connection-type = "rgmii-id";
229 nvmem-cells = <&macaddr_hwinfo_0>;
230 nvmem-cell-names = "mac-address";
231 mac-address-increment = <1>;
232 };
233
234 gpio0: gpio-controller@fc00 {
235 };
236
237 usb@22000 {
238 phy_type = "ulpi";
239 dr_mode = "host";
240 };
241
242 usb@23000 {
243 status = "disabled";
244 };
245 };
246
247 pci0: pcie@ffe09000 {
248 reg = <0x0 0xffe09000 0x0 0x1000>;
249 ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
250 0x1000000 0x0 0x00000000 0x0 0xffc30000 0x0 0x10000>;
251 pcie@0 {
252 ranges = <0x2000000 0x0 0xa0000000
253 0x2000000 0x0 0xa0000000
254 0x0 0x20000000
255
256 0x1000000 0x0 0x0
257 0x1000000 0x0 0x0
258 0x0 0x100000>;
259 };
260 };
261
262 pci1: pcie@ffe0a000 {
263 reg = <0x0 0xffe0a000 0x0 0x1000>;
264 ranges = <0x2000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000
265 0x1000000 0x0 0x00000000 0x0 0xffc20000 0x0 0x10000>;
266 pcie@0 {
267 ranges = <0x2000000 0x0 0xc0000000
268 0x2000000 0x0 0xc0000000
269 0x0 0x20000000
270
271 0x1000000 0x0 0x0
272 0x1000000 0x0 0x0
273 0x0 0x100000>;
274 };
275 };
276
277 buttons {
278 compatible = "gpio-keys";
279
280 reset {
281 label = "Reset button";
282 gpios = <&gpio0 8 1>; /* active low */
283 linux,code = <0x198>; /* KEY_RESTART */
284 };
285 };
286 };
287 /include/ "fsl/p1020si-post.dtsi"