0969b272a84b845c5e5c584758801e411b31b2f9
[openwrt/openwrt.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / tl-wdr4900-v1.dts
1 /*
2 * TP-Link TL-WDR4900 v1 Device Tree Source
3 *
4 * Copyright 2013 Gabor Juhos <juhosg@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12 /include/ "fsl/p1010si-pre.dtsi"
13
14 / {
15 model = "TP-Link TL-WDR4900 v1";
16 compatible = "tplink,tl-wdr4900-v1";
17
18 chosen {
19 bootargs = "console=ttyS0,115200";
20 /*
21 stdout-path = "/soc@ffe00000/serial@4500";
22 */
23 };
24
25 aliases {
26 spi0 = &spi0;
27 };
28
29 memory {
30 device_type = "memory";
31 };
32
33 soc: soc@ffe00000 {
34 ranges = <0x0 0x0 0xffe00000 0x100000>;
35
36 spi0: spi@7000 {
37 flash@0 {
38 compatible = "jedec,spi-nor";
39 reg = <0>;
40 spi-max-frequency = <25000000>;
41
42 partitions {
43 compatible = "fixed-partitions";
44 #address-cells = <1>;
45 #size-cells = <1>;
46
47 partition@0 {
48 reg = <0x0 0x0050000>;
49 label = "u-boot";
50 read-only;
51 };
52
53 partition@50000 {
54 reg = <0x00050000 0x00010000>;
55 label = "dtb";
56 read-only;
57 };
58
59 partition@60000 {
60 compatible = "tplink,firmware";
61 reg = <0x00060000 0x00f80000>;
62 label = "firmware";
63 };
64
65 config: partition@fe0000 {
66 reg = <0x00fe0000 0x00010000>;
67 label = "config";
68 read-only;
69 };
70
71 partition@ff0000 {
72 reg = <0x00ff0000 0x00010000>;
73 label = "caldata";
74 read-only;
75 };
76 };
77 };
78 };
79
80 gpio0: gpio-controller@fc00 {
81 };
82
83 usb@22000 {
84 phy_type = "utmi";
85 dr_mode = "host";
86 };
87
88 mdio@24000 {
89 phy0: ethernet-phy@0 {
90 reg = <0x0>;
91 qca,ar8327-initvals = <
92 0x00004 0x07600000 /* PAD0_MODE */
93 0x00008 0x00000000 /* PAD5_MODE */
94 0x0000c 0x01000000 /* PAD6_MODE */
95 0x00010 0x40000000 /* POWER_ON_STRIP */
96 0x00050 0xcf35cf35 /* LED_CTRL0 */
97 0x00054 0xcf35cf35 /* LED_CTRL1 */
98 0x00058 0xcf35cf35 /* LED_CTRL2 */
99 0x0005c 0x03ffff00 /* LED_CTRL3 */
100 0x0007c 0x0000007e /* PORT0_STATUS */
101 0x00094 0x00000200 /* PORT6_STATUS */
102 >;
103 };
104 };
105
106 mdio@25000 {
107 status = "disabled";
108 };
109
110 mdio@26000 {
111 status = "disabled";
112 };
113
114 enet0: ethernet@b0000 {
115 phy-handle = <&phy0>;
116 phy-connection-type = "rgmii-id";
117 mtd-mac-address = <&config 0x144>;
118 };
119
120 enet1: ethernet@b1000 {
121 status = "disabled";
122 };
123
124 enet2: ethernet@b2000 {
125 status = "disabled";
126 };
127
128 sdhc@2e000 {
129 status = "disabled";
130 };
131
132 serial1: serial@4600 {
133 status = "disabled";
134 };
135
136 can0: can@1c000 {
137 status = "disabled";
138 };
139
140 can1: can@1d000 {
141 status = "disabled";
142 };
143
144 ptp_clock@b0e00 {
145 compatible = "fsl,etsec-ptp";
146 reg = <0xb0e00 0xb0>;
147 interrupts = <68 2 0 0 69 2 0 0 70 2 0 0>;
148 fsl,cksel = <1>;
149 fsl,tclk-period = <5>;
150 fsl,tmr-prsc = <2>;
151 fsl,tmr-add = <0xcccccccd>;
152 fsl,tmr-fiper1 = <0x3b9ac9fb>; /* 1PPS */
153 fsl,tmr-fiper2 = <0x00018696>;
154 fsl,max-adj = <249999999>;
155 };
156 };
157
158 pci0: pcie@ffe09000 {
159 reg = <0 0xffe09000 0 0x1000>;
160 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
161 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
162 pcie@0 {
163 ranges = <0x2000000 0x0 0xa0000000
164 0x2000000 0x0 0xa0000000
165 0x0 0x20000000
166
167 0x1000000 0x0 0x0
168 0x1000000 0x0 0x0
169 0x0 0x100000>;
170 };
171 };
172
173 pci1: pcie@ffe0a000 {
174 reg = <0 0xffe0a000 0 0x1000>;
175 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
176 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
177 pcie@0 {
178 ranges = <0x2000000 0x0 0x80000000
179 0x2000000 0x0 0x80000000
180 0x0 0x20000000
181
182 0x1000000 0x0 0x0
183 0x1000000 0x0 0x0
184 0x0 0x100000>;
185 };
186 };
187
188 ifc: ifc@ffe1e000 {
189 status = "disabled";
190 };
191
192 leds {
193 compatible = "gpio-leds";
194
195 system {
196 gpios = <&gpio0 2 1>; /* active low */
197 label = "tp-link:blue:system";
198 };
199
200 usb1 {
201 gpios = <&gpio0 3 1>; /* active low */
202 label = "tp-link:green:usb1";
203 };
204
205 usb2 {
206 gpios = <&gpio0 4 1>; /* active low */
207 label = "tp-link:green:usb2";
208 };
209
210 usbpower {
211 gpios = <&gpio0 10 1>; /* active low */
212 label = "tp-link:usb:power";
213 };
214 };
215
216 buttons {
217 compatible = "gpio-keys";
218
219 reset {
220 label = "Reset button";
221 gpios = <&gpio0 5 1>; /* active low */
222 linux,code = <0x198>; /* KEY_RESTART */
223 };
224
225 rfkill {
226 label = "RFKILL switch";
227 gpios = <&gpio0 11 1>; /* active low */
228 linux,code = <0xf7>; /* RFKill */
229 };
230 };
231 };
232
233 /include/ "fsl/p1010si-post.dtsi"
234
235 /*
236 * The TL-WDR4900 v1 uses the NXP (Freescale) P1014 SoC which is closely
237 * related to the P1010.
238 *
239 * NXP QP1010FS.pdf "QorIQ P1010 and P1014 Communications Processors"
240 * datasheet states that the P1014 does not include the accelerated crypto
241 * module (CAAM/SEC4) which is present in the P1010.
242 *
243 * NXP Appliation Note AN4938 Rev. 2 implies that some P1014 may contain the
244 * SEC4 module, but states that SoCs with System Version Register values
245 * 0x80F10110 or 0x80F10120 do not have the security feature.
246 *
247 * All v1.3 TL-WDR4900 tested have SVR == 0x80F10110 which AN4938 describes
248 * as: core rev 1.0, "P1014 (without security)".
249 *
250 * The SVR value is reported by uboot on the serial console.
251 */
252
253 / {
254 soc: soc@ffe00000 {
255 /delete-node/ crypto@30000; /* Pulled in by p1010si-post */
256 };
257 };