ramips: mt76x8: add support for Cudy TR1200 v1
[openwrt/openwrt.git] / target / linux / mpc85xx / files / arch / powerpc / boot / dts / ws-ap3825i.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later or MIT
2
3 /include/ "fsl/p1020si-pre.dtsi"
4
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/input.h>
7 #include <dt-bindings/leds/common.h>
8
9 / {
10 model = "Extreme Networks WS-AP3825i";
11 compatible = "extreme-networks,ws-ap3825i";
12
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 aliases {
17 ethernet0 = &enet0;
18 ethernet1 = &enet2;
19 led-boot = &led_power_green;
20 led-failsafe = &led_power_red;
21 led-running = &led_power_green;
22 led-upgrade = &led_power_red;
23 };
24
25 chosen {
26 bootargs-override = "console=ttyS0,115200";
27 stdout-path = &serial0;
28 };
29
30 memory {
31 device_type = "memory";
32 };
33
34 leds {
35 compatible = "gpio-leds";
36
37 wifi1 {
38 gpios = <&spi_gpio 3 GPIO_ACTIVE_HIGH>;
39 label = "green:radio1";
40 linux,default-trigger = "phy0tpt";
41 };
42
43 wifi2 {
44 gpios = <&spi_gpio 2 GPIO_ACTIVE_HIGH>;
45 label = "green:radio2";
46 linux,default-trigger = "phy1tpt";
47 };
48
49 led_power_green: power_green {
50 gpios = <&spi_gpio 0 GPIO_ACTIVE_HIGH>;
51 function = LED_FUNCTION_POWER;
52 color = <LED_COLOR_ID_GREEN>;
53 };
54
55 led_power_red: power_red {
56 gpios = <&spi_gpio 1 GPIO_ACTIVE_HIGH>;
57 function = LED_FUNCTION_POWER;
58 color = <LED_COLOR_ID_RED>;
59 };
60
61 lan1_red {
62 gpios = <&spi_gpio 6 GPIO_ACTIVE_HIGH>;
63 label = "red:lan1";
64 };
65
66 lan1_green {
67 gpios = <&spi_gpio 4 GPIO_ACTIVE_HIGH>;
68 label = "green:lan1";
69 };
70
71 lan2_red {
72 gpios = <&spi_gpio 7 GPIO_ACTIVE_HIGH>;
73 label = "red:lan2";
74 };
75
76 lan2_green {
77 gpios = <&spi_gpio 5 GPIO_ACTIVE_HIGH>;
78 label = "green:lan2";
79 };
80 };
81
82 keys {
83 compatible = "gpio-keys";
84
85 reset {
86 label = "Reset button";
87 gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
88 linux,code = <KEY_RESTART>;
89 };
90 };
91
92 lbc: localbus@ffe05000 {
93 reg = <0 0xffe05000 0 0x1000>;
94 ranges = <0x0 0x0 0x0 0xec000000 0x4000000>;
95
96 nor@0 {
97 #address-cells = <1>;
98 #size-cells = <1>;
99 compatible = "cfi-flash";
100 reg = <0x0 0x0 0x4000000>;
101 bank-width = <2>;
102 device-width = <1>;
103
104 partitions {
105 compatible = "fixed-partitions";
106 #address-cells = <1>;
107 #size-cells = <1>;
108
109 partition@0 {
110 compatible = "denx,fit";
111 reg = <0x0 0x3d60000>;
112 label = "firmware";
113 };
114
115 partition@3d60000 {
116 reg = <0x3d60000 0x20000>;
117 label = "calib";
118 read-only;
119 };
120
121 partition@3d80000{
122 reg = <0x3d80000 0x80000>;
123 label = "u-boot";
124 read-only;
125 };
126
127 partition@3e00000{
128 reg = <0x3e00000 0x100000>;
129 label = "nvram";
130 read-only;
131 };
132
133 partition@3f00000 {
134 reg = <0x3f00000 0x20000>;
135 label = "cfg2";
136 };
137
138 partition@3f20000 {
139 reg = <0x3f20000 0x20000>;
140 label = "cfg1";
141 };
142 };
143 };
144 };
145
146 soc: soc@ffe00000 {
147 ranges = <0x0 0x0 0xffe00000 0x100000>;
148
149 gpio0: gpio-controller@fc00 {
150 };
151
152 mdio@24000 {
153 phy0: ethernet-phy@0 {
154 /* interrupts = <3 1 0 0>; */
155 reg = <0x5>;
156 reset-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
157 reset-assert-us = <10000>;
158 reset-deassert-us = <10000>;
159 };
160
161 phy2: ethernet-phy@2 {
162 /* interrupts = <1 1 0 0>; */
163 reg = <0x6>;
164 reset-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
165 reset-assert-us = <10000>;
166 reset-deassert-us = <10000>;
167 };
168 };
169
170 mdio@25000 {
171 status = "disabled";
172 };
173
174 mdio@26000 {
175 status = "disabled";
176 };
177
178 enet0: ethernet@b0000 {
179 status = "okay";
180 phy-handle = <&phy0>;
181 phy-connection-type = "rgmii-id";
182 };
183
184 enet1: ethernet@b1000 {
185 status = "disabled";
186 };
187
188 enet2: ethernet@b2000 {
189 status = "okay";
190 phy-handle = <&phy2>;
191 phy-connection-type = "rgmii-id";
192 };
193
194 usb@22000 {
195 phy_type = "ulpi";
196 dr_mode = "host";
197 };
198
199 usb@23000 {
200 status = "disabled";
201 };
202 };
203
204 pci0: pcie@ffe09000 {
205 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
206 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
207 reg = <0 0xffe09000 0 0x1000>;
208
209 /* Filled by U-Boot */
210 bus-range = <0x00 0x01>;
211 dma-ranges = <0x2000000 0x00 0xfff00000 0x00 0xffe00000
212 0x00 0x100000 0x42000000 0x00 0x00 0x00
213 0x00 0x00 0x10000000>;
214
215 pcie@0 {
216 ranges = <0x2000000 0x0 0xa0000000
217 0x2000000 0x0 0xa0000000
218 0x0 0x20000000
219
220 0x1000000 0x0 0x0
221 0x1000000 0x0 0x0
222 0x0 0x100000>;
223 };
224 };
225
226 pci1: pcie@ffe0a000 {
227 reg = <0 0xffe0a000 0 0x1000>;
228 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
229 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
230
231 /* Filled by U-Boot */
232 bus-range = <0x00 0x01>;
233 dma-ranges = <0x2000000 0x00 0xfff00000 0x00
234 0xffe00000 0x00 0x100000 0x42000000
235 0x00 0x00 0x00 0x00 0x00 0x10000000>;
236
237 pcie@0 {
238 ranges = <0x2000000 0x0 0x80000000
239 0x2000000 0x0 0x80000000
240 0x0 0x20000000
241
242 0x1000000 0x0 0x0
243 0x1000000 0x0 0x0
244 0x0 0x100000>;
245 };
246 };
247 };
248
249 &soc {
250 led_spi {
251 /*
252 * This is currently non-functioning because the spi-gpio
253 * driver refuses to register when presented with this node.
254 */
255 compatible = "spi-gpio";
256 #address-cells = <1>;
257 #size-cells = <0>;
258
259 sck-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
260 mosi-gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
261 num-chipselects = <0>;
262
263 spi_gpio: led_gpio@0 {
264 compatible = "fairchild,74hc595";
265 reg = <0>;
266 gpio-controller;
267 #gpio-cells = <2>;
268 registers-number = <1>;
269 spi-max-frequency = <100000>;
270 };
271 };
272 };
273
274 /include/ "fsl/p1020si-post.dtsi"
275
276 / {
277 cpus {
278 PowerPC,P1020@0 {
279 bus-frequency = <399999996>;
280 timebase-frequency = <50000000>;
281 clock-frequency = <799999992>;
282 d-cache-block-size = <0x20>;
283 d-cache-size = <0x8000>;
284 d-cache-sets = <0x80>;
285 i-cache-block-size = <0x20>;
286 i-cache-size = <0x8000>;
287 i-cache-sets = <0x80>;
288 cpu-release-addr = <0x0 0x0ffff280>;
289 status = "okay";
290 enable-method = "spin-table";
291 };
292
293 PowerPC,P1020@1 {
294 bus-frequency = <399999996>;
295 timebase-frequency = <50000000>;
296 clock-frequency = <799999992>;
297 d-cache-block-size = <0x20>;
298 d-cache-size = <0x8000>;
299 d-cache-sets = <0x80>;
300 i-cache-block-size = <0x20>;
301 i-cache-size = <0x8000>;
302 i-cache-sets = <0x80>;
303 cpu-release-addr = <0x0 0x0ffff2a0>;
304 status = "disabled";
305 enable-method = "spin-table";
306 };
307 };
308
309 memory {
310 reg = <0x0 0x0 0x0 0x10000000>;
311 };
312
313 reserved-memory {
314 #address-cells = <2>;
315 #size-cells = <2>;
316 ranges;
317
318 cpu1-bootpage@ff00000 {
319 /* Reserve upper 1 MB for second-core-bootpage */
320 reg = <0x0 0xff00000 0x0 0x100000>;
321 };
322 };
323
324 soc@ffe00000 {
325 bus-frequency = <399999996>;
326
327 serial@4600 {
328 clock-frequency = <399999996>;
329 };
330
331 serial@4500 {
332 clock-frequency = <399999996>;
333 };
334
335 pic@40000 {
336 clock-frequency = <399999996>;
337 };
338 };
339
340 localbus@ffe05000 {
341 bus-frequency = <24999999>;
342 };
343 };
344
345 &enet0 {
346 rx-stash-idx = <0x00>;
347 rx-stash-len = <0x60>;
348 bd-stash;
349 };
350
351 &enet2 {
352 rx-stash-idx = <0x00>;
353 rx-stash-len = <0x60>;
354 bd-stash;
355 };
356
357 /*
358 * For the OpenWrt 22.03 release, since Linux 5.10.138 now uses
359 * aliases to determine PCI domain numbers, drop aliases so as not to
360 * change the sysfs path of our wireless netdevs.
361 */
362
363 / {
364 aliases {
365 /delete-property/ pci0;
366 /delete-property/ pci1;
367 };
368 };