target/linux/mvebu/patches-3.10/0066-PCI-mvebu-Adapt-to-the-new-device-tree-layout.patch

   1 From 60538f9841697cd4539d353afd8a7f51cd17e4af Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Fri, 5 Jul 2013 14:54:17 +0200
   4 Subject: [PATCH 066/203] PCI: mvebu: Adapt to the new device tree layout
   5
   6 The new device tree layout encodes the window's target ID and attribute
   7 in the PCIe controller node's ranges property. This allows to parse
   8 such entries to obtain such information and use the recently introduced
   9 MBus API to create the windows, instead of using the current name based
  10 scheme.
  11
  12 Acked-by: Bjorn Helgaas <bhelgaas@google.com>
  13 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  14 Tested-by: Andrew Lunn <andrew@lunn.ch>
  15 Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
  16 ---
  17  .../devicetree/bindings/pci/mvebu-pci.txt          | 145 ++++++++++++++++-----
  18  1 file changed, 109 insertions(+), 36 deletions(-)
  19
  20 --- a/Documentation/devicetree/bindings/pci/mvebu-pci.txt
  21 +++ b/Documentation/devicetree/bindings/pci/mvebu-pci.txt
  22 @@ -1,6 +1,7 @@
  23  * Marvell EBU PCIe interfaces
  24
  25  Mandatory properties:
  26 +
  27  - compatible: one of the following values:
  28      marvell,armada-370-pcie
  29      marvell,armada-xp-pcie
  30 @@ -9,11 +10,49 @@ Mandatory properties:
  31  - #interrupt-cells, set to <1>
  32  - bus-range: PCI bus numbers covered
  33  - device_type, set to "pci"
  34 -- ranges: ranges for the PCI memory and I/O regions, as well as the
  35 -  MMIO registers to control the PCIe interfaces.
  36 +- ranges: ranges describing the MMIO registers to control the PCIe
  37 +  interfaces, and ranges describing the MBus windows needed to access
  38 +  the memory and I/O regions of each PCIe interface.
  39 +
  40 +The ranges describing the MMIO registers have the following layout:
  41 +
  42 +    0x82000000 0 r MBUS_ID(0xf0, 0x01) r 0 s
  43 +
  44 +where:
  45 +
  46 +  * r is a 32-bits value that gives the offset of the MMIO
  47 +  registers of this PCIe interface, from the base of the internal
  48 +  registers.
  49 +
  50 +  * s is a 32-bits value that give the size of this MMIO
  51 +  registers area. This range entry translates the '0x82000000 0 r' PCI
  52 +  address into the 'MBUS_ID(0xf0, 0x01) r' CPU address, which is part
  53 +  of the internal register window (as identified by MBUS_ID(0xf0,
  54 +  0x01)).
  55 +
  56 +The ranges describing the MBus windows have the following layout:
  57 +
  58 +    0x8t000000 s 0     MBUS_ID(w, a) 0 1 0
  59 +
  60 +where:
  61
  62 -In addition, the Device Tree node must have sub-nodes describing each
  63 +   * t is the type of the MBus window (as defined by the standard PCI DT
  64 +   bindings), 1 for I/O and 2 for memory.
  65 +
  66 +   * s is the PCI slot that corresponds to this PCIe interface
  67 +
  68 +   * w is the 'target ID' value for the MBus window
  69 +
  70 +   * a the 'attribute' value for the MBus window.
  71 +
  72 +Since the location and size of the different MBus windows is not fixed in
  73 +hardware, and only determined in runtime, those ranges cover the full first
  74 +4 GB of the physical address space, and do not translate into a valid CPU
  75 +address.
  76 +
  77 +In addition, the device tree node must have sub-nodes describing each
  78  PCIe interface, having the following mandatory properties:
  79 +
  80  - reg: used only for interrupt mapping, so only the first four bytes
  81    are used to refer to the correct bus number and device number.
  82  - assigned-addresses: reference to the MMIO registers used to control
  83 @@ -25,7 +64,8 @@ PCIe interface, having the following man
  84  - #address-cells, set to <3>
  85  - #size-cells, set to <2>
  86  - #interrupt-cells, set to <1>
  87 -- ranges, empty property.
  88 +- ranges, translating the MBus windows ranges of the parent node into
  89 +  standard PCI addresses.
  90  - interrupt-map-mask and interrupt-map, standard PCI properties to
  91    define the mapping of the PCIe interface to interrupt numbers.
  92
  93 @@ -46,27 +86,50 @@ pcie-controller {
  94
  95         bus-range = <0x00 0xff>;
  96
  97 -       ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */
  98 -                 0x82000000 0 0xd0042000 0xd0042000 0 0x00002000   /* Port 2.0 registers */
  99 -                 0x82000000 0 0xd0044000 0xd0044000 0 0x00002000   /* Port 0.1 registers */
 100 -                 0x82000000 0 0xd0048000 0xd0048000 0 0x00002000   /* Port 0.2 registers */
 101 -                 0x82000000 0 0xd004c000 0xd004c000 0 0x00002000   /* Port 0.3 registers */
 102 -                 0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */
 103 -                 0x82000000 0 0xd0082000 0xd0082000 0 0x00002000   /* Port 3.0 registers */
 104 -                 0x82000000 0 0xd0084000 0xd0084000 0 0x00002000   /* Port 1.1 registers */
 105 -                 0x82000000 0 0xd0088000 0xd0088000 0 0x00002000   /* Port 1.2 registers */
 106 -                 0x82000000 0 0xd008c000 0xd008c000 0 0x00002000   /* Port 1.3 registers */
 107 -                 0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
 108 -                 0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */
 109 +       ranges =
 110 +              <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000   /* Port 0.0 registers */
 111 +               0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000   /* Port 2.0 registers */
 112 +               0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000   /* Port 0.1 registers */
 113 +               0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000   /* Port 0.2 registers */
 114 +               0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000   /* Port 0.3 registers */
 115 +               0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000   /* Port 1.0 registers */
 116 +               0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000   /* Port 3.0 registers */
 117 +               0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000   /* Port 1.1 registers */
 118 +               0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000   /* Port 1.2 registers */
 119 +               0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000   /* Port 1.3 registers */
 120 +               0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
 121 +               0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO  */
 122 +               0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
 123 +               0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO  */
 124 +               0x82000000 0x3 0     MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
 125 +               0x81000000 0x3 0     MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO  */
 126 +               0x82000000 0x4 0     MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
 127 +               0x81000000 0x4 0     MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO  */
 128 +
 129 +               0x82000000 0x5 0     MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
 130 +               0x81000000 0x5 0     MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO  */
 131 +               0x82000000 0x6 0     MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
 132 +               0x81000000 0x6 0     MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO  */
 133 +               0x82000000 0x7 0     MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
 134 +               0x81000000 0x7 0     MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO  */
 135 +               0x82000000 0x8 0     MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
 136 +               0x81000000 0x8 0     MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO  */
 137 +
 138 +               0x82000000 0x9 0     MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
 139 +               0x81000000 0x9 0     MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO  */
 140 +
 141 +               0x82000000 0xa 0     MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
 142 +               0x81000000 0xa 0     MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO  */>;
 143
 144         pcie@1,0 {
 145                 device_type = "pci";
 146 -               assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;
 147 +               assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
 148                 reg = <0x0800 0 0 0 0>;
 149                 #address-cells = <3>;
 150                 #size-cells = <2>;
 151                 #interrupt-cells = <1>;
 152 -               ranges;
 153 +               ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
 154 +                         0x81000000 0 0 0x81000000 0x1 0 1 0>;
 155                 interrupt-map-mask = <0 0 0 0>;
 156                 interrupt-map = <0 0 0 0 &mpic 58>;
 157                 marvell,pcie-port = <0>;
 158 @@ -77,12 +140,13 @@ pcie-controller {
 159
 160         pcie@2,0 {
 161                 device_type = "pci";
 162 -               assigned-addresses = <0x82001000 0 0xd0044000 0 0x2000>;
 163 +               assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
 164                 reg = <0x1000 0 0 0 0>;
 165                 #address-cells = <3>;
 166                 #size-cells = <2>;
 167                 #interrupt-cells = <1>;
 168 -               ranges;
 169 +               ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
 170 +                         0x81000000 0 0 0x81000000 0x2 0 1 0>;
 171                 interrupt-map-mask = <0 0 0 0>;
 172                 interrupt-map = <0 0 0 0 &mpic 59>;
 173                 marvell,pcie-port = <0>;
 174 @@ -93,12 +157,13 @@ pcie-controller {
 175
 176         pcie@3,0 {
 177                 device_type = "pci";
 178 -               assigned-addresses = <0x82001800 0 0xd0048000 0 0x2000>;
 179 +               assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
 180                 reg = <0x1800 0 0 0 0>;
 181                 #address-cells = <3>;
 182                 #size-cells = <2>;
 183                 #interrupt-cells = <1>;
 184 -               ranges;
 185 +               ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
 186 +                         0x81000000 0 0 0x81000000 0x3 0 1 0>;
 187                 interrupt-map-mask = <0 0 0 0>;
 188                 interrupt-map = <0 0 0 0 &mpic 60>;
 189                 marvell,pcie-port = <0>;
 190 @@ -109,12 +174,13 @@ pcie-controller {
 191
 192         pcie@4,0 {
 193                 device_type = "pci";
 194 -               assigned-addresses = <0x82002000 0 0xd004c000 0 0x2000>;
 195 +               assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
 196                 reg = <0x2000 0 0 0 0>;
 197                 #address-cells = <3>;
 198                 #size-cells = <2>;
 199                 #interrupt-cells = <1>;
 200 -               ranges;
 201 +               ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
 202 +                         0x81000000 0 0 0x81000000 0x4 0 1 0>;
 203                 interrupt-map-mask = <0 0 0 0>;
 204                 interrupt-map = <0 0 0 0 &mpic 61>;
 205                 marvell,pcie-port = <0>;
 206 @@ -125,12 +191,13 @@ pcie-controller {
 207
 208         pcie@5,0 {
 209                 device_type = "pci";
 210 -               assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;
 211 +               assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
 212                 reg = <0x2800 0 0 0 0>;
 213                 #address-cells = <3>;
 214                 #size-cells = <2>;
 215                 #interrupt-cells = <1>;
 216 -               ranges;
 217 +               ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
 218 +                         0x81000000 0 0 0x81000000 0x5 0 1 0>;
 219                 interrupt-map-mask = <0 0 0 0>;
 220                 interrupt-map = <0 0 0 0 &mpic 62>;
 221                 marvell,pcie-port = <1>;
 222 @@ -141,12 +208,13 @@ pcie-controller {
 223
 224         pcie@6,0 {
 225                 device_type = "pci";
 226 -               assigned-addresses = <0x82003000 0 0xd0084000 0 0x2000>;
 227 +               assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
 228                 reg = <0x3000 0 0 0 0>;
 229                 #address-cells = <3>;
 230                 #size-cells = <2>;
 231                 #interrupt-cells = <1>;
 232 -               ranges;
 233 +               ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
 234 +                         0x81000000 0 0 0x81000000 0x6 0 1 0>;
 235                 interrupt-map-mask = <0 0 0 0>;
 236                 interrupt-map = <0 0 0 0 &mpic 63>;
 237                 marvell,pcie-port = <1>;
 238 @@ -157,12 +225,13 @@ pcie-controller {
 239
 240         pcie@7,0 {
 241                 device_type = "pci";
 242 -               assigned-addresses = <0x82003800 0 0xd0088000 0 0x2000>;
 243 +               assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
 244                 reg = <0x3800 0 0 0 0>;
 245                 #address-cells = <3>;
 246                 #size-cells = <2>;
 247                 #interrupt-cells = <1>;
 248 -               ranges;
 249 +               ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
 250 +                         0x81000000 0 0 0x81000000 0x7 0 1 0>;
 251                 interrupt-map-mask = <0 0 0 0>;
 252                 interrupt-map = <0 0 0 0 &mpic 64>;
 253                 marvell,pcie-port = <1>;
 254 @@ -173,12 +242,13 @@ pcie-controller {
 255
 256         pcie@8,0 {
 257                 device_type = "pci";
 258 -               assigned-addresses = <0x82004000 0 0xd008c000 0 0x2000>;
 259 +               assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
 260                 reg = <0x4000 0 0 0 0>;
 261                 #address-cells = <3>;
 262                 #size-cells = <2>;
 263                 #interrupt-cells = <1>;
 264 -               ranges;
 265 +               ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
 266 +                         0x81000000 0 0 0x81000000 0x8 0 1 0>;
 267                 interrupt-map-mask = <0 0 0 0>;
 268                 interrupt-map = <0 0 0 0 &mpic 65>;
 269                 marvell,pcie-port = <1>;
 270 @@ -186,14 +256,16 @@ pcie-controller {
 271                 clocks = <&gateclk 12>;
 272                 status = "disabled";
 273         };
 274 +
 275         pcie@9,0 {
 276                 device_type = "pci";
 277 -               assigned-addresses = <0x82004800 0 0xd0042000 0 0x2000>;
 278 +               assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
 279                 reg = <0x4800 0 0 0 0>;
 280                 #address-cells = <3>;
 281                 #size-cells = <2>;
 282                 #interrupt-cells = <1>;
 283 -               ranges;
 284 +               ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
 285 +                         0x81000000 0 0 0x81000000 0x9 0 1 0>;
 286                 interrupt-map-mask = <0 0 0 0>;
 287                 interrupt-map = <0 0 0 0 &mpic 99>;
 288                 marvell,pcie-port = <2>;
 289 @@ -204,12 +276,13 @@ pcie-controller {
 290
 291         pcie@10,0 {
 292                 device_type = "pci";
 293 -               assigned-addresses = <0x82005000 0 0xd0082000 0 0x2000>;
 294 +               assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
 295                 reg = <0x5000 0 0 0 0>;
 296                 #address-cells = <3>;
 297                 #size-cells = <2>;
 298                 #interrupt-cells = <1>;
 299 -               ranges;
 300 +               ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
 301 +                         0x81000000 0 0 0x81000000 0xa 0 1 0>;
 302                 interrupt-map-mask = <0 0 0 0>;
 303                 interrupt-map = <0 0 0 0 &mpic 103>;
 304                 marvell,pcie-port = <3>;