projects / openwrt / staging / mkresin.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
base-files: define yes/no as valid boolean options
[openwrt/staging/mkresin.git] / target / linux / mvebu / patches-3.10 / 0203-ARM-mvebu-fix-second-and-third-PCIe-unit-of-Armada-X.patch
1 From 9c2caf4d2d60780182d7754896c41496192b99c2 Mon Sep 17 00:00:00 2001
2 From: Arnaud Ebalard <arno@natisbad.org>
3 Date: Tue, 5 Nov 2013 21:46:02 +0100
4 Subject: [PATCH 203/203] ARM: mvebu: fix second and third PCIe unit of Armada
5 XP mv78260
6
7 mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The
8 two first units are both x4 and quad x1 capable. The third unit
9 is only x4 capable. This patch fixes mv78260 .dtsi to reflect
10 those capabilities.
11
12 Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
13 Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
14 Cc: <stable@vger.kernel.org> # v3.10.x
15 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
16 ---
17 arch/arm/boot/dts/armada-xp-mv78260.dtsi | 109 ++++++++++++++++++++++++-------
18 1 file changed, 85 insertions(+), 24 deletions(-)
19
20 --- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
21 +++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
22 @@ -48,7 +48,7 @@
23 /*
24 * MV78260 has 3 PCIe units Gen2.0: Two units can be
25 * configured as x4 or quad x1 lanes. One unit is
26 - * x4/x1.
27 + * x4 only.
28 */
29 pcie-controller {
30 compatible = "marvell,armada-xp-pcie";
31 @@ -68,7 +68,9 @@
32 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
33 0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
34 0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
35 - 0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
36 + 0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
37 + 0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
38 + 0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
39 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
40 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
41 0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
42 @@ -77,10 +79,18 @@
43 0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
44 0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
45 0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
46 - 0x82000000 0x9 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
47 - 0x81000000 0x9 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
48 - 0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
49 - 0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
50 +
51 + 0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
52 + 0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
53 + 0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
54 + 0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
55 + 0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
56 + 0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
57 + 0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
58 + 0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
59 +
60 + 0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
61 + 0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
62
63 pcie@1,0 {
64 device_type = "pci";
65 @@ -106,8 +116,8 @@
66 #address-cells = <3>;
67 #size-cells = <2>;
68 #interrupt-cells = <1>;
69 - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
70 - 0x81000000 0 0 0x81000000 0x2 0 1 0>;
71 + ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
72 + 0x81000000 0 0 0x81000000 0x2 0 1 0>;
73 interrupt-map-mask = <0 0 0 0>;
74 interrupt-map = <0 0 0 0 &mpic 59>;
75 marvell,pcie-port = <0>;
76 @@ -150,37 +160,88 @@
77 status = "disabled";
78 };
79
80 - pcie@9,0 {
81 + pcie@5,0 {
82 device_type = "pci";
83 - assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
84 - reg = <0x4800 0 0 0 0>;
85 + assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
86 + reg = <0x2800 0 0 0 0>;
87 #address-cells = <3>;
88 #size-cells = <2>;
89 #interrupt-cells = <1>;
90 - ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
91 - 0x81000000 0 0 0x81000000 0x9 0 1 0>;
92 + ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
93 + 0x81000000 0 0 0x81000000 0x5 0 1 0>;
94 interrupt-map-mask = <0 0 0 0>;
95 - interrupt-map = <0 0 0 0 &mpic 99>;
96 - marvell,pcie-port = <2>;
97 + interrupt-map = <0 0 0 0 &mpic 62>;
98 + marvell,pcie-port = <1>;
99 marvell,pcie-lane = <0>;
100 - clocks = <&gateclk 26>;
101 + clocks = <&gateclk 9>;
102 status = "disabled";
103 };
104
105 - pcie@10,0 {
106 + pcie@6,0 {
107 device_type = "pci";
108 - assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
109 - reg = <0x5000 0 0 0 0>;
110 + assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
111 + reg = <0x3000 0 0 0 0>;
112 #address-cells = <3>;
113 #size-cells = <2>;
114 #interrupt-cells = <1>;
115 - ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
116 - 0x81000000 0 0 0x81000000 0xa 0 1 0>;
117 + ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
118 + 0x81000000 0 0 0x81000000 0x6 0 1 0>;
119 interrupt-map-mask = <0 0 0 0>;
120 - interrupt-map = <0 0 0 0 &mpic 103>;
121 - marvell,pcie-port = <3>;
122 + interrupt-map = <0 0 0 0 &mpic 63>;
123 + marvell,pcie-port = <1>;
124 + marvell,pcie-lane = <1>;
125 + clocks = <&gateclk 10>;
126 + status = "disabled";
127 + };
128 +
129 + pcie@7,0 {
130 + device_type = "pci";
131 + assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
132 + reg = <0x3800 0 0 0 0>;
133 + #address-cells = <3>;
134 + #size-cells = <2>;
135 + #interrupt-cells = <1>;
136 + ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
137 + 0x81000000 0 0 0x81000000 0x7 0 1 0>;
138 + interrupt-map-mask = <0 0 0 0>;
139 + interrupt-map = <0 0 0 0 &mpic 64>;
140 + marvell,pcie-port = <1>;
141 + marvell,pcie-lane = <2>;
142 + clocks = <&gateclk 11>;
143 + status = "disabled";
144 + };
145 +
146 + pcie@8,0 {
147 + device_type = "pci";
148 + assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
149 + reg = <0x4000 0 0 0 0>;
150 + #address-cells = <3>;
151 + #size-cells = <2>;
152 + #interrupt-cells = <1>;
153 + ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
154 + 0x81000000 0 0 0x81000000 0x8 0 1 0>;
155 + interrupt-map-mask = <0 0 0 0>;
156 + interrupt-map = <0 0 0 0 &mpic 65>;
157 + marvell,pcie-port = <1>;
158 + marvell,pcie-lane = <3>;
159 + clocks = <&gateclk 12>;
160 + status = "disabled";
161 + };
162 +
163 + pcie@9,0 {
164 + device_type = "pci";
165 + assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
166 + reg = <0x4800 0 0 0 0>;
167 + #address-cells = <3>;
168 + #size-cells = <2>;
169 + #interrupt-cells = <1>;
170 + ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
171 + 0x81000000 0 0 0x81000000 0x9 0 1 0>;
172 + interrupt-map-mask = <0 0 0 0>;
173 + interrupt-map = <0 0 0 0 &mpic 99>;
174 + marvell,pcie-port = <2>;
175 marvell,pcie-lane = <0>;
176 - clocks = <&gateclk 27>;
177 + clocks = <&gateclk 26>;
178 status = "disabled";
179 };
180 };
Staging tree of Mathias Kresin