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ipq806x: remove obsolete Kernel 5.4
[openwrt/staging/dedeckeh.git] / target / linux / mvebu / patches-5.4 / 002-v5.5-arm64-dts-marvell-Prepare-the-introduction-of-CP115.patch
1 From 47cf40af64c35a69ef6a193c47768ad1bda29db2 Mon Sep 17 00:00:00 2001
2 From: Miquel Raynal <miquel.raynal@bootlin.com>
3 Date: Fri, 4 Oct 2019 16:27:29 +0200
4 Subject: [PATCH] arm64: dts: marvell: Prepare the introduction of CP115
5
6 CP110 and CP115 are almost the same in terms of features and have a
7 very limited set of differences. Let's create an armada-cp11x.dtsi
8 file which will be used to instantiate both CP110 and CP115
9 nodes.
10
11 The only changes between the two armada-cp11{0,x}.dtsi files are the
12 following naming in macros: s/CP110/CP11X/.
13
14 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
15 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
16 ---
17 arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 28 +-
18 arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 56 +-
19 .../arm64/boot/dts/marvell/armada-common.dtsi | 4 +-
20 arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 575 +----------------
21 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 579 ++++++++++++++++++
22 5 files changed, 627 insertions(+), 615 deletions(-)
23 create mode 100644 arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
24
25 --- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
26 +++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
27 @@ -17,23 +17,23 @@
28 /*
29 * Instantiate the CP110
30 */
31 -#define CP110_NAME cp0
32 -#define CP110_BASE f2000000
33 -#define CP110_PCIE_IO_BASE 0xf9000000
34 -#define CP110_PCIE_MEM_BASE 0xf6000000
35 -#define CP110_PCIE0_BASE f2600000
36 -#define CP110_PCIE1_BASE f2620000
37 -#define CP110_PCIE2_BASE f2640000
38 +#define CP11X_NAME cp0
39 +#define CP11X_BASE f2000000
40 +#define CP11X_PCIE_IO_BASE 0xf9000000
41 +#define CP11X_PCIE_MEM_BASE 0xf6000000
42 +#define CP11X_PCIE0_BASE f2600000
43 +#define CP11X_PCIE1_BASE f2620000
44 +#define CP11X_PCIE2_BASE f2640000
45
46 #include "armada-cp110.dtsi"
47
48 -#undef CP110_NAME
49 -#undef CP110_BASE
50 -#undef CP110_PCIE_IO_BASE
51 -#undef CP110_PCIE_MEM_BASE
52 -#undef CP110_PCIE0_BASE
53 -#undef CP110_PCIE1_BASE
54 -#undef CP110_PCIE2_BASE
55 +#undef CP11X_NAME
56 +#undef CP11X_BASE
57 +#undef CP11X_PCIE_IO_BASE
58 +#undef CP11X_PCIE_MEM_BASE
59 +#undef CP11X_PCIE0_BASE
60 +#undef CP11X_PCIE1_BASE
61 +#undef CP11X_PCIE2_BASE
62
63 &cp0_gpio1 {
64 status = "okay";
65 --- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
66 +++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
67 @@ -19,44 +19,44 @@
68 /*
69 * Instantiate the master CP110
70 */
71 -#define CP110_NAME cp0
72 -#define CP110_BASE f2000000
73 -#define CP110_PCIE_IO_BASE 0xf9000000
74 -#define CP110_PCIE_MEM_BASE 0xf6000000
75 -#define CP110_PCIE0_BASE f2600000
76 -#define CP110_PCIE1_BASE f2620000
77 -#define CP110_PCIE2_BASE f2640000
78 +#define CP11X_NAME cp0
79 +#define CP11X_BASE f2000000
80 +#define CP11X_PCIE_IO_BASE 0xf9000000
81 +#define CP11X_PCIE_MEM_BASE 0xf6000000
82 +#define CP11X_PCIE0_BASE f2600000
83 +#define CP11X_PCIE1_BASE f2620000
84 +#define CP11X_PCIE2_BASE f2640000
85
86 #include "armada-cp110.dtsi"
87
88 -#undef CP110_NAME
89 -#undef CP110_BASE
90 -#undef CP110_PCIE_IO_BASE
91 -#undef CP110_PCIE_MEM_BASE
92 -#undef CP110_PCIE0_BASE
93 -#undef CP110_PCIE1_BASE
94 -#undef CP110_PCIE2_BASE
95 +#undef CP11X_NAME
96 +#undef CP11X_BASE
97 +#undef CP11X_PCIE_IO_BASE
98 +#undef CP11X_PCIE_MEM_BASE
99 +#undef CP11X_PCIE0_BASE
100 +#undef CP11X_PCIE1_BASE
101 +#undef CP11X_PCIE2_BASE
102
103 /*
104 * Instantiate the slave CP110
105 */
106 -#define CP110_NAME cp1
107 -#define CP110_BASE f4000000
108 -#define CP110_PCIE_IO_BASE 0xfd000000
109 -#define CP110_PCIE_MEM_BASE 0xfa000000
110 -#define CP110_PCIE0_BASE f4600000
111 -#define CP110_PCIE1_BASE f4620000
112 -#define CP110_PCIE2_BASE f4640000
113 +#define CP11X_NAME cp1
114 +#define CP11X_BASE f4000000
115 +#define CP11X_PCIE_IO_BASE 0xfd000000
116 +#define CP11X_PCIE_MEM_BASE 0xfa000000
117 +#define CP11X_PCIE0_BASE f4600000
118 +#define CP11X_PCIE1_BASE f4620000
119 +#define CP11X_PCIE2_BASE f4640000
120
121 #include "armada-cp110.dtsi"
122
123 -#undef CP110_NAME
124 -#undef CP110_BASE
125 -#undef CP110_PCIE_IO_BASE
126 -#undef CP110_PCIE_MEM_BASE
127 -#undef CP110_PCIE0_BASE
128 -#undef CP110_PCIE1_BASE
129 -#undef CP110_PCIE2_BASE
130 +#undef CP11X_NAME
131 +#undef CP11X_BASE
132 +#undef CP11X_PCIE_IO_BASE
133 +#undef CP11X_PCIE_MEM_BASE
134 +#undef CP11X_PCIE0_BASE
135 +#undef CP11X_PCIE1_BASE
136 +#undef CP11X_PCIE2_BASE
137
138 /* The 80x0 has two CP blocks, but uses only one block from each. */
139 &cp1_gpio1 {
140 --- a/arch/arm64/boot/dts/marvell/armada-common.dtsi
141 +++ b/arch/arm64/boot/dts/marvell/armada-common.dtsi
142 @@ -6,6 +6,6 @@
143 /* Common definitions used by Armada 7K/8K DTs */
144 #define PASTER(x, y) x ## y
145 #define EVALUATOR(x, y) PASTER(x, y)
146 -#define CP110_LABEL(name) EVALUATOR(CP110_NAME, EVALUATOR(_, name))
147 -#define CP110_NODE_NAME(name) EVALUATOR(CP110_NAME, EVALUATOR(-, name))
148 +#define CP11X_LABEL(name) EVALUATOR(CP11X_NAME, EVALUATOR(_, name))
149 +#define CP11X_NODE_NAME(name) EVALUATOR(CP11X_NAME, EVALUATOR(-, name))
150 #define ADDRESSIFY(addr) EVALUATOR(0x, addr)
151 --- a/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
152 +++ b/arch/arm64/boot/dts/marvell/armada-cp110.dtsi
153 @@ -1,579 +1,12 @@
154 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
155 /*
156 - * Copyright (C) 2016 Marvell Technology Group Ltd.
157 + * Copyright (C) 2019 Marvell Technology Group Ltd.
158 *
159 * Device Tree file for Marvell Armada CP110.
160 */
161
162 -#include <dt-bindings/interrupt-controller/mvebu-icu.h>
163 -#include <dt-bindings/thermal/thermal.h>
164 +#define CP11X_TYPE cp110
165
166 -#include "armada-common.dtsi"
167 +#include "armada-cp11x.dtsi"
168
169 -#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
170 -#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
171 -#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
172 -
173 -/ {
174 - /*
175 - * The contents of the node are defined below, in order to
176 - * save one indentation level
177 - */
178 - CP110_NAME: CP110_NAME { };
179 -
180 - /*
181 - * CPs only have one sensor in the thermal IC.
182 - *
183 - * The cooling maps are empty as there are no cooling devices.
184 - */
185 - thermal-zones {
186 - CP110_LABEL(thermal_ic): CP110_NODE_NAME(thermal-ic) {
187 - polling-delay-passive = <0>; /* Interrupt driven */
188 - polling-delay = <0>; /* Interrupt driven */
189 -
190 - thermal-sensors = <&CP110_LABEL(thermal) 0>;
191 -
192 - trips {
193 - CP110_LABEL(crit): crit {
194 - temperature = <100000>; /* mC degrees */
195 - hysteresis = <2000>; /* mC degrees */
196 - type = "critical";
197 - };
198 - };
199 -
200 - cooling-maps { };
201 - };
202 - };
203 -};
204 -
205 -&CP110_NAME {
206 - #address-cells = <2>;
207 - #size-cells = <2>;
208 - compatible = "simple-bus";
209 - interrupt-parent = <&CP110_LABEL(icu_nsr)>;
210 - ranges;
211 -
212 - config-space@CP110_BASE {
213 - #address-cells = <1>;
214 - #size-cells = <1>;
215 - compatible = "simple-bus";
216 - ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
217 -
218 - CP110_LABEL(ethernet): ethernet@0 {
219 - compatible = "marvell,armada-7k-pp22";
220 - reg = <0x0 0x100000>, <0x129000 0xb000>;
221 - clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
222 - <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
223 - <&CP110_LABEL(clk) 1 18>;
224 - clock-names = "pp_clk", "gop_clk",
225 - "mg_clk", "mg_core_clk", "axi_clk";
226 - marvell,system-controller = <&CP110_LABEL(syscon0)>;
227 - status = "disabled";
228 - dma-coherent;
229 -
230 - CP110_LABEL(eth0): eth0 {
231 - interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
232 - <43 IRQ_TYPE_LEVEL_HIGH>,
233 - <47 IRQ_TYPE_LEVEL_HIGH>,
234 - <51 IRQ_TYPE_LEVEL_HIGH>,
235 - <55 IRQ_TYPE_LEVEL_HIGH>,
236 - <59 IRQ_TYPE_LEVEL_HIGH>,
237 - <63 IRQ_TYPE_LEVEL_HIGH>,
238 - <67 IRQ_TYPE_LEVEL_HIGH>,
239 - <71 IRQ_TYPE_LEVEL_HIGH>,
240 - <129 IRQ_TYPE_LEVEL_HIGH>;
241 - interrupt-names = "hif0", "hif1", "hif2",
242 - "hif3", "hif4", "hif5", "hif6", "hif7",
243 - "hif8", "link";
244 - port-id = <0>;
245 - gop-port-id = <0>;
246 - status = "disabled";
247 - };
248 -
249 - CP110_LABEL(eth1): eth1 {
250 - interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
251 - <44 IRQ_TYPE_LEVEL_HIGH>,
252 - <48 IRQ_TYPE_LEVEL_HIGH>,
253 - <52 IRQ_TYPE_LEVEL_HIGH>,
254 - <56 IRQ_TYPE_LEVEL_HIGH>,
255 - <60 IRQ_TYPE_LEVEL_HIGH>,
256 - <64 IRQ_TYPE_LEVEL_HIGH>,
257 - <68 IRQ_TYPE_LEVEL_HIGH>,
258 - <72 IRQ_TYPE_LEVEL_HIGH>,
259 - <128 IRQ_TYPE_LEVEL_HIGH>;
260 - interrupt-names = "hif0", "hif1", "hif2",
261 - "hif3", "hif4", "hif5", "hif6", "hif7",
262 - "hif8", "link";
263 - port-id = <1>;
264 - gop-port-id = <2>;
265 - status = "disabled";
266 - };
267 -
268 - CP110_LABEL(eth2): eth2 {
269 - interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
270 - <45 IRQ_TYPE_LEVEL_HIGH>,
271 - <49 IRQ_TYPE_LEVEL_HIGH>,
272 - <53 IRQ_TYPE_LEVEL_HIGH>,
273 - <57 IRQ_TYPE_LEVEL_HIGH>,
274 - <61 IRQ_TYPE_LEVEL_HIGH>,
275 - <65 IRQ_TYPE_LEVEL_HIGH>,
276 - <69 IRQ_TYPE_LEVEL_HIGH>,
277 - <73 IRQ_TYPE_LEVEL_HIGH>,
278 - <127 IRQ_TYPE_LEVEL_HIGH>;
279 - interrupt-names = "hif0", "hif1", "hif2",
280 - "hif3", "hif4", "hif5", "hif6", "hif7",
281 - "hif8", "link";
282 - port-id = <2>;
283 - gop-port-id = <3>;
284 - status = "disabled";
285 - };
286 - };
287 -
288 - CP110_LABEL(comphy): phy@120000 {
289 - compatible = "marvell,comphy-cp110";
290 - reg = <0x120000 0x6000>;
291 - marvell,system-controller = <&CP110_LABEL(syscon0)>;
292 - clocks = <&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
293 - <&CP110_LABEL(clk) 1 18>;
294 - clock-names = "mg_clk", "mg_core_clk", "axi_clk";
295 - #address-cells = <1>;
296 - #size-cells = <0>;
297 -
298 - CP110_LABEL(comphy0): phy@0 {
299 - reg = <0>;
300 - #phy-cells = <1>;
301 - };
302 -
303 - CP110_LABEL(comphy1): phy@1 {
304 - reg = <1>;
305 - #phy-cells = <1>;
306 - };
307 -
308 - CP110_LABEL(comphy2): phy@2 {
309 - reg = <2>;
310 - #phy-cells = <1>;
311 - };
312 -
313 - CP110_LABEL(comphy3): phy@3 {
314 - reg = <3>;
315 - #phy-cells = <1>;
316 - };
317 -
318 - CP110_LABEL(comphy4): phy@4 {
319 - reg = <4>;
320 - #phy-cells = <1>;
321 - };
322 -
323 - CP110_LABEL(comphy5): phy@5 {
324 - reg = <5>;
325 - #phy-cells = <1>;
326 - };
327 - };
328 -
329 - CP110_LABEL(mdio): mdio@12a200 {
330 - #address-cells = <1>;
331 - #size-cells = <0>;
332 - compatible = "marvell,orion-mdio";
333 - reg = <0x12a200 0x10>;
334 - clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
335 - <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
336 - status = "disabled";
337 - };
338 -
339 - CP110_LABEL(xmdio): mdio@12a600 {
340 - #address-cells = <1>;
341 - #size-cells = <0>;
342 - compatible = "marvell,xmdio";
343 - reg = <0x12a600 0x10>;
344 - clocks = <&CP110_LABEL(clk) 1 5>,
345 - <&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
346 - status = "disabled";
347 - };
348 -
349 - CP110_LABEL(icu): interrupt-controller@1e0000 {
350 - compatible = "marvell,cp110-icu";
351 - reg = <0x1e0000 0x440>;
352 - #address-cells = <1>;
353 - #size-cells = <1>;
354 -
355 - CP110_LABEL(icu_nsr): interrupt-controller@10 {
356 - compatible = "marvell,cp110-icu-nsr";
357 - reg = <0x10 0x20>;
358 - #interrupt-cells = <2>;
359 - interrupt-controller;
360 - msi-parent = <&gicp>;
361 - };
362 -
363 - CP110_LABEL(icu_sei): interrupt-controller@50 {
364 - compatible = "marvell,cp110-icu-sei";
365 - reg = <0x50 0x10>;
366 - #interrupt-cells = <2>;
367 - interrupt-controller;
368 - msi-parent = <&sei>;
369 - };
370 - };
371 -
372 - CP110_LABEL(rtc): rtc@284000 {
373 - compatible = "marvell,armada-8k-rtc";
374 - reg = <0x284000 0x20>, <0x284080 0x24>;
375 - reg-names = "rtc", "rtc-soc";
376 - interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
377 - };
378 -
379 - CP110_LABEL(syscon0): system-controller@440000 {
380 - compatible = "syscon", "simple-mfd";
381 - reg = <0x440000 0x2000>;
382 -
383 - CP110_LABEL(clk): clock {
384 - compatible = "marvell,cp110-clock";
385 - #clock-cells = <2>;
386 - };
387 -
388 - CP110_LABEL(gpio1): gpio@100 {
389 - compatible = "marvell,armada-8k-gpio";
390 - offset = <0x100>;
391 - ngpios = <32>;
392 - gpio-controller;
393 - #gpio-cells = <2>;
394 - gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
395 - interrupt-controller;
396 - interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
397 - <85 IRQ_TYPE_LEVEL_HIGH>,
398 - <84 IRQ_TYPE_LEVEL_HIGH>,
399 - <83 IRQ_TYPE_LEVEL_HIGH>;
400 - #interrupt-cells = <2>;
401 - status = "disabled";
402 - };
403 -
404 - CP110_LABEL(gpio2): gpio@140 {
405 - compatible = "marvell,armada-8k-gpio";
406 - offset = <0x140>;
407 - ngpios = <31>;
408 - gpio-controller;
409 - #gpio-cells = <2>;
410 - gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
411 - interrupt-controller;
412 - interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
413 - <81 IRQ_TYPE_LEVEL_HIGH>,
414 - <80 IRQ_TYPE_LEVEL_HIGH>,
415 - <79 IRQ_TYPE_LEVEL_HIGH>;
416 - #interrupt-cells = <2>;
417 - status = "disabled";
418 - };
419 - };
420 -
421 - CP110_LABEL(syscon1): system-controller@400000 {
422 - compatible = "syscon", "simple-mfd";
423 - reg = <0x400000 0x1000>;
424 - #address-cells = <1>;
425 - #size-cells = <1>;
426 -
427 - CP110_LABEL(thermal): thermal-sensor@70 {
428 - compatible = "marvell,armada-cp110-thermal";
429 - reg = <0x70 0x10>;
430 - interrupts-extended =
431 - <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
432 - #thermal-sensor-cells = <1>;
433 - };
434 - };
435 -
436 - CP110_LABEL(usb3_0): usb3@500000 {
437 - compatible = "marvell,armada-8k-xhci",
438 - "generic-xhci";
439 - reg = <0x500000 0x4000>;
440 - dma-coherent;
441 - interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
442 - clock-names = "core", "reg";
443 - clocks = <&CP110_LABEL(clk) 1 22>,
444 - <&CP110_LABEL(clk) 1 16>;
445 - status = "disabled";
446 - };
447 -
448 - CP110_LABEL(usb3_1): usb3@510000 {
449 - compatible = "marvell,armada-8k-xhci",
450 - "generic-xhci";
451 - reg = <0x510000 0x4000>;
452 - dma-coherent;
453 - interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
454 - clock-names = "core", "reg";
455 - clocks = <&CP110_LABEL(clk) 1 23>,
456 - <&CP110_LABEL(clk) 1 16>;
457 - status = "disabled";
458 - };
459 -
460 - CP110_LABEL(sata0): sata@540000 {
461 - compatible = "marvell,armada-8k-ahci",
462 - "generic-ahci";
463 - reg = <0x540000 0x30000>;
464 - dma-coherent;
465 - interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
466 - clocks = <&CP110_LABEL(clk) 1 15>,
467 - <&CP110_LABEL(clk) 1 16>;
468 - #address-cells = <1>;
469 - #size-cells = <0>;
470 - status = "disabled";
471 -
472 - sata-port@0 {
473 - reg = <0>;
474 - };
475 -
476 - sata-port@1 {
477 - reg = <1>;
478 - };
479 - };
480 -
481 - CP110_LABEL(xor0): xor@6a0000 {
482 - compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
483 - reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
484 - dma-coherent;
485 - msi-parent = <&gic_v2m0>;
486 - clock-names = "core", "reg";
487 - clocks = <&CP110_LABEL(clk) 1 8>,
488 - <&CP110_LABEL(clk) 1 14>;
489 - };
490 -
491 - CP110_LABEL(xor1): xor@6c0000 {
492 - compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
493 - reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
494 - dma-coherent;
495 - msi-parent = <&gic_v2m0>;
496 - clock-names = "core", "reg";
497 - clocks = <&CP110_LABEL(clk) 1 7>,
498 - <&CP110_LABEL(clk) 1 14>;
499 - };
500 -
501 - CP110_LABEL(spi0): spi@700600 {
502 - compatible = "marvell,armada-380-spi";
503 - reg = <0x700600 0x50>;
504 - #address-cells = <0x1>;
505 - #size-cells = <0x0>;
506 - clock-names = "core", "axi";
507 - clocks = <&CP110_LABEL(clk) 1 21>,
508 - <&CP110_LABEL(clk) 1 17>;
509 - status = "disabled";
510 - };
511 -
512 - CP110_LABEL(spi1): spi@700680 {
513 - compatible = "marvell,armada-380-spi";
514 - reg = <0x700680 0x50>;
515 - #address-cells = <1>;
516 - #size-cells = <0>;
517 - clock-names = "core", "axi";
518 - clocks = <&CP110_LABEL(clk) 1 21>,
519 - <&CP110_LABEL(clk) 1 17>;
520 - status = "disabled";
521 - };
522 -
523 - CP110_LABEL(i2c0): i2c@701000 {
524 - compatible = "marvell,mv78230-i2c";
525 - reg = <0x701000 0x20>;
526 - #address-cells = <1>;
527 - #size-cells = <0>;
528 - interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
529 - clock-names = "core", "reg";
530 - clocks = <&CP110_LABEL(clk) 1 21>,
531 - <&CP110_LABEL(clk) 1 17>;
532 - status = "disabled";
533 - };
534 -
535 - CP110_LABEL(i2c1): i2c@701100 {
536 - compatible = "marvell,mv78230-i2c";
537 - reg = <0x701100 0x20>;
538 - #address-cells = <1>;
539 - #size-cells = <0>;
540 - interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
541 - clock-names = "core", "reg";
542 - clocks = <&CP110_LABEL(clk) 1 21>,
543 - <&CP110_LABEL(clk) 1 17>;
544 - status = "disabled";
545 - };
546 -
547 - CP110_LABEL(uart0): serial@702000 {
548 - compatible = "snps,dw-apb-uart";
549 - reg = <0x702000 0x100>;
550 - reg-shift = <2>;
551 - interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
552 - reg-io-width = <1>;
553 - clock-names = "baudclk", "apb_pclk";
554 - clocks = <&CP110_LABEL(clk) 1 21>,
555 - <&CP110_LABEL(clk) 1 17>;
556 - status = "disabled";
557 - };
558 -
559 - CP110_LABEL(uart1): serial@702100 {
560 - compatible = "snps,dw-apb-uart";
561 - reg = <0x702100 0x100>;
562 - reg-shift = <2>;
563 - interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
564 - reg-io-width = <1>;
565 - clock-names = "baudclk", "apb_pclk";
566 - clocks = <&CP110_LABEL(clk) 1 21>,
567 - <&CP110_LABEL(clk) 1 17>;
568 - status = "disabled";
569 - };
570 -
571 - CP110_LABEL(uart2): serial@702200 {
572 - compatible = "snps,dw-apb-uart";
573 - reg = <0x702200 0x100>;
574 - reg-shift = <2>;
575 - interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
576 - reg-io-width = <1>;
577 - clock-names = "baudclk", "apb_pclk";
578 - clocks = <&CP110_LABEL(clk) 1 21>,
579 - <&CP110_LABEL(clk) 1 17>;
580 - status = "disabled";
581 - };
582 -
583 - CP110_LABEL(uart3): serial@702300 {
584 - compatible = "snps,dw-apb-uart";
585 - reg = <0x702300 0x100>;
586 - reg-shift = <2>;
587 - interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
588 - reg-io-width = <1>;
589 - clock-names = "baudclk", "apb_pclk";
590 - clocks = <&CP110_LABEL(clk) 1 21>,
591 - <&CP110_LABEL(clk) 1 17>;
592 - status = "disabled";
593 - };
594 -
595 - CP110_LABEL(nand_controller): nand@720000 {
596 - /*
597 - * Due to the limitation of the pins available
598 - * this controller is only usable on the CPM
599 - * for A7K and on the CPS for A8K.
600 - */
601 - compatible = "marvell,armada-8k-nand-controller",
602 - "marvell,armada370-nand-controller";
603 - reg = <0x720000 0x54>;
604 - #address-cells = <1>;
605 - #size-cells = <0>;
606 - interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
607 - clock-names = "core", "reg";
608 - clocks = <&CP110_LABEL(clk) 1 2>,
609 - <&CP110_LABEL(clk) 1 17>;
610 - marvell,system-controller = <&CP110_LABEL(syscon0)>;
611 - status = "disabled";
612 - };
613 -
614 - CP110_LABEL(trng): trng@760000 {
615 - compatible = "marvell,armada-8k-rng",
616 - "inside-secure,safexcel-eip76";
617 - reg = <0x760000 0x7d>;
618 - interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
619 - clock-names = "core", "reg";
620 - clocks = <&CP110_LABEL(clk) 1 25>,
621 - <&CP110_LABEL(clk) 1 17>;
622 - status = "okay";
623 - };
624 -
625 - CP110_LABEL(sdhci0): sdhci@780000 {
626 - compatible = "marvell,armada-cp110-sdhci";
627 - reg = <0x780000 0x300>;
628 - interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
629 - clock-names = "core", "axi";
630 - clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
631 - dma-coherent;
632 - status = "disabled";
633 - };
634 -
635 - CP110_LABEL(crypto): crypto@800000 {
636 - compatible = "inside-secure,safexcel-eip197b";
637 - reg = <0x800000 0x200000>;
638 - interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
639 - <88 IRQ_TYPE_LEVEL_HIGH>,
640 - <89 IRQ_TYPE_LEVEL_HIGH>,
641 - <90 IRQ_TYPE_LEVEL_HIGH>,
642 - <91 IRQ_TYPE_LEVEL_HIGH>,
643 - <92 IRQ_TYPE_LEVEL_HIGH>;
644 - interrupt-names = "mem", "ring0", "ring1",
645 - "ring2", "ring3", "eip";
646 - clock-names = "core", "reg";
647 - clocks = <&CP110_LABEL(clk) 1 26>,
648 - <&CP110_LABEL(clk) 1 17>;
649 - dma-coherent;
650 - };
651 - };
652 -
653 - CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
654 - compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
655 - reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
656 - <0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
657 - reg-names = "ctrl", "config";
658 - #address-cells = <3>;
659 - #size-cells = <2>;
660 - #interrupt-cells = <1>;
661 - device_type = "pci";
662 - dma-coherent;
663 - msi-parent = <&gic_v2m0>;
664 -
665 - bus-range = <0 0xff>;
666 - ranges =
667 - /* downstream I/O */
668 - <0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
669 - /* non-prefetchable memory */
670 - 0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
671 - interrupt-map-mask = <0 0 0 0>;
672 - interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
673 - interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
674 - num-lanes = <1>;
675 - clock-names = "core", "reg";
676 - clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
677 - status = "disabled";
678 - };
679 -
680 - CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
681 - compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
682 - reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
683 - <0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
684 - reg-names = "ctrl", "config";
685 - #address-cells = <3>;
686 - #size-cells = <2>;
687 - #interrupt-cells = <1>;
688 - device_type = "pci";
689 - dma-coherent;
690 - msi-parent = <&gic_v2m0>;
691 -
692 - bus-range = <0 0xff>;
693 - ranges =
694 - /* downstream I/O */
695 - <0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
696 - /* non-prefetchable memory */
697 - 0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
698 - interrupt-map-mask = <0 0 0 0>;
699 - interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
700 - interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
701 -
702 - num-lanes = <1>;
703 - clock-names = "core", "reg";
704 - clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
705 - status = "disabled";
706 - };
707 -
708 - CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
709 - compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
710 - reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
711 - <0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
712 - reg-names = "ctrl", "config";
713 - #address-cells = <3>;
714 - #size-cells = <2>;
715 - #interrupt-cells = <1>;
716 - device_type = "pci";
717 - dma-coherent;
718 - msi-parent = <&gic_v2m0>;
719 -
720 - bus-range = <0 0xff>;
721 - ranges =
722 - /* downstream I/O */
723 - <0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
724 - /* non-prefetchable memory */
725 - 0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
726 - interrupt-map-mask = <0 0 0 0>;
727 - interrupt-map = <0 0 0 0 &CP110_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
728 - interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
729 -
730 - num-lanes = <1>;
731 - clock-names = "core", "reg";
732 - clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
733 - status = "disabled";
734 - };
735 -};
736 +#undef CP11X_TYPE
737 --- /dev/null
738 +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
739 @@ -0,0 +1,579 @@
740 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
741 +/*
742 + * Copyright (C) 2016 Marvell Technology Group Ltd.
743 + *
744 + * Device Tree file for Marvell Armada CP11x.
745 + */
746 +
747 +#include <dt-bindings/interrupt-controller/mvebu-icu.h>
748 +#include <dt-bindings/thermal/thermal.h>
749 +
750 +#include "armada-common.dtsi"
751 +
752 +#define CP11X_PCIEx_IO_BASE(iface) (CP11X_PCIE_IO_BASE + (iface * 0x10000))
753 +#define CP11X_PCIEx_MEM_BASE(iface) (CP11X_PCIE_MEM_BASE + (iface * 0x1000000))
754 +#define CP11X_PCIEx_CONF_BASE(iface) (CP11X_PCIEx_MEM_BASE(iface) + 0xf00000)
755 +
756 +/ {
757 + /*
758 + * The contents of the node are defined below, in order to
759 + * save one indentation level
760 + */
761 + CP11X_NAME: CP11X_NAME { };
762 +
763 + /*
764 + * CPs only have one sensor in the thermal IC.
765 + *
766 + * The cooling maps are empty as there are no cooling devices.
767 + */
768 + thermal-zones {
769 + CP11X_LABEL(thermal_ic): CP11X_NODE_NAME(thermal-ic) {
770 + polling-delay-passive = <0>; /* Interrupt driven */
771 + polling-delay = <0>; /* Interrupt driven */
772 +
773 + thermal-sensors = <&CP11X_LABEL(thermal) 0>;
774 +
775 + trips {
776 + CP11X_LABEL(crit): crit {
777 + temperature = <100000>; /* mC degrees */
778 + hysteresis = <2000>; /* mC degrees */
779 + type = "critical";
780 + };
781 + };
782 +
783 + cooling-maps { };
784 + };
785 + };
786 +};
787 +
788 +&CP11X_NAME {
789 + #address-cells = <2>;
790 + #size-cells = <2>;
791 + compatible = "simple-bus";
792 + interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
793 + ranges;
794 +
795 + config-space@CP11X_BASE {
796 + #address-cells = <1>;
797 + #size-cells = <1>;
798 + compatible = "simple-bus";
799 + ranges = <0x0 0x0 ADDRESSIFY(CP11X_BASE) 0x2000000>;
800 +
801 + CP11X_LABEL(ethernet): ethernet@0 {
802 + compatible = "marvell,armada-7k-pp22";
803 + reg = <0x0 0x100000>, <0x129000 0xb000>;
804 + clocks = <&CP11X_LABEL(clk) 1 3>, <&CP11X_LABEL(clk) 1 9>,
805 + <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
806 + <&CP11X_LABEL(clk) 1 18>;
807 + clock-names = "pp_clk", "gop_clk",
808 + "mg_clk", "mg_core_clk", "axi_clk";
809 + marvell,system-controller = <&CP11X_LABEL(syscon0)>;
810 + status = "disabled";
811 + dma-coherent;
812 +
813 + CP11X_LABEL(eth0): eth0 {
814 + interrupts = <39 IRQ_TYPE_LEVEL_HIGH>,
815 + <43 IRQ_TYPE_LEVEL_HIGH>,
816 + <47 IRQ_TYPE_LEVEL_HIGH>,
817 + <51 IRQ_TYPE_LEVEL_HIGH>,
818 + <55 IRQ_TYPE_LEVEL_HIGH>,
819 + <59 IRQ_TYPE_LEVEL_HIGH>,
820 + <63 IRQ_TYPE_LEVEL_HIGH>,
821 + <67 IRQ_TYPE_LEVEL_HIGH>,
822 + <71 IRQ_TYPE_LEVEL_HIGH>,
823 + <129 IRQ_TYPE_LEVEL_HIGH>;
824 + interrupt-names = "hif0", "hif1", "hif2",
825 + "hif3", "hif4", "hif5", "hif6", "hif7",
826 + "hif8", "link";
827 + port-id = <0>;
828 + gop-port-id = <0>;
829 + status = "disabled";
830 + };
831 +
832 + CP11X_LABEL(eth1): eth1 {
833 + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>,
834 + <44 IRQ_TYPE_LEVEL_HIGH>,
835 + <48 IRQ_TYPE_LEVEL_HIGH>,
836 + <52 IRQ_TYPE_LEVEL_HIGH>,
837 + <56 IRQ_TYPE_LEVEL_HIGH>,
838 + <60 IRQ_TYPE_LEVEL_HIGH>,
839 + <64 IRQ_TYPE_LEVEL_HIGH>,
840 + <68 IRQ_TYPE_LEVEL_HIGH>,
841 + <72 IRQ_TYPE_LEVEL_HIGH>,
842 + <128 IRQ_TYPE_LEVEL_HIGH>;
843 + interrupt-names = "hif0", "hif1", "hif2",
844 + "hif3", "hif4", "hif5", "hif6", "hif7",
845 + "hif8", "link";
846 + port-id = <1>;
847 + gop-port-id = <2>;
848 + status = "disabled";
849 + };
850 +
851 + CP11X_LABEL(eth2): eth2 {
852 + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>,
853 + <45 IRQ_TYPE_LEVEL_HIGH>,
854 + <49 IRQ_TYPE_LEVEL_HIGH>,
855 + <53 IRQ_TYPE_LEVEL_HIGH>,
856 + <57 IRQ_TYPE_LEVEL_HIGH>,
857 + <61 IRQ_TYPE_LEVEL_HIGH>,
858 + <65 IRQ_TYPE_LEVEL_HIGH>,
859 + <69 IRQ_TYPE_LEVEL_HIGH>,
860 + <73 IRQ_TYPE_LEVEL_HIGH>,
861 + <127 IRQ_TYPE_LEVEL_HIGH>;
862 + interrupt-names = "hif0", "hif1", "hif2",
863 + "hif3", "hif4", "hif5", "hif6", "hif7",
864 + "hif8", "link";
865 + port-id = <2>;
866 + gop-port-id = <3>;
867 + status = "disabled";
868 + };
869 + };
870 +
871 + CP11X_LABEL(comphy): phy@120000 {
872 + compatible = "marvell,comphy-cp110";
873 + reg = <0x120000 0x6000>;
874 + marvell,system-controller = <&CP11X_LABEL(syscon0)>;
875 + clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
876 + <&CP11X_LABEL(clk) 1 18>;
877 + clock-names = "mg_clk", "mg_core_clk", "axi_clk";
878 + #address-cells = <1>;
879 + #size-cells = <0>;
880 +
881 + CP11X_LABEL(comphy0): phy@0 {
882 + reg = <0>;
883 + #phy-cells = <1>;
884 + };
885 +
886 + CP11X_LABEL(comphy1): phy@1 {
887 + reg = <1>;
888 + #phy-cells = <1>;
889 + };
890 +
891 + CP11X_LABEL(comphy2): phy@2 {
892 + reg = <2>;
893 + #phy-cells = <1>;
894 + };
895 +
896 + CP11X_LABEL(comphy3): phy@3 {
897 + reg = <3>;
898 + #phy-cells = <1>;
899 + };
900 +
901 + CP11X_LABEL(comphy4): phy@4 {
902 + reg = <4>;
903 + #phy-cells = <1>;
904 + };
905 +
906 + CP11X_LABEL(comphy5): phy@5 {
907 + reg = <5>;
908 + #phy-cells = <1>;
909 + };
910 + };
911 +
912 + CP11X_LABEL(mdio): mdio@12a200 {
913 + #address-cells = <1>;
914 + #size-cells = <0>;
915 + compatible = "marvell,orion-mdio";
916 + reg = <0x12a200 0x10>;
917 + clocks = <&CP11X_LABEL(clk) 1 9>, <&CP11X_LABEL(clk) 1 5>,
918 + <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
919 + status = "disabled";
920 + };
921 +
922 + CP11X_LABEL(xmdio): mdio@12a600 {
923 + #address-cells = <1>;
924 + #size-cells = <0>;
925 + compatible = "marvell,xmdio";
926 + reg = <0x12a600 0x10>;
927 + clocks = <&CP11X_LABEL(clk) 1 5>,
928 + <&CP11X_LABEL(clk) 1 6>, <&CP11X_LABEL(clk) 1 18>;
929 + status = "disabled";
930 + };
931 +
932 + CP11X_LABEL(icu): interrupt-controller@1e0000 {
933 + compatible = "marvell,cp110-icu";
934 + reg = <0x1e0000 0x440>;
935 + #address-cells = <1>;
936 + #size-cells = <1>;
937 +
938 + CP11X_LABEL(icu_nsr): interrupt-controller@10 {
939 + compatible = "marvell,cp110-icu-nsr";
940 + reg = <0x10 0x20>;
941 + #interrupt-cells = <2>;
942 + interrupt-controller;
943 + msi-parent = <&gicp>;
944 + };
945 +
946 + CP11X_LABEL(icu_sei): interrupt-controller@50 {
947 + compatible = "marvell,cp110-icu-sei";
948 + reg = <0x50 0x10>;
949 + #interrupt-cells = <2>;
950 + interrupt-controller;
951 + msi-parent = <&sei>;
952 + };
953 + };
954 +
955 + CP11X_LABEL(rtc): rtc@284000 {
956 + compatible = "marvell,armada-8k-rtc";
957 + reg = <0x284000 0x20>, <0x284080 0x24>;
958 + reg-names = "rtc", "rtc-soc";
959 + interrupts = <77 IRQ_TYPE_LEVEL_HIGH>;
960 + };
961 +
962 + CP11X_LABEL(syscon0): system-controller@440000 {
963 + compatible = "syscon", "simple-mfd";
964 + reg = <0x440000 0x2000>;
965 +
966 + CP11X_LABEL(clk): clock {
967 + compatible = "marvell,cp110-clock";
968 + #clock-cells = <2>;
969 + };
970 +
971 + CP11X_LABEL(gpio1): gpio@100 {
972 + compatible = "marvell,armada-8k-gpio";
973 + offset = <0x100>;
974 + ngpios = <32>;
975 + gpio-controller;
976 + #gpio-cells = <2>;
977 + gpio-ranges = <&CP11X_LABEL(pinctrl) 0 0 32>;
978 + interrupt-controller;
979 + interrupts = <86 IRQ_TYPE_LEVEL_HIGH>,
980 + <85 IRQ_TYPE_LEVEL_HIGH>,
981 + <84 IRQ_TYPE_LEVEL_HIGH>,
982 + <83 IRQ_TYPE_LEVEL_HIGH>;
983 + #interrupt-cells = <2>;
984 + status = "disabled";
985 + };
986 +
987 + CP11X_LABEL(gpio2): gpio@140 {
988 + compatible = "marvell,armada-8k-gpio";
989 + offset = <0x140>;
990 + ngpios = <31>;
991 + gpio-controller;
992 + #gpio-cells = <2>;
993 + gpio-ranges = <&CP11X_LABEL(pinctrl) 0 32 31>;
994 + interrupt-controller;
995 + interrupts = <82 IRQ_TYPE_LEVEL_HIGH>,
996 + <81 IRQ_TYPE_LEVEL_HIGH>,
997 + <80 IRQ_TYPE_LEVEL_HIGH>,
998 + <79 IRQ_TYPE_LEVEL_HIGH>;
999 + #interrupt-cells = <2>;
1000 + status = "disabled";
1001 + };
1002 + };
1003 +
1004 + CP11X_LABEL(syscon1): system-controller@400000 {
1005 + compatible = "syscon", "simple-mfd";
1006 + reg = <0x400000 0x1000>;
1007 + #address-cells = <1>;
1008 + #size-cells = <1>;
1009 +
1010 + CP11X_LABEL(thermal): thermal-sensor@70 {
1011 + compatible = "marvell,armada-cp110-thermal";
1012 + reg = <0x70 0x10>;
1013 + interrupts-extended =
1014 + <&CP11X_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>;
1015 + #thermal-sensor-cells = <1>;
1016 + };
1017 + };
1018 +
1019 + CP11X_LABEL(usb3_0): usb3@500000 {
1020 + compatible = "marvell,armada-8k-xhci",
1021 + "generic-xhci";
1022 + reg = <0x500000 0x4000>;
1023 + dma-coherent;
1024 + interrupts = <106 IRQ_TYPE_LEVEL_HIGH>;
1025 + clock-names = "core", "reg";
1026 + clocks = <&CP11X_LABEL(clk) 1 22>,
1027 + <&CP11X_LABEL(clk) 1 16>;
1028 + status = "disabled";
1029 + };
1030 +
1031 + CP11X_LABEL(usb3_1): usb3@510000 {
1032 + compatible = "marvell,armada-8k-xhci",
1033 + "generic-xhci";
1034 + reg = <0x510000 0x4000>;
1035 + dma-coherent;
1036 + interrupts = <105 IRQ_TYPE_LEVEL_HIGH>;
1037 + clock-names = "core", "reg";
1038 + clocks = <&CP11X_LABEL(clk) 1 23>,
1039 + <&CP11X_LABEL(clk) 1 16>;
1040 + status = "disabled";
1041 + };
1042 +
1043 + CP11X_LABEL(sata0): sata@540000 {
1044 + compatible = "marvell,armada-8k-ahci",
1045 + "generic-ahci";
1046 + reg = <0x540000 0x30000>;
1047 + dma-coherent;
1048 + interrupts = <107 IRQ_TYPE_LEVEL_HIGH>;
1049 + clocks = <&CP11X_LABEL(clk) 1 15>,
1050 + <&CP11X_LABEL(clk) 1 16>;
1051 + #address-cells = <1>;
1052 + #size-cells = <0>;
1053 + status = "disabled";
1054 +
1055 + sata-port@0 {
1056 + reg = <0>;
1057 + };
1058 +
1059 + sata-port@1 {
1060 + reg = <1>;
1061 + };
1062 + };
1063 +
1064 + CP11X_LABEL(xor0): xor@6a0000 {
1065 + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
1066 + reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
1067 + dma-coherent;
1068 + msi-parent = <&gic_v2m0>;
1069 + clock-names = "core", "reg";
1070 + clocks = <&CP11X_LABEL(clk) 1 8>,
1071 + <&CP11X_LABEL(clk) 1 14>;
1072 + };
1073 +
1074 + CP11X_LABEL(xor1): xor@6c0000 {
1075 + compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
1076 + reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
1077 + dma-coherent;
1078 + msi-parent = <&gic_v2m0>;
1079 + clock-names = "core", "reg";
1080 + clocks = <&CP11X_LABEL(clk) 1 7>,
1081 + <&CP11X_LABEL(clk) 1 14>;
1082 + };
1083 +
1084 + CP11X_LABEL(spi0): spi@700600 {
1085 + compatible = "marvell,armada-380-spi";
1086 + reg = <0x700600 0x50>;
1087 + #address-cells = <0x1>;
1088 + #size-cells = <0x0>;
1089 + clock-names = "core", "axi";
1090 + clocks = <&CP11X_LABEL(clk) 1 21>,
1091 + <&CP11X_LABEL(clk) 1 17>;
1092 + status = "disabled";
1093 + };
1094 +
1095 + CP11X_LABEL(spi1): spi@700680 {
1096 + compatible = "marvell,armada-380-spi";
1097 + reg = <0x700680 0x50>;
1098 + #address-cells = <1>;
1099 + #size-cells = <0>;
1100 + clock-names = "core", "axi";
1101 + clocks = <&CP11X_LABEL(clk) 1 21>,
1102 + <&CP11X_LABEL(clk) 1 17>;
1103 + status = "disabled";
1104 + };
1105 +
1106 + CP11X_LABEL(i2c0): i2c@701000 {
1107 + compatible = "marvell,mv78230-i2c";
1108 + reg = <0x701000 0x20>;
1109 + #address-cells = <1>;
1110 + #size-cells = <0>;
1111 + interrupts = <120 IRQ_TYPE_LEVEL_HIGH>;
1112 + clock-names = "core", "reg";
1113 + clocks = <&CP11X_LABEL(clk) 1 21>,
1114 + <&CP11X_LABEL(clk) 1 17>;
1115 + status = "disabled";
1116 + };
1117 +
1118 + CP11X_LABEL(i2c1): i2c@701100 {
1119 + compatible = "marvell,mv78230-i2c";
1120 + reg = <0x701100 0x20>;
1121 + #address-cells = <1>;
1122 + #size-cells = <0>;
1123 + interrupts = <121 IRQ_TYPE_LEVEL_HIGH>;
1124 + clock-names = "core", "reg";
1125 + clocks = <&CP11X_LABEL(clk) 1 21>,
1126 + <&CP11X_LABEL(clk) 1 17>;
1127 + status = "disabled";
1128 + };
1129 +
1130 + CP11X_LABEL(uart0): serial@702000 {
1131 + compatible = "snps,dw-apb-uart";
1132 + reg = <0x702000 0x100>;
1133 + reg-shift = <2>;
1134 + interrupts = <122 IRQ_TYPE_LEVEL_HIGH>;
1135 + reg-io-width = <1>;
1136 + clock-names = "baudclk", "apb_pclk";
1137 + clocks = <&CP11X_LABEL(clk) 1 21>,
1138 + <&CP11X_LABEL(clk) 1 17>;
1139 + status = "disabled";
1140 + };
1141 +
1142 + CP11X_LABEL(uart1): serial@702100 {
1143 + compatible = "snps,dw-apb-uart";
1144 + reg = <0x702100 0x100>;
1145 + reg-shift = <2>;
1146 + interrupts = <123 IRQ_TYPE_LEVEL_HIGH>;
1147 + reg-io-width = <1>;
1148 + clock-names = "baudclk", "apb_pclk";
1149 + clocks = <&CP11X_LABEL(clk) 1 21>,
1150 + <&CP11X_LABEL(clk) 1 17>;
1151 + status = "disabled";
1152 + };
1153 +
1154 + CP11X_LABEL(uart2): serial@702200 {
1155 + compatible = "snps,dw-apb-uart";
1156 + reg = <0x702200 0x100>;
1157 + reg-shift = <2>;
1158 + interrupts = <124 IRQ_TYPE_LEVEL_HIGH>;
1159 + reg-io-width = <1>;
1160 + clock-names = "baudclk", "apb_pclk";
1161 + clocks = <&CP11X_LABEL(clk) 1 21>,
1162 + <&CP11X_LABEL(clk) 1 17>;
1163 + status = "disabled";
1164 + };
1165 +
1166 + CP11X_LABEL(uart3): serial@702300 {
1167 + compatible = "snps,dw-apb-uart";
1168 + reg = <0x702300 0x100>;
1169 + reg-shift = <2>;
1170 + interrupts = <125 IRQ_TYPE_LEVEL_HIGH>;
1171 + reg-io-width = <1>;
1172 + clock-names = "baudclk", "apb_pclk";
1173 + clocks = <&CP11X_LABEL(clk) 1 21>,
1174 + <&CP11X_LABEL(clk) 1 17>;
1175 + status = "disabled";
1176 + };
1177 +
1178 + CP11X_LABEL(nand_controller): nand@720000 {
1179 + /*
1180 + * Due to the limitation of the pins available
1181 + * this controller is only usable on the CPM
1182 + * for A7K and on the CPS for A8K.
1183 + */
1184 + compatible = "marvell,armada-8k-nand-controller",
1185 + "marvell,armada370-nand-controller";
1186 + reg = <0x720000 0x54>;
1187 + #address-cells = <1>;
1188 + #size-cells = <0>;
1189 + interrupts = <115 IRQ_TYPE_LEVEL_HIGH>;
1190 + clock-names = "core", "reg";
1191 + clocks = <&CP11X_LABEL(clk) 1 2>,
1192 + <&CP11X_LABEL(clk) 1 17>;
1193 + marvell,system-controller = <&CP11X_LABEL(syscon0)>;
1194 + status = "disabled";
1195 + };
1196 +
1197 + CP11X_LABEL(trng): trng@760000 {
1198 + compatible = "marvell,armada-8k-rng",
1199 + "inside-secure,safexcel-eip76";
1200 + reg = <0x760000 0x7d>;
1201 + interrupts = <95 IRQ_TYPE_LEVEL_HIGH>;
1202 + clock-names = "core", "reg";
1203 + clocks = <&CP11X_LABEL(clk) 1 25>,
1204 + <&CP11X_LABEL(clk) 1 17>;
1205 + status = "okay";
1206 + };
1207 +
1208 + CP11X_LABEL(sdhci0): sdhci@780000 {
1209 + compatible = "marvell,armada-cp110-sdhci";
1210 + reg = <0x780000 0x300>;
1211 + interrupts = <27 IRQ_TYPE_LEVEL_HIGH>;
1212 + clock-names = "core", "axi";
1213 + clocks = <&CP11X_LABEL(clk) 1 4>, <&CP11X_LABEL(clk) 1 18>;
1214 + dma-coherent;
1215 + status = "disabled";
1216 + };
1217 +
1218 + CP11X_LABEL(crypto): crypto@800000 {
1219 + compatible = "inside-secure,safexcel-eip197b";
1220 + reg = <0x800000 0x200000>;
1221 + interrupts = <87 IRQ_TYPE_LEVEL_HIGH>,
1222 + <88 IRQ_TYPE_LEVEL_HIGH>,
1223 + <89 IRQ_TYPE_LEVEL_HIGH>,
1224 + <90 IRQ_TYPE_LEVEL_HIGH>,
1225 + <91 IRQ_TYPE_LEVEL_HIGH>,
1226 + <92 IRQ_TYPE_LEVEL_HIGH>;
1227 + interrupt-names = "mem", "ring0", "ring1",
1228 + "ring2", "ring3", "eip";
1229 + clock-names = "core", "reg";
1230 + clocks = <&CP11X_LABEL(clk) 1 26>,
1231 + <&CP11X_LABEL(clk) 1 17>;
1232 + dma-coherent;
1233 + };
1234 + };
1235 +
1236 + CP11X_LABEL(pcie0): pcie@CP11X_PCIE0_BASE {
1237 + compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
1238 + reg = <0 ADDRESSIFY(CP11X_PCIE0_BASE) 0 0x10000>,
1239 + <0 CP11X_PCIEx_CONF_BASE(0) 0 0x80000>;
1240 + reg-names = "ctrl", "config";
1241 + #address-cells = <3>;
1242 + #size-cells = <2>;
1243 + #interrupt-cells = <1>;
1244 + device_type = "pci";
1245 + dma-coherent;
1246 + msi-parent = <&gic_v2m0>;
1247 +
1248 + bus-range = <0 0xff>;
1249 + ranges =
1250 + /* downstream I/O */
1251 + <0x81000000 0 CP11X_PCIEx_IO_BASE(0) 0 CP11X_PCIEx_IO_BASE(0) 0 0x10000
1252 + /* non-prefetchable memory */
1253 + 0x82000000 0 CP11X_PCIEx_MEM_BASE(0) 0 CP11X_PCIEx_MEM_BASE(0) 0 0xf00000>;
1254 + interrupt-map-mask = <0 0 0 0>;
1255 + interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 22 IRQ_TYPE_LEVEL_HIGH>;
1256 + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
1257 + num-lanes = <1>;
1258 + clock-names = "core", "reg";
1259 + clocks = <&CP11X_LABEL(clk) 1 13>, <&CP11X_LABEL(clk) 1 14>;
1260 + status = "disabled";
1261 + };
1262 +
1263 + CP11X_LABEL(pcie1): pcie@CP11X_PCIE1_BASE {
1264 + compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
1265 + reg = <0 ADDRESSIFY(CP11X_PCIE1_BASE) 0 0x10000>,
1266 + <0 CP11X_PCIEx_CONF_BASE(1) 0 0x80000>;
1267 + reg-names = "ctrl", "config";
1268 + #address-cells = <3>;
1269 + #size-cells = <2>;
1270 + #interrupt-cells = <1>;
1271 + device_type = "pci";
1272 + dma-coherent;
1273 + msi-parent = <&gic_v2m0>;
1274 +
1275 + bus-range = <0 0xff>;
1276 + ranges =
1277 + /* downstream I/O */
1278 + <0x81000000 0 CP11X_PCIEx_IO_BASE(1) 0 CP11X_PCIEx_IO_BASE(1) 0 0x10000
1279 + /* non-prefetchable memory */
1280 + 0x82000000 0 CP11X_PCIEx_MEM_BASE(1) 0 CP11X_PCIEx_MEM_BASE(1) 0 0xf00000>;
1281 + interrupt-map-mask = <0 0 0 0>;
1282 + interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 24 IRQ_TYPE_LEVEL_HIGH>;
1283 + interrupts = <24 IRQ_TYPE_LEVEL_HIGH>;
1284 +
1285 + num-lanes = <1>;
1286 + clock-names = "core", "reg";
1287 + clocks = <&CP11X_LABEL(clk) 1 11>, <&CP11X_LABEL(clk) 1 14>;
1288 + status = "disabled";
1289 + };
1290 +
1291 + CP11X_LABEL(pcie2): pcie@CP11X_PCIE2_BASE {
1292 + compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
1293 + reg = <0 ADDRESSIFY(CP11X_PCIE2_BASE) 0 0x10000>,
1294 + <0 CP11X_PCIEx_CONF_BASE(2) 0 0x80000>;
1295 + reg-names = "ctrl", "config";
1296 + #address-cells = <3>;
1297 + #size-cells = <2>;
1298 + #interrupt-cells = <1>;
1299 + device_type = "pci";
1300 + dma-coherent;
1301 + msi-parent = <&gic_v2m0>;
1302 +
1303 + bus-range = <0 0xff>;
1304 + ranges =
1305 + /* downstream I/O */
1306 + <0x81000000 0 CP11X_PCIEx_IO_BASE(2) 0 CP11X_PCIEx_IO_BASE(2) 0 0x10000
1307 + /* non-prefetchable memory */
1308 + 0x82000000 0 CP11X_PCIEx_MEM_BASE(2) 0 CP11X_PCIEx_MEM_BASE(2) 0 0xf00000>;
1309 + interrupt-map-mask = <0 0 0 0>;
1310 + interrupt-map = <0 0 0 0 &CP11X_LABEL(icu_nsr) 23 IRQ_TYPE_LEVEL_HIGH>;
1311 + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
1312 +
1313 + num-lanes = <1>;
1314 + clock-names = "core", "reg";
1315 + clocks = <&CP11X_LABEL(clk) 1 12>, <&CP11X_LABEL(clk) 1 14>;
1316 + status = "disabled";
1317 + };
1318 +};
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