1 --- a/drivers/usb/host/Kconfig
2 +++ b/drivers/usb/host/Kconfig
3 @@ -350,6 +350,13 @@ config USB_OCTEON_EHCI
4 USB 2.0 device support. All CN6XXX based chips with USB are
8 + tristate "OXNAS EHCI Module"
9 + depends on USB_EHCI_HCD && ARCH_OXNAS
10 + select USB_EHCI_ROOT_HUB_TT
12 + Enable support for the OX820 SOC's on-chip EHCI controller.
16 config USB_OXU210HP_HCD
17 --- a/drivers/usb/host/Makefile
18 +++ b/drivers/usb/host/Makefile
19 @@ -48,6 +48,7 @@ obj-$(CONFIG_USB_EHCI_HCD_SPEAR) += ehci
20 obj-$(CONFIG_USB_EHCI_HCD_STI) += ehci-st.o
21 obj-$(CONFIG_USB_EHCI_EXYNOS) += ehci-exynos.o
22 obj-$(CONFIG_USB_EHCI_HCD_AT91) += ehci-atmel.o
23 +obj-$(CONFIG_USB_EHCI_OXNAS) += ehci-oxnas.o
24 obj-$(CONFIG_USB_EHCI_TEGRA) += ehci-tegra.o
25 obj-$(CONFIG_USB_EHCI_BRCMSTB) += ehci-brcm.o
27 --- a/arch/arm/boot/dts/ox820.dtsi
28 +++ b/arch/arm/boot/dts/ox820.dtsi
33 + ehci: ehci@40200100 {
34 + compatible = "plxtech,nas782x-ehci";
35 + reg = <0x40200100 0xf00>;
36 + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
37 + clocks = <&stdclk CLK_820_USBMPH>, <&pllb>, <&stdclk CLK_820_REF600>;
38 + clock-names = "usb", "refsrc", "phyref";
39 + resets = <&reset RESET_USBHS>, <&reset RESET_USBPHYA>, <&reset RESET_USBPHYB>;
40 + reset-names = "host", "phya", "phyb";
41 + oxsemi,sys-ctrl = <&sys>;
42 + /* Otherwise ref300 is used, which is derived from sata phy
43 + * in that case, usb depends on sata initialization */
44 + /* FIXME: how to make this dependency explicit ? */
45 + oxsemi,ehci_use_pllb;
46 + status = "disabled";
48 + ehci_port1: port@1 {
50 + #trigger-source-cells = <0>;
52 + ehci_port2: port@2 {
54 + #trigger-source-cells = <0>;
61 --- a/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts
62 +++ b/arch/arm/boot/dts/ox820-cloudengines-pogoplug-series-3.dts