ramips: DTS rework
[openwrt/openwrt.git] / target / linux / ramips / dts / NA930.dts
1 /dts-v1/;
2
3 #include "mt7620a.dtsi"
4
5 / {
6 compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
7 model = "Sercomm NA930";
8
9 chosen {
10 bootargs = "console=ttyS1,57600";
11 };
12
13 nand {
14 #address-cells = <1>;
15 #size-cells = <1>;
16 compatible = "mtk,mt7620-nand";
17
18 partition@0 {
19 label = "u-boot";
20 reg = <0x0 0x20000>;
21 read-only;
22 };
23
24 partition@200000 {
25 label = "factory";
26 reg = <0x200000 0x40000>;
27 read-only;
28 };
29
30 partition@240000 {
31 label = "Config";
32 reg = <0x240000 0x400000>;
33 read-only;
34 };
35
36 partition@640000 {
37 label = "firmware";
38 reg = <0x640000 0x1400000>;
39 };
40 };
41
42 gpio-keys-polled {
43 compatible = "gpio-keys-polled";
44 #address-cells = <1>;
45 #size-cells = <0>;
46 poll-interval = <20>;
47
48 reset {
49 label = "reset";
50 gpios = <&gpio0 11 1>;
51 linux,code = <0x198>;
52 };
53
54 zwave {
55 label = "zwave";
56 gpios = <&gpio0 12 1>;
57 linux,code = <0x100>;
58 };
59
60 wps {
61 label = "wps";
62 gpios = <&gpio0 14 1>;
63 linux,code = <0x211>;
64 };
65 };
66
67 gpio-leds {
68 compatible = "gpio-leds";
69
70 zwave {
71 label = "na930:blue:zwave";
72 gpios = <&gpio2 0 1>;
73 };
74
75 status {
76 label = "na930:blue:status";
77 gpios = <&gpio2 26 1>;
78 };
79
80 service {
81 label = "na930:blue:service";
82 gpios = <&gpio2 28 1>;
83 };
84
85 power {
86 label = "na930:blue:power";
87 gpios = <&gpio2 29 1>;
88 };
89 };
90
91 gpio_export {
92 compatible = "gpio-export";
93 #size-cells = <0>;
94
95 telit {
96 gpio-export,name = "telit";
97 gpio-export,output = <1>;
98 gpios = <&gpio0 13 0>;
99 };
100 };
101 };
102
103 &pinctrl {
104 state_default: pinctrl0 {
105 gpio {
106 ralink,group = "i2c", "rgmii2", "spi", "ephy";
107 ralink,function = "gpio";
108 };
109
110 uartf_gpio {
111 ralink,group = "uartf";
112 ralink,function = "gpio uartf";
113 };
114 };
115 };
116
117 &uart {
118 status = "okay";
119 };
120
121 &gpio1 {
122 status = "okay";
123 };
124
125 &gpio2 {
126 status = "okay";
127 };
128
129 &ethernet {
130 status = "okay";
131 pinctrl-names = "default";
132 pinctrl-0 = <&rgmii1_pins &mdio_pins>;
133 mediatek,portmap = "llllw";
134
135 port@4 {
136 status = "okay";
137 phy-handle = <&phy4>;
138 phy-mode = "rgmii";
139 };
140
141 port@5 {
142 status = "okay";
143 phy-handle = <&phy5>;
144 phy-mode = "rgmii";
145 };
146
147 mdio-bus {
148 status = "okay";
149
150 phy4: ethernet-phy@4 {
151 reg = <4>;
152 phy-mode = "rgmii";
153 };
154
155 phy5: ethernet-phy@5 {
156 reg = <5>;
157 phy-mode = "rgmii";
158 };
159 };
160 };
161
162 &gsw {
163 mediatek,port4 = "gmac";
164 };
165
166 &ehci {
167 status = "okay";
168 };
169
170 &ohci {
171 status = "okay";
172 };