target/linux/ramips/dts/mt7621_asus_rt-acx5p.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 /dts-v1/;
   3
   4 #include "mt7621.dtsi"
   5
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8
   9 / {
  10         aliases {
  11                 led-boot = &led_power;
  12                 led-failsafe = &led_power;
  13                 led-running = &led_power;
  14                 led-upgrade = &led_power;
  15         };
  16
  17         chosen {
  18                 bootargs = "console=ttyS0,57600";
  19         };
  20
  21         palmbus: palmbus@1E000000 {
  22                 i2c@900 {
  23                         status = "okay";
  24                 };
  25         };
  26
  27         keys {
  28                 compatible = "gpio-keys";
  29
  30                 reset {
  31                         label = "reset";
  32                         gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
  33                         linux,code = <KEY_RESTART>;
  34                 };
  35
  36                 wps {
  37                         label = "wps";
  38                         gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  39                         linux,code = <KEY_WPS_BUTTON>;
  40                 };
  41         };
  42
  43         leds {
  44                 compatible = "gpio-leds";
  45
  46                 led_power: power {
  47                         label = "rt-ac85p:blue:power";
  48                         gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
  49                 };
  50                 wlan2g {
  51                         label = "rt-ac85p:blue:wlan2g";
  52                         gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
  53                         linux,default-trigger = "phy0radio";
  54                 };
  55
  56                 wlan5g {
  57                         label = "rt-ac85p:blue:wlan5g";
  58                         gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
  59                         linux,default-trigger = "phy1radio";
  60                 };
  61         };
  62 };
  63
  64 &sdhci {
  65         status = "okay";
  66 };
  67
  68 &nand {
  69         status = "okay";
  70
  71         partitions {
  72                 compatible = "fixed-partitions";
  73                 #address-cells = <1>;
  74                 #size-cells = <1>;
  75
  76                 partition@0 {
  77                         label = "u-boot";
  78                         reg = <0x0 0xe0000>;
  79                         read-only;
  80                 };
  81
  82                 partition@e0000 {
  83                         label = "u-boot-env";
  84                         reg = <0xe0000 0x100000>;
  85                         read-only;
  86                 };
  87
  88                 factory: partition@1e0000 {
  89                         label = "factory";
  90                         reg = <0x1e0000 0x100000>;
  91                         read-only;
  92                 };
  93
  94                 factory2: partition@2e0000 {
  95                         label = "factory2";
  96                         reg = <0x2e0000 0x100000>;
  97                         read-only;
  98                 };
  99
 100                 partition@3e0000 {
 101                         label = "kernel";
 102                         reg = <0x3e0000 0x400000>;
 103                 };
 104
 105                 partition@7e0000 {
 106                         label = "ubi";
 107                         reg = <0x7e0000 0x2e00000>;
 108                 };
 109
 110                 partition@35e0000 {
 111                         label = "firmware2";
 112                         reg = <0x35e0000 0x3200000>;
 113                 };
 114         };
 115 };
 116
 117 &pcie {
 118         status = "okay";
 119 };
 120
 121 &pcie0 {
 122         wifi0: wifi@0,0 {
 123                 compatible = "pci14c3,7615";
 124                 reg = <0x0000 0 0 0 0>;
 125                 mediatek,mtd-eeprom = <&factory 0x0000>;
 126                 ieee80211-freq-limit = <2400000 2500000>;
 127         };
 128 };
 129
 130 &pcie1 {
 131         wifi1: wifi@0,0 {
 132                 compatible = "pci14c3,7615";
 133                 reg = <0x0000 0 0 0 0>;
 134                 mediatek,mtd-eeprom = <&factory 0x8000>;
 135                 ieee80211-freq-limit = <5000000 6000000>;
 136         };
 137 };
 138
 139 &ethernet {
 140         mtd-mac-address = <&factory 0xe000>;
 141         mediatek,portmap = "wllll";
 142         port@5 {
 143                 status = "disabled";
 144         };
 145 };
 146
 147 &i2c {
 148         status = "disabled";
 149 };
 150
 151 &pinctrl {
 152         state_default: pinctrl0 {
 153                 gpio {
 154                         ralink,group = "uart2", "uart3", "i2c";
 155                         ralink,function = "gpio";
 156                 };
 157         };
 158 };