ramips: correct the PCIe port number for Zbtlink ZBT-WE1326
[openwrt/staging/stintel.git] / target / linux / ramips / dts / mt7621_zbtlink_zbt-we1326.dts
1 #include "mt7621.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "zbtlink,zbt-we1326", "mediatek,mt7621-soc";
8 model = "Zbtlink ZBT-WE1326";
9
10 aliases {
11 label-mac-device = &wifi1;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 };
17
18 keys {
19 compatible = "gpio-keys";
20
21 reset {
22 label = "reset";
23 gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
24 linux,code = <KEY_RESTART>;
25 };
26 };
27 };
28
29 &state_default {
30 gpio {
31 groups = "wdt";
32 function = "gpio";
33 };
34 };
35
36 &spi0 {
37 status = "okay";
38
39 flash@0 {
40 compatible = "jedec,spi-nor";
41 reg = <0>;
42 spi-max-frequency = <10000000>;
43
44 partitions {
45 compatible = "fixed-partitions";
46 #address-cells = <1>;
47 #size-cells = <1>;
48
49 partition@0 {
50 label = "u-boot";
51 reg = <0x0 0x30000>;
52 read-only;
53 };
54
55 partition@30000 {
56 label = "u-boot-env";
57 reg = <0x30000 0x10000>;
58 read-only;
59 };
60
61 factory: partition@40000 {
62 label = "factory";
63 reg = <0x40000 0x10000>;
64 read-only;
65 };
66
67 partition@50000 {
68 compatible = "denx,uimage";
69 label = "firmware";
70 reg = <0x50000 0xfb0000>;
71 };
72 };
73 };
74 };
75
76 &gmac0 {
77 nvmem-cells = <&macaddr_factory_e000>;
78 nvmem-cell-names = "mac-address";
79 };
80
81 &gmac1 {
82 status = "okay";
83 label = "wan";
84 phy-handle = <&ethphy4>;
85
86 nvmem-cells = <&macaddr_factory_e006>;
87 nvmem-cell-names = "mac-address";
88 };
89
90 &mdio {
91 ethphy4: ethernet-phy@4 {
92 reg = <4>;
93 };
94 };
95
96 &switch0 {
97 ports {
98 port@0 {
99 status = "okay";
100 label = "lan1";
101 };
102
103 port@1 {
104 status = "okay";
105 label = "lan2";
106 };
107
108 port@2 {
109 status = "okay";
110 label = "lan3";
111 };
112
113 port@3 {
114 status = "okay";
115 label = "lan4";
116 };
117 };
118 };
119
120 &pcie {
121 status = "okay";
122 };
123
124 &pcie1 {
125 wifi@0,0 {
126 compatible = "mediatek,mt76";
127 reg = <0x0000 0 0 0 0>;
128 mediatek,mtd-eeprom = <&factory 0x8000>;
129 ieee80211-freq-limit = <5000000 6000000>;
130
131 led {
132 led-sources = <2>;
133 led-active-low;
134 };
135 };
136 };
137
138 &pcie2 {
139 wifi1: wifi@0,0 {
140 compatible = "mediatek,mt76";
141 reg = <0x0000 0 0 0 0>;
142 mediatek,mtd-eeprom = <&factory 0x0000>;
143 ieee80211-freq-limit = <2400000 2500000>;
144
145 led {
146 led-sources = <0>;
147 led-active-low;
148 };
149 };
150 };
151
152 &sdhci {
153 status = "okay";
154 };
155
156 &factory {
157 compatible = "nvmem-cells";
158 #address-cells = <1>;
159 #size-cells = <1>;
160
161 macaddr_factory_e000: macaddr@e000 {
162 reg = <0xe000 0x6>;
163 };
164
165 macaddr_factory_e006: macaddr@e006 {
166 reg = <0xe006 0x6>;
167 };
168 };