target/linux/ramips/files/arch/mips/pci/pci-rt288x.c

   1 #include <linux/types.h>
   2 #include <linux/pci.h>
   3 #include <linux/io.h>
   4 #include <linux/init.h>
   5
   6 #include <asm/mach-ralink/rt288x.h>
   7 #include <asm/mach-ralink/rt288x_pci.h>
   8
   9 #ifdef CONFIG_PCI
  10
  11 extern int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
  12 extern int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
  13
  14 struct pci_ops rt2880_pci_ops = {
  15         .read =  pci_config_read,
  16         .write = pci_config_write,
  17 };
  18
  19 static struct resource pci_io_resource = {
  20         .name = "pci MEM space",
  21         .start = 0x20000000,
  22         .end = 0x2FFFFFFF,
  23         .flags = IORESOURCE_MEM,
  24 };
  25
  26 static struct resource pci_mem_resource = {
  27         .name = "pci IO space",
  28         .start = 0x00460000,
  29         .end = 0x0046FFFF,
  30         .flags = IORESOURCE_IO,
  31 };
  32
  33 struct pci_controller rt2880_controller = {
  34         .pci_ops = &rt2880_pci_ops,
  35         .mem_resource = &pci_io_resource,
  36         .io_resource = &pci_mem_resource,
  37         .mem_offset = 0x00000000UL,
  38         .io_offset = 0x00000000UL,
  39 };
  40
  41 void inline
  42 read_config(unsigned long bus, unsigned long dev, unsigned long func,
  43         unsigned long reg, unsigned long *val)
  44 {
  45         unsigned long address =
  46                 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
  47         writel(address, RT2880_PCI_CONFIG_ADDR);
  48         *val = readl(RT2880_PCI_CONFIG_DATA);
  49 }
  50
  51 void inline
  52 write_config(unsigned long bus, unsigned long dev, unsigned long func,
  53         unsigned long reg, unsigned long val)
  54 {
  55         unsigned long address =
  56                 (bus << 16) | (dev << 11) | (func << 8) | (reg & 0xfc) | 0x80000000;
  57         writel(address, RT2880_PCI_CONFIG_ADDR);
  58         writel(val, RT2880_PCI_CONFIG_DATA);
  59 }
  60
  61 int __init
  62 pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  63 {
  64         u16 cmd;
  65         unsigned long val;
  66         int irq = -1;
  67         if (dev->bus->number != 0)
  68                 return 0;
  69
  70         switch(PCI_SLOT(dev->devfn))
  71         {
  72         case 0x00:
  73                 write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
  74                 read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
  75                 break;
  76         case 0x11:
  77                 irq = RT288X_CPU_IRQ_PCI;
  78                 break;
  79         default:
  80                 printk("%s:%s[%d] trying to alloc unknown pci irq\n", __FILE__, __func__, __LINE__);
  81                 BUG();
  82                 break;
  83         }
  84
  85         pci_write_config_byte((struct pci_dev*)dev, PCI_CACHE_LINE_SIZE, 0x14);
  86         pci_write_config_byte((struct pci_dev*)dev, PCI_LATENCY_TIMER, 0xFF);
  87         pci_read_config_word((struct pci_dev*)dev, PCI_COMMAND, &cmd);
  88         cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  89                 PCI_COMMAND_INVALIDATE | PCI_COMMAND_FAST_BACK | PCI_COMMAND_SERR |
  90                 PCI_COMMAND_WAIT | PCI_COMMAND_PARITY;
  91         pci_write_config_word((struct pci_dev*)dev, PCI_COMMAND, cmd);
  92         pci_write_config_byte((struct pci_dev*)dev, PCI_INTERRUPT_LINE, dev->irq);
  93         return irq;
  94 }
  95
  96 int
  97 init_rt2880pci(void)
  98 {
  99         unsigned long val = 0;
 100         int i;
 101         writel(0, RT2880_PCI_PCICFG_ADDR);
 102         for(i = 0; i < 0xfffff; i++) {}
 103         writel(0x79, RT2880_PCI_ARBCTL);
 104         writel(0x07FF0001, RT2880_PCI_BAR0SETUP_ADDR);
 105         writel(RT2880_PCI_SLOT1_BASE, RT2880_PCI_MEMBASE);
 106         writel(0x00460000, RT2880_PCI_IOBASE);
 107         writel(0x08000000, RT2880_PCI_IMBASEBAR0_ADDR);
 108         writel(0x08021814, RT2880_PCI_ID);
 109         writel(0x00800001, RT2880_PCI_CLASS);
 110         writel(0x28801814, RT2880_PCI_SUBID);
 111         writel(0x000c0000, RT2880_PCI_PCIMSK_ADDR);
 112         write_config(0, 0, 0, PCI_BASE_ADDRESS_0, 0x08000000);
 113         read_config(0, 0, 0, PCI_BASE_ADDRESS_0, &val);
 114         register_pci_controller(&rt2880_controller);
 115         return 0;
 116 }
 117
 118 int
 119 pcibios_plat_dev_init(struct pci_dev *dev)
 120 {
 121         return 0;
 122 }
 123
 124 struct pci_fixup pcibios_fixups[] = {
 125         {0}
 126 };
 127
 128 arch_initcall(init_rt2880pci);
 129
 130 #endif