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ramips: ethernet: ralink: move reset of the esw into the esw instead of fe
[openwrt/staging/wigyori.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3050.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #include <linux/switch.h>
24 #include <linux/reset.h>
25
26 #include "mtk_eth_soc.h"
27
28 /* HW limitations for this switch:
29 * - No large frame support (PKT_MAX_LEN at most 1536)
30 * - Can't have untagged vlan and tagged vlan on one port at the same time,
31 * though this might be possible using the undocumented PPE.
32 */
33
34 #define RT305X_ESW_REG_ISR 0x00
35 #define RT305X_ESW_REG_IMR 0x04
36 #define RT305X_ESW_REG_FCT0 0x08
37 #define RT305X_ESW_REG_PFC1 0x14
38 #define RT305X_ESW_REG_ATS 0x24
39 #define RT305X_ESW_REG_ATS0 0x28
40 #define RT305X_ESW_REG_ATS1 0x2c
41 #define RT305X_ESW_REG_ATS2 0x30
42 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
43 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
44 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
45 #define RT305X_ESW_REG_POA 0x80
46 #define RT305X_ESW_REG_FPA 0x84
47 #define RT305X_ESW_REG_SOCPC 0x8c
48 #define RT305X_ESW_REG_POC0 0x90
49 #define RT305X_ESW_REG_POC1 0x94
50 #define RT305X_ESW_REG_POC2 0x98
51 #define RT305X_ESW_REG_SGC 0x9c
52 #define RT305X_ESW_REG_STRT 0xa0
53 #define RT305X_ESW_REG_PCR0 0xc0
54 #define RT305X_ESW_REG_PCR1 0xc4
55 #define RT305X_ESW_REG_FPA2 0xc8
56 #define RT305X_ESW_REG_FCT2 0xcc
57 #define RT305X_ESW_REG_SGC2 0xe4
58 #define RT305X_ESW_REG_P0LED 0xa4
59 #define RT305X_ESW_REG_P1LED 0xa8
60 #define RT305X_ESW_REG_P2LED 0xac
61 #define RT305X_ESW_REG_P3LED 0xb0
62 #define RT305X_ESW_REG_P4LED 0xb4
63 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
64 #define RT305X_ESW_REG_P1PC 0xec
65 #define RT305X_ESW_REG_P2PC 0xf0
66 #define RT305X_ESW_REG_P3PC 0xf4
67 #define RT305X_ESW_REG_P4PC 0xf8
68 #define RT305X_ESW_REG_P5PC 0xfc
69
70 #define RT305X_ESW_LED_LINK 0
71 #define RT305X_ESW_LED_100M 1
72 #define RT305X_ESW_LED_DUPLEX 2
73 #define RT305X_ESW_LED_ACTIVITY 3
74 #define RT305X_ESW_LED_COLLISION 4
75 #define RT305X_ESW_LED_LINKACT 5
76 #define RT305X_ESW_LED_DUPLCOLL 6
77 #define RT305X_ESW_LED_10MACT 7
78 #define RT305X_ESW_LED_100MACT 8
79 /* Additional led states not in datasheet: */
80 #define RT305X_ESW_LED_BLINK 10
81 #define RT305X_ESW_LED_ON 12
82
83 #define RT305X_ESW_LINK_S 25
84 #define RT305X_ESW_DUPLEX_S 9
85 #define RT305X_ESW_SPD_S 0
86
87 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
88 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
89 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
90
91 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
92
93 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
94 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
95
96 #define RT305X_ESW_PVIDC_PVID_M 0xfff
97 #define RT305X_ESW_PVIDC_PVID_S 12
98
99 #define RT305X_ESW_VLANI_VID_M 0xfff
100 #define RT305X_ESW_VLANI_VID_S 12
101
102 #define RT305X_ESW_VMSC_MSC_M 0xff
103 #define RT305X_ESW_VMSC_MSC_S 8
104
105 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
106 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
107 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
108 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
109
110 #define RT305X_ESW_POC0_EN_BP_S 0
111 #define RT305X_ESW_POC0_EN_FC_S 8
112 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
113 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
114 #define RT305X_ESW_POC0_DIS_PORT_S 23
115
116 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
117 #define RT305X_ESW_POC2_UNTAG_EN_S 0
118 #define RT305X_ESW_POC2_ENAGING_S 8
119 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
120
121 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
122 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
123 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
124 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
125
126 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
127 #define RT305X_ESW_PFC1_EN_VLAN_S 16
128 #define RT305X_ESW_PFC1_EN_TOS_S 24
129
130 #define RT305X_ESW_VLAN_NONE 0xfff
131
132 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
133 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
134
135 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
136 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
137
138 #define RT305X_ESW_POA_LINK_MASK 0x1f
139 #define RT305X_ESW_POA_LINK_SHIFT 25
140
141 #define RT305X_ESW_PORT_ST_CHG BIT(26)
142 #define RT305X_ESW_PORT0 0
143 #define RT305X_ESW_PORT1 1
144 #define RT305X_ESW_PORT2 2
145 #define RT305X_ESW_PORT3 3
146 #define RT305X_ESW_PORT4 4
147 #define RT305X_ESW_PORT5 5
148 #define RT305X_ESW_PORT6 6
149
150 #define RT305X_ESW_PORTS_NONE 0
151
152 #define RT305X_ESW_PMAP_LLLLLL 0x3f
153 #define RT305X_ESW_PMAP_LLLLWL 0x2f
154 #define RT305X_ESW_PMAP_WLLLLL 0x3e
155
156 #define RT305X_ESW_PORTS_INTERNAL \
157 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
158 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
159 BIT(RT305X_ESW_PORT4))
160
161 #define RT305X_ESW_PORTS_NOCPU \
162 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
163
164 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
165
166 #define RT305X_ESW_PORTS_ALL \
167 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
168
169 #define RT305X_ESW_NUM_VLANS 16
170 #define RT305X_ESW_NUM_VIDS 4096
171 #define RT305X_ESW_NUM_PORTS 7
172 #define RT305X_ESW_NUM_LANWAN 6
173 #define RT305X_ESW_NUM_LEDS 5
174
175 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
176 #define RT5350_EWS_REG_LED_POLARITY 0x168
177
178 enum {
179 /* Global attributes. */
180 RT305X_ESW_ATTR_ENABLE_VLAN,
181 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
182 RT305X_ESW_ATTR_BC_STATUS,
183 RT305X_ESW_ATTR_LED_FREQ,
184 /* Port attributes. */
185 RT305X_ESW_ATTR_PORT_DISABLE,
186 RT305X_ESW_ATTR_PORT_DOUBLETAG,
187 RT305X_ESW_ATTR_PORT_UNTAG,
188 RT305X_ESW_ATTR_PORT_LED,
189 RT305X_ESW_ATTR_PORT_LAN,
190 RT305X_ESW_ATTR_PORT_RECV_BAD,
191 RT305X_ESW_ATTR_PORT_RECV_GOOD,
192 RT5350_ESW_ATTR_PORT_TR_BAD,
193 RT5350_ESW_ATTR_PORT_TR_GOOD,
194 };
195
196 struct esw_port {
197 bool disable;
198 bool doubletag;
199 bool untag;
200 u8 led;
201 u16 pvid;
202 };
203
204 struct esw_vlan {
205 u8 ports;
206 u16 vid;
207 };
208
209 enum {
210 RT305X_ESW_VLAN_CONFIG_NONE = 0,
211 RT305X_ESW_VLAN_CONFIG_LLLLW,
212 RT305X_ESW_VLAN_CONFIG_WLLLL,
213 };
214
215 struct rt305x_esw {
216 struct device *dev;
217 void __iomem *base;
218 int irq;
219
220 /* Protects against concurrent register r/w operations. */
221 spinlock_t reg_rw_lock;
222
223 unsigned char port_map;
224 unsigned char port_disable;
225 unsigned int reg_initval_fct2;
226 unsigned int reg_initval_fpa2;
227 unsigned int reg_led_polarity;
228
229 struct switch_dev swdev;
230 bool global_vlan_enable;
231 bool alt_vlan_disable;
232 int bc_storm_protect;
233 int led_frequency;
234 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
235 struct esw_port ports[RT305X_ESW_NUM_PORTS];
236 struct reset_control *rst_esw;
237 struct reset_control *rst_ephy;
238
239 };
240
241 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
242 {
243 __raw_writel(val, esw->base + reg);
244 }
245
246 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
247 {
248 return __raw_readl(esw->base + reg);
249 }
250
251 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
252 unsigned long mask, unsigned long val)
253 {
254 unsigned long t;
255
256 t = __raw_readl(esw->base + reg) & ~mask;
257 __raw_writel(t | val, esw->base + reg);
258 }
259
260 static void esw_reset(struct rt305x_esw *esw)
261 {
262 if (!esw->rst_esw)
263 return;
264
265 reset_control_assert(esw->rst_esw);
266 usleep_range(60, 120);
267 reset_control_deassert(esw->rst_esw);
268 /* the esw takes long to reset otherwise the board hang */
269 msleep(10);
270 }
271
272 static void esw_reset_ephy(struct rt305x_esw *esw)
273 {
274 if (!esw->rst_ephy)
275 return;
276
277 reset_control_assert(esw->rst_ephy);
278 usleep_range(60, 120);
279 reset_control_deassert(esw->rst_ephy);
280 usleep_range(60, 120);
281 }
282
283 static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
284 unsigned long mask, unsigned long val)
285 {
286 unsigned long flags;
287
288 spin_lock_irqsave(&esw->reg_rw_lock, flags);
289 esw_rmw_raw(esw, reg, mask, val);
290 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
291 }
292
293 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
294 u32 phy_register, u32 write_data)
295 {
296 unsigned long t_start = jiffies;
297 int ret = 0;
298
299 while (1) {
300 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
301 RT305X_ESW_PCR1_WT_DONE))
302 break;
303 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
304 ret = 1;
305 goto out;
306 }
307 }
308
309 write_data &= 0xffff;
310 esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
311 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
312 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
313 RT305X_ESW_REG_PCR0);
314
315 t_start = jiffies;
316 while (1) {
317 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
318 RT305X_ESW_PCR1_WT_DONE)
319 break;
320
321 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
322 ret = 1;
323 break;
324 }
325 }
326 out:
327 if (ret)
328 dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
329 return ret;
330 }
331
332 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
333 {
334 unsigned s;
335 unsigned val;
336
337 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
338 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
339 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
340
341 return val;
342 }
343
344 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
345 {
346 unsigned s;
347
348 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
349 esw_rmw(esw,
350 RT305X_ESW_REG_VLANI(vlan / 2),
351 RT305X_ESW_VLANI_VID_M << s,
352 (vid & RT305X_ESW_VLANI_VID_M) << s);
353 }
354
355 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
356 {
357 unsigned s, val;
358
359 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
360 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
361 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
362 }
363
364 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
365 {
366 unsigned s;
367
368 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
369 esw_rmw(esw,
370 RT305X_ESW_REG_PVIDC(port / 2),
371 RT305X_ESW_PVIDC_PVID_M << s,
372 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
373 }
374
375 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
376 {
377 unsigned s, val;
378
379 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
380 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
381 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
382
383 return val;
384 }
385
386 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
387 {
388 unsigned s;
389
390 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
391 esw_rmw(esw,
392 RT305X_ESW_REG_VMSC(vlan / 4),
393 RT305X_ESW_VMSC_MSC_M << s,
394 (msc & RT305X_ESW_VMSC_MSC_M) << s);
395 }
396
397 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
398 {
399 unsigned reg;
400
401 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
402 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
403 RT305X_ESW_POC0_DIS_PORT_M;
404 }
405
406 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
407 {
408 unsigned old_mask;
409 unsigned enable_mask;
410 unsigned changed;
411 int i;
412
413 old_mask = esw_get_port_disable(esw);
414 changed = old_mask ^ disable_mask;
415 enable_mask = old_mask & disable_mask;
416
417 /* enable before writing to MII */
418 esw_rmw(esw, RT305X_ESW_REG_POC0,
419 (RT305X_ESW_POC0_DIS_PORT_M <<
420 RT305X_ESW_POC0_DIS_PORT_S),
421 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
422
423 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
424 if (!(changed & (1 << i)))
425 continue;
426 if (disable_mask & (1 << i)) {
427 /* disable */
428 rt305x_mii_write(esw, i, MII_BMCR,
429 BMCR_PDOWN);
430 } else {
431 /* enable */
432 rt305x_mii_write(esw, i, MII_BMCR,
433 BMCR_FULLDPLX |
434 BMCR_ANENABLE |
435 BMCR_ANRESTART |
436 BMCR_SPEED100);
437 }
438 }
439
440 /* disable after writing to MII */
441 esw_rmw(esw, RT305X_ESW_REG_POC0,
442 (RT305X_ESW_POC0_DIS_PORT_M <<
443 RT305X_ESW_POC0_DIS_PORT_S),
444 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
445 }
446
447 static void esw_set_gsc(struct rt305x_esw *esw)
448 {
449 esw_rmw(esw, RT305X_ESW_REG_SGC,
450 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
451 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
452 esw_rmw(esw, RT305X_ESW_REG_SGC,
453 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
454 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
455 }
456
457 static int esw_apply_config(struct switch_dev *dev);
458
459 static void esw_hw_init(struct rt305x_esw *esw)
460 {
461 int i;
462 u8 port_disable = 0;
463 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
464
465 esw_reset(esw);
466
467 /* vodoo from original driver */
468 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
469 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
470 /* Port priority 1 for all ports, vlan enabled. */
471 esw_w32(esw, 0x00005555 |
472 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
473 RT305X_ESW_REG_PFC1);
474
475 /* Enable all ports, Back Pressure and Flow Control */
476 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
477 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
478 RT305X_ESW_REG_POC0);
479
480 /* Enable Aging, and VLAN TAG removal */
481 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
482 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
483 RT305X_ESW_REG_POC2);
484
485 if (esw->reg_initval_fct2)
486 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
487 else
488 esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
489
490 /* 300s aging timer, max packet len 1536, broadcast storm prevention
491 * disabled, disable collision abort, mac xor48 hash, 10 packet back
492 * pressure jam, GMII disable was_transmit, back pressure disabled,
493 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
494 * ports.
495 */
496 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
497
498 /* Setup SoC Port control register */
499 esw_w32(esw,
500 (RT305X_ESW_SOCPC_CRC_PADDING |
501 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
502 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
503 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
504 RT305X_ESW_REG_SOCPC);
505
506 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
507 * turbo mii off, rgmi 3.3v off
508 * port5: disabled
509 * port6: enabled, gige, full-duplex, rx/tx-flow-control
510 */
511 if (esw->reg_initval_fpa2)
512 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
513 else
514 esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
515 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
516
517 /* Force Link/Activity on ports */
518 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
519 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
520 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
521 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
522 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
523
524 /* Copy disabled port configuration from device tree setup */
525 port_disable = esw->port_disable;
526
527 /* Disable nonexistent ports by reading the switch config
528 * after having enabled all possible ports above
529 */
530 port_disable |= esw_get_port_disable(esw);
531
532 for (i = 0; i < 6; i++)
533 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
534
535 if (ralink_soc == RT305X_SOC_RT3352) {
536 esw_reset_ephy(esw);
537
538 rt305x_mii_write(esw, 0, 31, 0x8000);
539 for (i = 0; i < 5; i++) {
540 if (esw->ports[i].disable) {
541 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
542 } else {
543 rt305x_mii_write(esw, i, MII_BMCR,
544 BMCR_FULLDPLX |
545 BMCR_ANENABLE |
546 BMCR_SPEED100);
547 }
548 /* TX10 waveform coefficient LSB=0 disable PHY */
549 rt305x_mii_write(esw, i, 26, 0x1601);
550 /* TX100/TX10 AD/DA current bias */
551 rt305x_mii_write(esw, i, 29, 0x7016);
552 /* TX100 slew rate control */
553 rt305x_mii_write(esw, i, 30, 0x0038);
554 }
555
556 /* select global register */
557 rt305x_mii_write(esw, 0, 31, 0x0);
558 /* enlarge agcsel threshold 3 and threshold 2 */
559 rt305x_mii_write(esw, 0, 1, 0x4a40);
560 /* enlarge agcsel threshold 5 and threshold 4 */
561 rt305x_mii_write(esw, 0, 2, 0x6254);
562 /* enlarge agcsel threshold */
563 rt305x_mii_write(esw, 0, 3, 0xa17f);
564 rt305x_mii_write(esw, 0, 12, 0x7eaa);
565 /* longer TP_IDL tail length */
566 rt305x_mii_write(esw, 0, 14, 0x65);
567 /* increased squelch pulse count threshold. */
568 rt305x_mii_write(esw, 0, 16, 0x0684);
569 /* set TX10 signal amplitude threshold to minimum */
570 rt305x_mii_write(esw, 0, 17, 0x0fe0);
571 /* set squelch amplitude to higher threshold */
572 rt305x_mii_write(esw, 0, 18, 0x40ba);
573 /* tune TP_IDL tail and head waveform, enable power
574 * down slew rate control
575 */
576 rt305x_mii_write(esw, 0, 22, 0x253f);
577 /* set PLL/Receive bias current are calibrated */
578 rt305x_mii_write(esw, 0, 27, 0x2fda);
579 /* change PLL/Receive bias current to internal(RT3350) */
580 rt305x_mii_write(esw, 0, 28, 0xc410);
581 /* change PLL bias current to internal(RT3052_MP3) */
582 rt305x_mii_write(esw, 0, 29, 0x598b);
583 /* select local register */
584 rt305x_mii_write(esw, 0, 31, 0x8000);
585 } else if (ralink_soc == RT305X_SOC_RT5350) {
586 esw_reset_ephy(esw);
587
588 /* set the led polarity */
589 esw_w32(esw, esw->reg_led_polarity & 0x1F,
590 RT5350_EWS_REG_LED_POLARITY);
591
592 /* local registers */
593 rt305x_mii_write(esw, 0, 31, 0x8000);
594 for (i = 0; i < 5; i++) {
595 if (esw->ports[i].disable) {
596 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
597 } else {
598 rt305x_mii_write(esw, i, MII_BMCR,
599 BMCR_FULLDPLX |
600 BMCR_ANENABLE |
601 BMCR_SPEED100);
602 }
603 /* TX10 waveform coefficient LSB=0 disable PHY */
604 rt305x_mii_write(esw, i, 26, 0x1601);
605 /* TX100/TX10 AD/DA current bias */
606 rt305x_mii_write(esw, i, 29, 0x7015);
607 /* TX100 slew rate control */
608 rt305x_mii_write(esw, i, 30, 0x0038);
609 }
610
611 /* global registers */
612 rt305x_mii_write(esw, 0, 31, 0x0);
613 /* enlarge agcsel threshold 3 and threshold 2 */
614 rt305x_mii_write(esw, 0, 1, 0x4a40);
615 /* enlarge agcsel threshold 5 and threshold 4 */
616 rt305x_mii_write(esw, 0, 2, 0x6254);
617 /* enlarge agcsel threshold 6 */
618 rt305x_mii_write(esw, 0, 3, 0xa17f);
619 rt305x_mii_write(esw, 0, 12, 0x7eaa);
620 /* longer TP_IDL tail length */
621 rt305x_mii_write(esw, 0, 14, 0x65);
622 /* increased squelch pulse count threshold. */
623 rt305x_mii_write(esw, 0, 16, 0x0684);
624 /* set TX10 signal amplitude threshold to minimum */
625 rt305x_mii_write(esw, 0, 17, 0x0fe0);
626 /* set squelch amplitude to higher threshold */
627 rt305x_mii_write(esw, 0, 18, 0x40ba);
628 /* tune TP_IDL tail and head waveform, enable power
629 * down slew rate control
630 */
631 rt305x_mii_write(esw, 0, 22, 0x253f);
632 /* set PLL/Receive bias current are calibrated */
633 rt305x_mii_write(esw, 0, 27, 0x2fda);
634 /* change PLL/Receive bias current to internal(RT3350) */
635 rt305x_mii_write(esw, 0, 28, 0xc410);
636 /* change PLL bias current to internal(RT3052_MP3) */
637 rt305x_mii_write(esw, 0, 29, 0x598b);
638 /* select local register */
639 rt305x_mii_write(esw, 0, 31, 0x8000);
640 } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
641 int i;
642
643 esw_reset_ephy(esw);
644
645 /* set the led polarity */
646 esw_w32(esw, esw->reg_led_polarity & 0x1F,
647 RT5350_EWS_REG_LED_POLARITY);
648
649 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
650 rt305x_mii_write(esw, 0, 26, 0x0020);
651
652 for (i = 0; i < 5; i++) {
653 rt305x_mii_write(esw, i, 31, 0x8000);
654 rt305x_mii_write(esw, i, 0, 0x3100);
655 rt305x_mii_write(esw, i, 30, 0xa000);
656 rt305x_mii_write(esw, i, 31, 0xa000);
657 rt305x_mii_write(esw, i, 16, 0x0606);
658 rt305x_mii_write(esw, i, 23, 0x0f0e);
659 rt305x_mii_write(esw, i, 24, 0x1610);
660 rt305x_mii_write(esw, i, 30, 0x1f15);
661 rt305x_mii_write(esw, i, 28, 0x6111);
662 rt305x_mii_write(esw, i, 31, 0x2000);
663 rt305x_mii_write(esw, i, 26, 0x0000);
664 }
665
666 /* 100Base AOI setting */
667 rt305x_mii_write(esw, 0, 31, 0x5000);
668 rt305x_mii_write(esw, 0, 19, 0x004a);
669 rt305x_mii_write(esw, 0, 20, 0x015a);
670 rt305x_mii_write(esw, 0, 21, 0x00ee);
671 rt305x_mii_write(esw, 0, 22, 0x0033);
672 rt305x_mii_write(esw, 0, 23, 0x020a);
673 rt305x_mii_write(esw, 0, 24, 0x0000);
674 rt305x_mii_write(esw, 0, 25, 0x024a);
675 rt305x_mii_write(esw, 0, 26, 0x035a);
676 rt305x_mii_write(esw, 0, 27, 0x02ee);
677 rt305x_mii_write(esw, 0, 28, 0x0233);
678 rt305x_mii_write(esw, 0, 29, 0x000a);
679 rt305x_mii_write(esw, 0, 30, 0x0000);
680 } else {
681 rt305x_mii_write(esw, 0, 31, 0x8000);
682 for (i = 0; i < 5; i++) {
683 if (esw->ports[i].disable) {
684 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
685 } else {
686 rt305x_mii_write(esw, i, MII_BMCR,
687 BMCR_FULLDPLX |
688 BMCR_ANENABLE |
689 BMCR_SPEED100);
690 }
691 /* TX10 waveform coefficient */
692 rt305x_mii_write(esw, i, 26, 0x1601);
693 /* TX100/TX10 AD/DA current bias */
694 rt305x_mii_write(esw, i, 29, 0x7058);
695 /* TX100 slew rate control */
696 rt305x_mii_write(esw, i, 30, 0x0018);
697 }
698
699 /* PHY IOT */
700 /* select global register */
701 rt305x_mii_write(esw, 0, 31, 0x0);
702 /* tune TP_IDL tail and head waveform */
703 rt305x_mii_write(esw, 0, 22, 0x052f);
704 /* set TX10 signal amplitude threshold to minimum */
705 rt305x_mii_write(esw, 0, 17, 0x0fe0);
706 /* set squelch amplitude to higher threshold */
707 rt305x_mii_write(esw, 0, 18, 0x40ba);
708 /* longer TP_IDL tail length */
709 rt305x_mii_write(esw, 0, 14, 0x65);
710 /* select local register */
711 rt305x_mii_write(esw, 0, 31, 0x8000);
712 }
713
714 if (esw->port_map)
715 port_map = esw->port_map;
716 else
717 port_map = RT305X_ESW_PMAP_LLLLLL;
718
719 /* Unused HW feature, but still nice to be consistent here...
720 * This is also exported to userspace ('lan' attribute) so it's
721 * conveniently usable to decide which ports go into the wan vlan by
722 * default.
723 */
724 esw_rmw(esw, RT305X_ESW_REG_SGC2,
725 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
726 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
727
728 /* make the switch leds blink */
729 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
730 esw->ports[i].led = 0x05;
731
732 /* Apply the empty config. */
733 esw_apply_config(&esw->swdev);
734
735 /* Only unmask the port change interrupt */
736 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
737 }
738
739 static irqreturn_t esw_interrupt(int irq, void *_esw)
740 {
741 struct rt305x_esw *esw = (struct rt305x_esw *)_esw;
742 u32 status;
743
744 status = esw_r32(esw, RT305X_ESW_REG_ISR);
745 if (status & RT305X_ESW_PORT_ST_CHG) {
746 u32 link = esw_r32(esw, RT305X_ESW_REG_POA);
747
748 link >>= RT305X_ESW_POA_LINK_SHIFT;
749 link &= RT305X_ESW_POA_LINK_MASK;
750 dev_info(esw->dev, "link changed 0x%02X\n", link);
751 }
752 esw_w32(esw, status, RT305X_ESW_REG_ISR);
753
754 return IRQ_HANDLED;
755 }
756
757 static int esw_apply_config(struct switch_dev *dev)
758 {
759 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
760 int i;
761 u8 disable = 0;
762 u8 doubletag = 0;
763 u8 en_vlan = 0;
764 u8 untag = 0;
765
766 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
767 u32 vid, vmsc;
768 if (esw->global_vlan_enable) {
769 vid = esw->vlans[i].vid;
770 vmsc = esw->vlans[i].ports;
771 } else {
772 vid = RT305X_ESW_VLAN_NONE;
773 vmsc = RT305X_ESW_PORTS_NONE;
774 }
775 esw_set_vlan_id(esw, i, vid);
776 esw_set_vmsc(esw, i, vmsc);
777 }
778
779 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
780 u32 pvid;
781 disable |= esw->ports[i].disable << i;
782 if (esw->global_vlan_enable) {
783 doubletag |= esw->ports[i].doubletag << i;
784 en_vlan |= 1 << i;
785 untag |= esw->ports[i].untag << i;
786 pvid = esw->ports[i].pvid;
787 } else {
788 int x = esw->alt_vlan_disable ? 0 : 1;
789 doubletag |= x << i;
790 en_vlan |= x << i;
791 untag |= x << i;
792 pvid = 0;
793 }
794 esw_set_pvid(esw, i, pvid);
795 if (i < RT305X_ESW_NUM_LEDS)
796 esw_w32(esw, esw->ports[i].led,
797 RT305X_ESW_REG_P0LED + 4*i);
798 }
799
800 esw_set_gsc(esw);
801 esw_set_port_disable(esw, disable);
802 esw_rmw(esw, RT305X_ESW_REG_SGC2,
803 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
804 RT305X_ESW_SGC2_DOUBLE_TAG_S),
805 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
806 esw_rmw(esw, RT305X_ESW_REG_PFC1,
807 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
808 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
809 esw_rmw(esw, RT305X_ESW_REG_POC2,
810 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
811 untag << RT305X_ESW_POC2_UNTAG_EN_S);
812
813 if (!esw->global_vlan_enable) {
814 /*
815 * Still need to put all ports into vlan 0 or they'll be
816 * isolated.
817 * NOTE: vlan 0 is special, no vlan tag is prepended
818 */
819 esw_set_vlan_id(esw, 0, 0);
820 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
821 }
822
823 return 0;
824 }
825
826 static int esw_reset_switch(struct switch_dev *dev)
827 {
828 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
829
830 esw->global_vlan_enable = 0;
831 memset(esw->ports, 0, sizeof(esw->ports));
832 memset(esw->vlans, 0, sizeof(esw->vlans));
833 esw_hw_init(esw);
834
835 return 0;
836 }
837
838 static int esw_get_vlan_enable(struct switch_dev *dev,
839 const struct switch_attr *attr,
840 struct switch_val *val)
841 {
842 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
843
844 val->value.i = esw->global_vlan_enable;
845
846 return 0;
847 }
848
849 static int esw_set_vlan_enable(struct switch_dev *dev,
850 const struct switch_attr *attr,
851 struct switch_val *val)
852 {
853 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
854
855 esw->global_vlan_enable = val->value.i != 0;
856
857 return 0;
858 }
859
860 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
861 const struct switch_attr *attr,
862 struct switch_val *val)
863 {
864 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
865
866 val->value.i = esw->alt_vlan_disable;
867
868 return 0;
869 }
870
871 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
872 const struct switch_attr *attr,
873 struct switch_val *val)
874 {
875 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
876
877 esw->alt_vlan_disable = val->value.i != 0;
878
879 return 0;
880 }
881
882 static int
883 rt305x_esw_set_bc_status(struct switch_dev *dev,
884 const struct switch_attr *attr,
885 struct switch_val *val)
886 {
887 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
888
889 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
890
891 return 0;
892 }
893
894 static int
895 rt305x_esw_get_bc_status(struct switch_dev *dev,
896 const struct switch_attr *attr,
897 struct switch_val *val)
898 {
899 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
900
901 val->value.i = esw->bc_storm_protect;
902
903 return 0;
904 }
905
906 static int
907 rt305x_esw_set_led_freq(struct switch_dev *dev,
908 const struct switch_attr *attr,
909 struct switch_val *val)
910 {
911 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
912
913 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
914
915 return 0;
916 }
917
918 static int
919 rt305x_esw_get_led_freq(struct switch_dev *dev,
920 const struct switch_attr *attr,
921 struct switch_val *val)
922 {
923 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
924
925 val->value.i = esw->led_frequency;
926
927 return 0;
928 }
929
930 static int esw_get_port_link(struct switch_dev *dev,
931 int port,
932 struct switch_port_link *link)
933 {
934 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
935 u32 speed, poa;
936
937 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
938 return -EINVAL;
939
940 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
941
942 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
943 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
944 if (port < RT305X_ESW_NUM_LEDS) {
945 speed = (poa >> RT305X_ESW_SPD_S) & 1;
946 } else {
947 if (port == RT305X_ESW_NUM_PORTS - 1)
948 poa >>= 1;
949 speed = (poa >> RT305X_ESW_SPD_S) & 3;
950 }
951 switch (speed) {
952 case 0:
953 link->speed = SWITCH_PORT_SPEED_10;
954 break;
955 case 1:
956 link->speed = SWITCH_PORT_SPEED_100;
957 break;
958 case 2:
959 case 3: /* forced gige speed can be 2 or 3 */
960 link->speed = SWITCH_PORT_SPEED_1000;
961 break;
962 default:
963 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
964 break;
965 }
966
967 return 0;
968 }
969
970 static int esw_get_port_bool(struct switch_dev *dev,
971 const struct switch_attr *attr,
972 struct switch_val *val)
973 {
974 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
975 int idx = val->port_vlan;
976 u32 x, reg, shift;
977
978 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
979 return -EINVAL;
980
981 switch (attr->id) {
982 case RT305X_ESW_ATTR_PORT_DISABLE:
983 reg = RT305X_ESW_REG_POC0;
984 shift = RT305X_ESW_POC0_DIS_PORT_S;
985 break;
986 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
987 reg = RT305X_ESW_REG_SGC2;
988 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
989 break;
990 case RT305X_ESW_ATTR_PORT_UNTAG:
991 reg = RT305X_ESW_REG_POC2;
992 shift = RT305X_ESW_POC2_UNTAG_EN_S;
993 break;
994 case RT305X_ESW_ATTR_PORT_LAN:
995 reg = RT305X_ESW_REG_SGC2;
996 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
997 if (idx >= RT305X_ESW_NUM_LANWAN)
998 return -EINVAL;
999 break;
1000 default:
1001 return -EINVAL;
1002 }
1003
1004 x = esw_r32(esw, reg);
1005 val->value.i = (x >> (idx + shift)) & 1;
1006
1007 return 0;
1008 }
1009
1010 static int esw_set_port_bool(struct switch_dev *dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1013 {
1014 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1015 int idx = val->port_vlan;
1016
1017 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1018 val->value.i < 0 || val->value.i > 1)
1019 return -EINVAL;
1020
1021 switch (attr->id) {
1022 case RT305X_ESW_ATTR_PORT_DISABLE:
1023 esw->ports[idx].disable = val->value.i;
1024 break;
1025 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1026 esw->ports[idx].doubletag = val->value.i;
1027 break;
1028 case RT305X_ESW_ATTR_PORT_UNTAG:
1029 esw->ports[idx].untag = val->value.i;
1030 break;
1031 default:
1032 return -EINVAL;
1033 }
1034
1035 return 0;
1036 }
1037
1038 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1039 const struct switch_attr *attr,
1040 struct switch_val *val)
1041 {
1042 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1043 int idx = val->port_vlan;
1044 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1045 u32 reg;
1046
1047 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1048 return -EINVAL;
1049 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1050 val->value.i = (reg >> shift) & 0xffff;
1051
1052 return 0;
1053 }
1054
1055 static int
1056 esw_get_port_tr_badgood(struct switch_dev *dev,
1057 const struct switch_attr *attr,
1058 struct switch_val *val)
1059 {
1060 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1061
1062 int idx = val->port_vlan;
1063 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1064 u32 reg;
1065
1066 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
1067 return -EINVAL;
1068
1069 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1070 return -EINVAL;
1071
1072 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1073 val->value.i = (reg >> shift) & 0xffff;
1074
1075 return 0;
1076 }
1077
1078 static int esw_get_port_led(struct switch_dev *dev,
1079 const struct switch_attr *attr,
1080 struct switch_val *val)
1081 {
1082 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1083 int idx = val->port_vlan;
1084
1085 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1086 idx >= RT305X_ESW_NUM_LEDS)
1087 return -EINVAL;
1088
1089 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1090
1091 return 0;
1092 }
1093
1094 static int esw_set_port_led(struct switch_dev *dev,
1095 const struct switch_attr *attr,
1096 struct switch_val *val)
1097 {
1098 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1099 int idx = val->port_vlan;
1100
1101 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1102 return -EINVAL;
1103
1104 esw->ports[idx].led = val->value.i;
1105
1106 return 0;
1107 }
1108
1109 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1110 {
1111 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1112
1113 if (port >= RT305X_ESW_NUM_PORTS)
1114 return -EINVAL;
1115
1116 *val = esw_get_pvid(esw, port);
1117
1118 return 0;
1119 }
1120
1121 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1122 {
1123 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1124
1125 if (port >= RT305X_ESW_NUM_PORTS)
1126 return -EINVAL;
1127
1128 esw->ports[port].pvid = val;
1129
1130 return 0;
1131 }
1132
1133 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1134 {
1135 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1136 u32 vmsc, poc2;
1137 int vlan_idx = -1;
1138 int i;
1139
1140 val->len = 0;
1141
1142 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1143 return -EINVAL;
1144
1145 /* valid vlan? */
1146 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1147 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1148 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1149 vlan_idx = i;
1150 break;
1151 }
1152 }
1153
1154 if (vlan_idx == -1)
1155 return -EINVAL;
1156
1157 vmsc = esw_get_vmsc(esw, vlan_idx);
1158 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1159
1160 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1161 struct switch_port *p;
1162 int port_mask = 1 << i;
1163
1164 if (!(vmsc & port_mask))
1165 continue;
1166
1167 p = &val->value.ports[val->len++];
1168 p->id = i;
1169 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1170 p->flags = 0;
1171 else
1172 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1173 }
1174
1175 return 0;
1176 }
1177
1178 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1179 {
1180 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1181 int ports;
1182 int vlan_idx = -1;
1183 int i;
1184
1185 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1186 val->len > RT305X_ESW_NUM_PORTS)
1187 return -EINVAL;
1188
1189 /* one of the already defined vlans? */
1190 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1191 if (esw->vlans[i].vid == val->port_vlan &&
1192 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1193 vlan_idx = i;
1194 break;
1195 }
1196 }
1197
1198 /* select a free slot */
1199 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1200 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1201 vlan_idx = i;
1202 }
1203
1204 /* bail if all slots are in use */
1205 if (vlan_idx == -1)
1206 return -EINVAL;
1207
1208 ports = RT305X_ESW_PORTS_NONE;
1209 for (i = 0; i < val->len; i++) {
1210 struct switch_port *p = &val->value.ports[i];
1211 int port_mask = 1 << p->id;
1212 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1213
1214 if (p->id >= RT305X_ESW_NUM_PORTS)
1215 return -EINVAL;
1216
1217 ports |= port_mask;
1218 esw->ports[p->id].untag = untagged;
1219 }
1220 esw->vlans[vlan_idx].ports = ports;
1221 if (ports == RT305X_ESW_PORTS_NONE)
1222 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1223 else
1224 esw->vlans[vlan_idx].vid = val->port_vlan;
1225
1226 return 0;
1227 }
1228
1229 static const struct switch_attr esw_global[] = {
1230 {
1231 .type = SWITCH_TYPE_INT,
1232 .name = "enable_vlan",
1233 .description = "VLAN mode (1:enabled)",
1234 .max = 1,
1235 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1236 .get = esw_get_vlan_enable,
1237 .set = esw_set_vlan_enable,
1238 },
1239 {
1240 .type = SWITCH_TYPE_INT,
1241 .name = "alternate_vlan_disable",
1242 .description = "Use en_vlan instead of doubletag to disable"
1243 " VLAN mode",
1244 .max = 1,
1245 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1246 .get = esw_get_alt_vlan_disable,
1247 .set = esw_set_alt_vlan_disable,
1248 },
1249 {
1250 .type = SWITCH_TYPE_INT,
1251 .name = "bc_storm_protect",
1252 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1253 .max = 3,
1254 .id = RT305X_ESW_ATTR_BC_STATUS,
1255 .get = rt305x_esw_get_bc_status,
1256 .set = rt305x_esw_set_bc_status,
1257 },
1258 {
1259 .type = SWITCH_TYPE_INT,
1260 .name = "led_frequency",
1261 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1262 .max = 3,
1263 .id = RT305X_ESW_ATTR_LED_FREQ,
1264 .get = rt305x_esw_get_led_freq,
1265 .set = rt305x_esw_set_led_freq,
1266 }
1267 };
1268
1269 static const struct switch_attr esw_port[] = {
1270 {
1271 .type = SWITCH_TYPE_INT,
1272 .name = "disable",
1273 .description = "Port state (1:disabled)",
1274 .max = 1,
1275 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1276 .get = esw_get_port_bool,
1277 .set = esw_set_port_bool,
1278 },
1279 {
1280 .type = SWITCH_TYPE_INT,
1281 .name = "doubletag",
1282 .description = "Double tagging for incoming vlan packets "
1283 "(1:enabled)",
1284 .max = 1,
1285 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1286 .get = esw_get_port_bool,
1287 .set = esw_set_port_bool,
1288 },
1289 {
1290 .type = SWITCH_TYPE_INT,
1291 .name = "untag",
1292 .description = "Untag (1:strip outgoing vlan tag)",
1293 .max = 1,
1294 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1295 .get = esw_get_port_bool,
1296 .set = esw_set_port_bool,
1297 },
1298 {
1299 .type = SWITCH_TYPE_INT,
1300 .name = "led",
1301 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1302 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1303 " 8:100mact, 10:blink, 11:off, 12:on)",
1304 .max = 15,
1305 .id = RT305X_ESW_ATTR_PORT_LED,
1306 .get = esw_get_port_led,
1307 .set = esw_set_port_led,
1308 },
1309 {
1310 .type = SWITCH_TYPE_INT,
1311 .name = "lan",
1312 .description = "HW port group (0:wan, 1:lan)",
1313 .max = 1,
1314 .id = RT305X_ESW_ATTR_PORT_LAN,
1315 .get = esw_get_port_bool,
1316 },
1317 {
1318 .type = SWITCH_TYPE_INT,
1319 .name = "recv_bad",
1320 .description = "Receive bad packet counter",
1321 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1322 .get = esw_get_port_recv_badgood,
1323 },
1324 {
1325 .type = SWITCH_TYPE_INT,
1326 .name = "recv_good",
1327 .description = "Receive good packet counter",
1328 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1329 .get = esw_get_port_recv_badgood,
1330 },
1331 {
1332 .type = SWITCH_TYPE_INT,
1333 .name = "tr_bad",
1334
1335 .description = "Transmit bad packet counter. rt5350 only",
1336 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1337 .get = esw_get_port_tr_badgood,
1338 },
1339 {
1340 .type = SWITCH_TYPE_INT,
1341 .name = "tr_good",
1342
1343 .description = "Transmit good packet counter. rt5350 only",
1344 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1345 .get = esw_get_port_tr_badgood,
1346 },
1347 };
1348
1349 static const struct switch_attr esw_vlan[] = {
1350 };
1351
1352 static const struct switch_dev_ops esw_ops = {
1353 .attr_global = {
1354 .attr = esw_global,
1355 .n_attr = ARRAY_SIZE(esw_global),
1356 },
1357 .attr_port = {
1358 .attr = esw_port,
1359 .n_attr = ARRAY_SIZE(esw_port),
1360 },
1361 .attr_vlan = {
1362 .attr = esw_vlan,
1363 .n_attr = ARRAY_SIZE(esw_vlan),
1364 },
1365 .get_vlan_ports = esw_get_vlan_ports,
1366 .set_vlan_ports = esw_set_vlan_ports,
1367 .get_port_pvid = esw_get_port_pvid,
1368 .set_port_pvid = esw_set_port_pvid,
1369 .get_port_link = esw_get_port_link,
1370 .apply_config = esw_apply_config,
1371 .reset_switch = esw_reset_switch,
1372 };
1373
1374 static int esw_probe(struct platform_device *pdev)
1375 {
1376 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1377 struct device_node *np = pdev->dev.of_node;
1378 const __be32 *port_map, *port_disable, *reg_init;
1379 struct switch_dev *swdev;
1380 struct rt305x_esw *esw;
1381 int ret;
1382
1383 esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
1384 if (!esw)
1385 return -ENOMEM;
1386
1387 esw->dev = &pdev->dev;
1388 esw->irq = irq_of_parse_and_map(np, 0);
1389 esw->base = devm_ioremap_resource(&pdev->dev, res);
1390 if (IS_ERR(esw->base))
1391 return PTR_ERR(esw->base);
1392
1393 port_map = of_get_property(np, "mediatek,portmap", NULL);
1394 if (port_map)
1395 esw->port_map = be32_to_cpu(*port_map);
1396
1397 port_disable = of_get_property(np, "mediatek,portdisable", NULL);
1398 if (port_disable)
1399 esw->port_disable = be32_to_cpu(*port_disable);
1400
1401 reg_init = of_get_property(np, "ralink,fct2", NULL);
1402 if (reg_init)
1403 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1404
1405 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1406 if (reg_init)
1407 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1408
1409 reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
1410 if (reg_init)
1411 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1412
1413 esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw");
1414 if (IS_ERR(esw->rst_esw))
1415 esw->rst_esw = NULL;
1416 esw->rst_ephy = devm_reset_control_get(&pdev->dev, "ephy");
1417 if (IS_ERR(esw->rst_ephy))
1418 esw->rst_ephy = NULL;
1419
1420 swdev = &esw->swdev;
1421 swdev->of_node = pdev->dev.of_node;
1422 swdev->name = "rt305x-esw";
1423 swdev->alias = "rt305x";
1424 swdev->cpu_port = RT305X_ESW_PORT6;
1425 swdev->ports = RT305X_ESW_NUM_PORTS;
1426 swdev->vlans = RT305X_ESW_NUM_VIDS;
1427 swdev->ops = &esw_ops;
1428
1429 ret = register_switch(swdev, NULL);
1430 if (ret < 0) {
1431 dev_err(&pdev->dev, "register_switch failed\n");
1432 return ret;
1433 }
1434
1435 platform_set_drvdata(pdev, esw);
1436
1437 spin_lock_init(&esw->reg_rw_lock);
1438
1439 esw_hw_init(esw);
1440
1441 reg_init = of_get_property(np, "ralink,rgmii", NULL);
1442 if (reg_init && be32_to_cpu(*reg_init) == 1) {
1443 /*
1444 * External switch connected to RGMII interface.
1445 * Unregister the switch device after initialization.
1446 */
1447 dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
1448 unregister_switch(&esw->swdev);
1449 platform_set_drvdata(pdev, NULL);
1450 return -ENODEV;
1451 }
1452
1453 ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
1454 esw);
1455
1456 if (!ret) {
1457 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1458 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1459 }
1460
1461 return ret;
1462 }
1463
1464 static int esw_remove(struct platform_device *pdev)
1465 {
1466 struct rt305x_esw *esw = platform_get_drvdata(pdev);
1467
1468 if (esw) {
1469 esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
1470 platform_set_drvdata(pdev, NULL);
1471 }
1472
1473 return 0;
1474 }
1475
1476 static const struct of_device_id ralink_esw_match[] = {
1477 { .compatible = "ralink,rt3050-esw" },
1478 {},
1479 };
1480 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1481
1482 static struct platform_driver esw_driver = {
1483 .probe = esw_probe,
1484 .remove = esw_remove,
1485 .driver = {
1486 .name = "rt3050-esw",
1487 .owner = THIS_MODULE,
1488 .of_match_table = ralink_esw_match,
1489 },
1490 };
1491
1492 module_platform_driver(esw_driver);
1493
1494 MODULE_LICENSE("GPL");
1495 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1496 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1497 MODULE_VERSION(MTK_FE_DRV_VERSION);
Staging tree of Zoltan Herpai