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ramips: ethernet: ralink: rewrite esw_rt3050 to support link states
[openwrt/openwrt.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / esw_rt3050.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 * Copyright (C) 2016 Vittorio Gambaletta <openwrt@vittgam.net>
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/platform_device.h>
19 #include <asm/mach-ralink/ralink_regs.h>
20 #include <linux/of_device.h>
21 #include <linux/of_irq.h>
22
23 #include <linux/switch.h>
24 #include <linux/reset.h>
25
26 #include "mtk_eth_soc.h"
27 #include "esw_rt3050.h"
28
29 /* HW limitations for this switch:
30 * - No large frame support (PKT_MAX_LEN at most 1536)
31 * - Can't have untagged vlan and tagged vlan on one port at the same time,
32 * though this might be possible using the undocumented PPE.
33 */
34
35 #define RT305X_ESW_REG_ISR 0x00
36 #define RT305X_ESW_REG_IMR 0x04
37 #define RT305X_ESW_REG_FCT0 0x08
38 #define RT305X_ESW_REG_PFC1 0x14
39 #define RT305X_ESW_REG_ATS 0x24
40 #define RT305X_ESW_REG_ATS0 0x28
41 #define RT305X_ESW_REG_ATS1 0x2c
42 #define RT305X_ESW_REG_ATS2 0x30
43 #define RT305X_ESW_REG_PVIDC(_n) (0x40 + 4 * (_n))
44 #define RT305X_ESW_REG_VLANI(_n) (0x50 + 4 * (_n))
45 #define RT305X_ESW_REG_VMSC(_n) (0x70 + 4 * (_n))
46 #define RT305X_ESW_REG_POA 0x80
47 #define RT305X_ESW_REG_FPA 0x84
48 #define RT305X_ESW_REG_SOCPC 0x8c
49 #define RT305X_ESW_REG_POC0 0x90
50 #define RT305X_ESW_REG_POC1 0x94
51 #define RT305X_ESW_REG_POC2 0x98
52 #define RT305X_ESW_REG_SGC 0x9c
53 #define RT305X_ESW_REG_STRT 0xa0
54 #define RT305X_ESW_REG_PCR0 0xc0
55 #define RT305X_ESW_REG_PCR1 0xc4
56 #define RT305X_ESW_REG_FPA2 0xc8
57 #define RT305X_ESW_REG_FCT2 0xcc
58 #define RT305X_ESW_REG_SGC2 0xe4
59 #define RT305X_ESW_REG_P0LED 0xa4
60 #define RT305X_ESW_REG_P1LED 0xa8
61 #define RT305X_ESW_REG_P2LED 0xac
62 #define RT305X_ESW_REG_P3LED 0xb0
63 #define RT305X_ESW_REG_P4LED 0xb4
64 #define RT305X_ESW_REG_PXPC(_x) (0xe8 + (4 * _x))
65 #define RT305X_ESW_REG_P1PC 0xec
66 #define RT305X_ESW_REG_P2PC 0xf0
67 #define RT305X_ESW_REG_P3PC 0xf4
68 #define RT305X_ESW_REG_P4PC 0xf8
69 #define RT305X_ESW_REG_P5PC 0xfc
70
71 #define RT305X_ESW_LED_LINK 0
72 #define RT305X_ESW_LED_100M 1
73 #define RT305X_ESW_LED_DUPLEX 2
74 #define RT305X_ESW_LED_ACTIVITY 3
75 #define RT305X_ESW_LED_COLLISION 4
76 #define RT305X_ESW_LED_LINKACT 5
77 #define RT305X_ESW_LED_DUPLCOLL 6
78 #define RT305X_ESW_LED_10MACT 7
79 #define RT305X_ESW_LED_100MACT 8
80 /* Additional led states not in datasheet: */
81 #define RT305X_ESW_LED_BLINK 10
82 #define RT305X_ESW_LED_ON 12
83
84 #define RT305X_ESW_LINK_S 25
85 #define RT305X_ESW_DUPLEX_S 9
86 #define RT305X_ESW_SPD_S 0
87
88 #define RT305X_ESW_PCR0_WT_NWAY_DATA_S 16
89 #define RT305X_ESW_PCR0_WT_PHY_CMD BIT(13)
90 #define RT305X_ESW_PCR0_CPU_PHY_REG_S 8
91
92 #define RT305X_ESW_PCR1_WT_DONE BIT(0)
93
94 #define RT305X_ESW_ATS_TIMEOUT (5 * HZ)
95 #define RT305X_ESW_PHY_TIMEOUT (5 * HZ)
96
97 #define RT305X_ESW_PVIDC_PVID_M 0xfff
98 #define RT305X_ESW_PVIDC_PVID_S 12
99
100 #define RT305X_ESW_VLANI_VID_M 0xfff
101 #define RT305X_ESW_VLANI_VID_S 12
102
103 #define RT305X_ESW_VMSC_MSC_M 0xff
104 #define RT305X_ESW_VMSC_MSC_S 8
105
106 #define RT305X_ESW_SOCPC_DISUN2CPU_S 0
107 #define RT305X_ESW_SOCPC_DISMC2CPU_S 8
108 #define RT305X_ESW_SOCPC_DISBC2CPU_S 16
109 #define RT305X_ESW_SOCPC_CRC_PADDING BIT(25)
110
111 #define RT305X_ESW_POC0_EN_BP_S 0
112 #define RT305X_ESW_POC0_EN_FC_S 8
113 #define RT305X_ESW_POC0_DIS_RMC2CPU_S 16
114 #define RT305X_ESW_POC0_DIS_PORT_M 0x7f
115 #define RT305X_ESW_POC0_DIS_PORT_S 23
116
117 #define RT305X_ESW_POC2_UNTAG_EN_M 0xff
118 #define RT305X_ESW_POC2_UNTAG_EN_S 0
119 #define RT305X_ESW_POC2_ENAGING_S 8
120 #define RT305X_ESW_POC2_DIS_UC_PAUSE_S 16
121
122 #define RT305X_ESW_SGC2_DOUBLE_TAG_M 0x7f
123 #define RT305X_ESW_SGC2_DOUBLE_TAG_S 0
124 #define RT305X_ESW_SGC2_LAN_PMAP_M 0x3f
125 #define RT305X_ESW_SGC2_LAN_PMAP_S 24
126
127 #define RT305X_ESW_PFC1_EN_VLAN_M 0xff
128 #define RT305X_ESW_PFC1_EN_VLAN_S 16
129 #define RT305X_ESW_PFC1_EN_TOS_S 24
130
131 #define RT305X_ESW_VLAN_NONE 0xfff
132
133 #define RT305X_ESW_GSC_BC_STROM_MASK 0x3
134 #define RT305X_ESW_GSC_BC_STROM_SHIFT 4
135
136 #define RT305X_ESW_GSC_LED_FREQ_MASK 0x3
137 #define RT305X_ESW_GSC_LED_FREQ_SHIFT 23
138
139 #define RT305X_ESW_POA_LINK_MASK 0x1f
140 #define RT305X_ESW_POA_LINK_SHIFT 25
141
142 #define RT305X_ESW_PORT_ST_CHG BIT(26)
143 #define RT305X_ESW_PORT0 0
144 #define RT305X_ESW_PORT1 1
145 #define RT305X_ESW_PORT2 2
146 #define RT305X_ESW_PORT3 3
147 #define RT305X_ESW_PORT4 4
148 #define RT305X_ESW_PORT5 5
149 #define RT305X_ESW_PORT6 6
150
151 #define RT305X_ESW_PORTS_NONE 0
152
153 #define RT305X_ESW_PMAP_LLLLLL 0x3f
154 #define RT305X_ESW_PMAP_LLLLWL 0x2f
155 #define RT305X_ESW_PMAP_WLLLLL 0x3e
156
157 #define RT305X_ESW_PORTS_INTERNAL \
158 (BIT(RT305X_ESW_PORT0) | BIT(RT305X_ESW_PORT1) | \
159 BIT(RT305X_ESW_PORT2) | BIT(RT305X_ESW_PORT3) | \
160 BIT(RT305X_ESW_PORT4))
161
162 #define RT305X_ESW_PORTS_NOCPU \
163 (RT305X_ESW_PORTS_INTERNAL | BIT(RT305X_ESW_PORT5))
164
165 #define RT305X_ESW_PORTS_CPU BIT(RT305X_ESW_PORT6)
166
167 #define RT305X_ESW_PORTS_ALL \
168 (RT305X_ESW_PORTS_NOCPU | RT305X_ESW_PORTS_CPU)
169
170 #define RT305X_ESW_NUM_VLANS 16
171 #define RT305X_ESW_NUM_VIDS 4096
172 #define RT305X_ESW_NUM_PORTS 7
173 #define RT305X_ESW_NUM_LANWAN 6
174 #define RT305X_ESW_NUM_LEDS 5
175
176 #define RT5350_ESW_REG_PXTPC(_x) (0x150 + (4 * _x))
177 #define RT5350_EWS_REG_LED_POLARITY 0x168
178
179 enum {
180 /* Global attributes. */
181 RT305X_ESW_ATTR_ENABLE_VLAN,
182 RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
183 RT305X_ESW_ATTR_BC_STATUS,
184 RT305X_ESW_ATTR_LED_FREQ,
185 /* Port attributes. */
186 RT305X_ESW_ATTR_PORT_DISABLE,
187 RT305X_ESW_ATTR_PORT_DOUBLETAG,
188 RT305X_ESW_ATTR_PORT_UNTAG,
189 RT305X_ESW_ATTR_PORT_LED,
190 RT305X_ESW_ATTR_PORT_LAN,
191 RT305X_ESW_ATTR_PORT_RECV_BAD,
192 RT305X_ESW_ATTR_PORT_RECV_GOOD,
193 RT5350_ESW_ATTR_PORT_TR_BAD,
194 RT5350_ESW_ATTR_PORT_TR_GOOD,
195 };
196
197 struct esw_port {
198 bool disable;
199 bool doubletag;
200 bool untag;
201 u8 led;
202 u16 pvid;
203 };
204
205 struct esw_vlan {
206 u8 ports;
207 u16 vid;
208 };
209
210 enum {
211 RT305X_ESW_VLAN_CONFIG_NONE = 0,
212 RT305X_ESW_VLAN_CONFIG_LLLLW,
213 RT305X_ESW_VLAN_CONFIG_WLLLL,
214 };
215
216 struct rt305x_esw {
217 struct device *dev;
218 void __iomem *base;
219 int irq;
220 struct fe_priv *priv;
221
222 /* Protects against concurrent register r/w operations. */
223 spinlock_t reg_rw_lock;
224
225 unsigned char port_map;
226 unsigned char port_disable;
227 unsigned int reg_initval_fct2;
228 unsigned int reg_initval_fpa2;
229 unsigned int reg_led_polarity;
230
231 struct switch_dev swdev;
232 bool global_vlan_enable;
233 bool alt_vlan_disable;
234 int bc_storm_protect;
235 int led_frequency;
236 struct esw_vlan vlans[RT305X_ESW_NUM_VLANS];
237 struct esw_port ports[RT305X_ESW_NUM_PORTS];
238 struct reset_control *rst_esw;
239 struct reset_control *rst_ephy;
240
241 };
242
243 static inline void esw_w32(struct rt305x_esw *esw, u32 val, unsigned reg)
244 {
245 __raw_writel(val, esw->base + reg);
246 }
247
248 static inline u32 esw_r32(struct rt305x_esw *esw, unsigned reg)
249 {
250 return __raw_readl(esw->base + reg);
251 }
252
253 static inline void esw_rmw_raw(struct rt305x_esw *esw, unsigned reg,
254 unsigned long mask, unsigned long val)
255 {
256 unsigned long t;
257
258 t = __raw_readl(esw->base + reg) & ~mask;
259 __raw_writel(t | val, esw->base + reg);
260 }
261
262 static void esw_reset(struct rt305x_esw *esw)
263 {
264 if (!esw->rst_esw)
265 return;
266
267 reset_control_assert(esw->rst_esw);
268 usleep_range(60, 120);
269 reset_control_deassert(esw->rst_esw);
270 /* the esw takes long to reset otherwise the board hang */
271 msleep(10);
272 }
273
274 static void esw_reset_ephy(struct rt305x_esw *esw)
275 {
276 if (!esw->rst_ephy)
277 return;
278
279 reset_control_assert(esw->rst_ephy);
280 usleep_range(60, 120);
281 reset_control_deassert(esw->rst_ephy);
282 usleep_range(60, 120);
283 }
284
285 static void esw_rmw(struct rt305x_esw *esw, unsigned reg,
286 unsigned long mask, unsigned long val)
287 {
288 unsigned long flags;
289
290 spin_lock_irqsave(&esw->reg_rw_lock, flags);
291 esw_rmw_raw(esw, reg, mask, val);
292 spin_unlock_irqrestore(&esw->reg_rw_lock, flags);
293 }
294
295 static u32 rt305x_mii_write(struct rt305x_esw *esw, u32 phy_addr,
296 u32 phy_register, u32 write_data)
297 {
298 unsigned long t_start = jiffies;
299 int ret = 0;
300
301 while (1) {
302 if (!(esw_r32(esw, RT305X_ESW_REG_PCR1) &
303 RT305X_ESW_PCR1_WT_DONE))
304 break;
305 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
306 ret = 1;
307 goto out;
308 }
309 }
310
311 write_data &= 0xffff;
312 esw_w32(esw, (write_data << RT305X_ESW_PCR0_WT_NWAY_DATA_S) |
313 (phy_register << RT305X_ESW_PCR0_CPU_PHY_REG_S) |
314 (phy_addr) | RT305X_ESW_PCR0_WT_PHY_CMD,
315 RT305X_ESW_REG_PCR0);
316
317 t_start = jiffies;
318 while (1) {
319 if (esw_r32(esw, RT305X_ESW_REG_PCR1) &
320 RT305X_ESW_PCR1_WT_DONE)
321 break;
322
323 if (time_after(jiffies, t_start + RT305X_ESW_PHY_TIMEOUT)) {
324 ret = 1;
325 break;
326 }
327 }
328 out:
329 if (ret)
330 dev_err(esw->dev, "ramips_eth: MDIO timeout\n");
331 return ret;
332 }
333
334 static unsigned esw_get_vlan_id(struct rt305x_esw *esw, unsigned vlan)
335 {
336 unsigned s;
337 unsigned val;
338
339 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
340 val = esw_r32(esw, RT305X_ESW_REG_VLANI(vlan / 2));
341 val = (val >> s) & RT305X_ESW_VLANI_VID_M;
342
343 return val;
344 }
345
346 static void esw_set_vlan_id(struct rt305x_esw *esw, unsigned vlan, unsigned vid)
347 {
348 unsigned s;
349
350 s = RT305X_ESW_VLANI_VID_S * (vlan % 2);
351 esw_rmw(esw,
352 RT305X_ESW_REG_VLANI(vlan / 2),
353 RT305X_ESW_VLANI_VID_M << s,
354 (vid & RT305X_ESW_VLANI_VID_M) << s);
355 }
356
357 static unsigned esw_get_pvid(struct rt305x_esw *esw, unsigned port)
358 {
359 unsigned s, val;
360
361 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
362 val = esw_r32(esw, RT305X_ESW_REG_PVIDC(port / 2));
363 return (val >> s) & RT305X_ESW_PVIDC_PVID_M;
364 }
365
366 static void esw_set_pvid(struct rt305x_esw *esw, unsigned port, unsigned pvid)
367 {
368 unsigned s;
369
370 s = RT305X_ESW_PVIDC_PVID_S * (port % 2);
371 esw_rmw(esw,
372 RT305X_ESW_REG_PVIDC(port / 2),
373 RT305X_ESW_PVIDC_PVID_M << s,
374 (pvid & RT305X_ESW_PVIDC_PVID_M) << s);
375 }
376
377 static unsigned esw_get_vmsc(struct rt305x_esw *esw, unsigned vlan)
378 {
379 unsigned s, val;
380
381 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
382 val = esw_r32(esw, RT305X_ESW_REG_VMSC(vlan / 4));
383 val = (val >> s) & RT305X_ESW_VMSC_MSC_M;
384
385 return val;
386 }
387
388 static void esw_set_vmsc(struct rt305x_esw *esw, unsigned vlan, unsigned msc)
389 {
390 unsigned s;
391
392 s = RT305X_ESW_VMSC_MSC_S * (vlan % 4);
393 esw_rmw(esw,
394 RT305X_ESW_REG_VMSC(vlan / 4),
395 RT305X_ESW_VMSC_MSC_M << s,
396 (msc & RT305X_ESW_VMSC_MSC_M) << s);
397 }
398
399 static unsigned esw_get_port_disable(struct rt305x_esw *esw)
400 {
401 unsigned reg;
402
403 reg = esw_r32(esw, RT305X_ESW_REG_POC0);
404 return (reg >> RT305X_ESW_POC0_DIS_PORT_S) &
405 RT305X_ESW_POC0_DIS_PORT_M;
406 }
407
408 static void esw_set_port_disable(struct rt305x_esw *esw, unsigned disable_mask)
409 {
410 unsigned old_mask;
411 unsigned enable_mask;
412 unsigned changed;
413 int i;
414
415 old_mask = esw_get_port_disable(esw);
416 changed = old_mask ^ disable_mask;
417 enable_mask = old_mask & disable_mask;
418
419 /* enable before writing to MII */
420 esw_rmw(esw, RT305X_ESW_REG_POC0,
421 (RT305X_ESW_POC0_DIS_PORT_M <<
422 RT305X_ESW_POC0_DIS_PORT_S),
423 enable_mask << RT305X_ESW_POC0_DIS_PORT_S);
424
425 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++) {
426 if (!(changed & (1 << i)))
427 continue;
428 if (disable_mask & (1 << i)) {
429 /* disable */
430 rt305x_mii_write(esw, i, MII_BMCR,
431 BMCR_PDOWN);
432 } else {
433 /* enable */
434 rt305x_mii_write(esw, i, MII_BMCR,
435 BMCR_FULLDPLX |
436 BMCR_ANENABLE |
437 BMCR_ANRESTART |
438 BMCR_SPEED100);
439 }
440 }
441
442 /* disable after writing to MII */
443 esw_rmw(esw, RT305X_ESW_REG_POC0,
444 (RT305X_ESW_POC0_DIS_PORT_M <<
445 RT305X_ESW_POC0_DIS_PORT_S),
446 disable_mask << RT305X_ESW_POC0_DIS_PORT_S);
447 }
448
449 static void esw_set_gsc(struct rt305x_esw *esw)
450 {
451 esw_rmw(esw, RT305X_ESW_REG_SGC,
452 RT305X_ESW_GSC_BC_STROM_MASK << RT305X_ESW_GSC_BC_STROM_SHIFT,
453 esw->bc_storm_protect << RT305X_ESW_GSC_BC_STROM_SHIFT);
454 esw_rmw(esw, RT305X_ESW_REG_SGC,
455 RT305X_ESW_GSC_LED_FREQ_MASK << RT305X_ESW_GSC_LED_FREQ_SHIFT,
456 esw->led_frequency << RT305X_ESW_GSC_LED_FREQ_SHIFT);
457 }
458
459 static int esw_apply_config(struct switch_dev *dev);
460
461 static void esw_hw_init(struct rt305x_esw *esw)
462 {
463 int i;
464 u8 port_disable = 0;
465 u8 port_map = RT305X_ESW_PMAP_LLLLLL;
466
467 esw_reset(esw);
468
469 /* vodoo from original driver */
470 esw_w32(esw, 0xC8A07850, RT305X_ESW_REG_FCT0);
471 esw_w32(esw, 0x00000000, RT305X_ESW_REG_SGC2);
472 /* Port priority 1 for all ports, vlan enabled. */
473 esw_w32(esw, 0x00005555 |
474 (RT305X_ESW_PORTS_ALL << RT305X_ESW_PFC1_EN_VLAN_S),
475 RT305X_ESW_REG_PFC1);
476
477 /* Enable all ports, Back Pressure and Flow Control */
478 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_BP_S) |
479 (RT305X_ESW_PORTS_ALL << RT305X_ESW_POC0_EN_FC_S)),
480 RT305X_ESW_REG_POC0);
481
482 /* Enable Aging, and VLAN TAG removal */
483 esw_w32(esw, ((RT305X_ESW_PORTS_ALL << RT305X_ESW_POC2_ENAGING_S) |
484 (RT305X_ESW_PORTS_NOCPU << RT305X_ESW_POC2_UNTAG_EN_S)),
485 RT305X_ESW_REG_POC2);
486
487 if (esw->reg_initval_fct2)
488 esw_w32(esw, esw->reg_initval_fct2, RT305X_ESW_REG_FCT2);
489 else
490 esw_w32(esw, 0x0002500c, RT305X_ESW_REG_FCT2);
491
492 /* 300s aging timer, max packet len 1536, broadcast storm prevention
493 * disabled, disable collision abort, mac xor48 hash, 10 packet back
494 * pressure jam, GMII disable was_transmit, back pressure disabled,
495 * 30ms led flash, unmatched IGMP as broadcast, rmc tb fault to all
496 * ports.
497 */
498 esw_w32(esw, 0x0008a301, RT305X_ESW_REG_SGC);
499
500 /* Setup SoC Port control register */
501 esw_w32(esw,
502 (RT305X_ESW_SOCPC_CRC_PADDING |
503 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISUN2CPU_S) |
504 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISMC2CPU_S) |
505 (RT305X_ESW_PORTS_CPU << RT305X_ESW_SOCPC_DISBC2CPU_S)),
506 RT305X_ESW_REG_SOCPC);
507
508 /* ext phy base addr 31, enable port 5 polling, rx/tx clock skew 1,
509 * turbo mii off, rgmi 3.3v off
510 * port5: disabled
511 * port6: enabled, gige, full-duplex, rx/tx-flow-control
512 */
513 if (esw->reg_initval_fpa2)
514 esw_w32(esw, esw->reg_initval_fpa2, RT305X_ESW_REG_FPA2);
515 else
516 esw_w32(esw, 0x3f502b28, RT305X_ESW_REG_FPA2);
517 esw_w32(esw, 0x00000000, RT305X_ESW_REG_FPA);
518
519 /* Force Link/Activity on ports */
520 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P0LED);
521 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P1LED);
522 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P2LED);
523 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P3LED);
524 esw_w32(esw, 0x00000005, RT305X_ESW_REG_P4LED);
525
526 /* Copy disabled port configuration from device tree setup */
527 port_disable = esw->port_disable;
528
529 /* Disable nonexistent ports by reading the switch config
530 * after having enabled all possible ports above
531 */
532 port_disable |= esw_get_port_disable(esw);
533
534 for (i = 0; i < 6; i++)
535 esw->ports[i].disable = (port_disable & (1 << i)) != 0;
536
537 if (ralink_soc == RT305X_SOC_RT3352) {
538 esw_reset_ephy(esw);
539
540 rt305x_mii_write(esw, 0, 31, 0x8000);
541 for (i = 0; i < 5; i++) {
542 if (esw->ports[i].disable) {
543 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
544 } else {
545 rt305x_mii_write(esw, i, MII_BMCR,
546 BMCR_FULLDPLX |
547 BMCR_ANENABLE |
548 BMCR_SPEED100);
549 }
550 /* TX10 waveform coefficient LSB=0 disable PHY */
551 rt305x_mii_write(esw, i, 26, 0x1601);
552 /* TX100/TX10 AD/DA current bias */
553 rt305x_mii_write(esw, i, 29, 0x7016);
554 /* TX100 slew rate control */
555 rt305x_mii_write(esw, i, 30, 0x0038);
556 }
557
558 /* select global register */
559 rt305x_mii_write(esw, 0, 31, 0x0);
560 /* enlarge agcsel threshold 3 and threshold 2 */
561 rt305x_mii_write(esw, 0, 1, 0x4a40);
562 /* enlarge agcsel threshold 5 and threshold 4 */
563 rt305x_mii_write(esw, 0, 2, 0x6254);
564 /* enlarge agcsel threshold */
565 rt305x_mii_write(esw, 0, 3, 0xa17f);
566 rt305x_mii_write(esw, 0, 12, 0x7eaa);
567 /* longer TP_IDL tail length */
568 rt305x_mii_write(esw, 0, 14, 0x65);
569 /* increased squelch pulse count threshold. */
570 rt305x_mii_write(esw, 0, 16, 0x0684);
571 /* set TX10 signal amplitude threshold to minimum */
572 rt305x_mii_write(esw, 0, 17, 0x0fe0);
573 /* set squelch amplitude to higher threshold */
574 rt305x_mii_write(esw, 0, 18, 0x40ba);
575 /* tune TP_IDL tail and head waveform, enable power
576 * down slew rate control
577 */
578 rt305x_mii_write(esw, 0, 22, 0x253f);
579 /* set PLL/Receive bias current are calibrated */
580 rt305x_mii_write(esw, 0, 27, 0x2fda);
581 /* change PLL/Receive bias current to internal(RT3350) */
582 rt305x_mii_write(esw, 0, 28, 0xc410);
583 /* change PLL bias current to internal(RT3052_MP3) */
584 rt305x_mii_write(esw, 0, 29, 0x598b);
585 /* select local register */
586 rt305x_mii_write(esw, 0, 31, 0x8000);
587 } else if (ralink_soc == RT305X_SOC_RT5350) {
588 esw_reset_ephy(esw);
589
590 /* set the led polarity */
591 esw_w32(esw, esw->reg_led_polarity & 0x1F,
592 RT5350_EWS_REG_LED_POLARITY);
593
594 /* local registers */
595 rt305x_mii_write(esw, 0, 31, 0x8000);
596 for (i = 0; i < 5; i++) {
597 if (esw->ports[i].disable) {
598 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
599 } else {
600 rt305x_mii_write(esw, i, MII_BMCR,
601 BMCR_FULLDPLX |
602 BMCR_ANENABLE |
603 BMCR_SPEED100);
604 }
605 /* TX10 waveform coefficient LSB=0 disable PHY */
606 rt305x_mii_write(esw, i, 26, 0x1601);
607 /* TX100/TX10 AD/DA current bias */
608 rt305x_mii_write(esw, i, 29, 0x7015);
609 /* TX100 slew rate control */
610 rt305x_mii_write(esw, i, 30, 0x0038);
611 }
612
613 /* global registers */
614 rt305x_mii_write(esw, 0, 31, 0x0);
615 /* enlarge agcsel threshold 3 and threshold 2 */
616 rt305x_mii_write(esw, 0, 1, 0x4a40);
617 /* enlarge agcsel threshold 5 and threshold 4 */
618 rt305x_mii_write(esw, 0, 2, 0x6254);
619 /* enlarge agcsel threshold 6 */
620 rt305x_mii_write(esw, 0, 3, 0xa17f);
621 rt305x_mii_write(esw, 0, 12, 0x7eaa);
622 /* longer TP_IDL tail length */
623 rt305x_mii_write(esw, 0, 14, 0x65);
624 /* increased squelch pulse count threshold. */
625 rt305x_mii_write(esw, 0, 16, 0x0684);
626 /* set TX10 signal amplitude threshold to minimum */
627 rt305x_mii_write(esw, 0, 17, 0x0fe0);
628 /* set squelch amplitude to higher threshold */
629 rt305x_mii_write(esw, 0, 18, 0x40ba);
630 /* tune TP_IDL tail and head waveform, enable power
631 * down slew rate control
632 */
633 rt305x_mii_write(esw, 0, 22, 0x253f);
634 /* set PLL/Receive bias current are calibrated */
635 rt305x_mii_write(esw, 0, 27, 0x2fda);
636 /* change PLL/Receive bias current to internal(RT3350) */
637 rt305x_mii_write(esw, 0, 28, 0xc410);
638 /* change PLL bias current to internal(RT3052_MP3) */
639 rt305x_mii_write(esw, 0, 29, 0x598b);
640 /* select local register */
641 rt305x_mii_write(esw, 0, 31, 0x8000);
642 } else if (ralink_soc == MT762X_SOC_MT7628AN || ralink_soc == MT762X_SOC_MT7688) {
643 int i;
644
645 esw_reset_ephy(esw);
646
647 /* set the led polarity */
648 esw_w32(esw, esw->reg_led_polarity & 0x1F,
649 RT5350_EWS_REG_LED_POLARITY);
650
651 rt305x_mii_write(esw, 0, 31, 0x2000); /* change G2 page */
652 rt305x_mii_write(esw, 0, 26, 0x0020);
653
654 for (i = 0; i < 5; i++) {
655 rt305x_mii_write(esw, i, 31, 0x8000);
656 rt305x_mii_write(esw, i, 0, 0x3100);
657 rt305x_mii_write(esw, i, 30, 0xa000);
658 rt305x_mii_write(esw, i, 31, 0xa000);
659 rt305x_mii_write(esw, i, 16, 0x0606);
660 rt305x_mii_write(esw, i, 23, 0x0f0e);
661 rt305x_mii_write(esw, i, 24, 0x1610);
662 rt305x_mii_write(esw, i, 30, 0x1f15);
663 rt305x_mii_write(esw, i, 28, 0x6111);
664 rt305x_mii_write(esw, i, 31, 0x2000);
665 rt305x_mii_write(esw, i, 26, 0x0000);
666 }
667
668 /* 100Base AOI setting */
669 rt305x_mii_write(esw, 0, 31, 0x5000);
670 rt305x_mii_write(esw, 0, 19, 0x004a);
671 rt305x_mii_write(esw, 0, 20, 0x015a);
672 rt305x_mii_write(esw, 0, 21, 0x00ee);
673 rt305x_mii_write(esw, 0, 22, 0x0033);
674 rt305x_mii_write(esw, 0, 23, 0x020a);
675 rt305x_mii_write(esw, 0, 24, 0x0000);
676 rt305x_mii_write(esw, 0, 25, 0x024a);
677 rt305x_mii_write(esw, 0, 26, 0x035a);
678 rt305x_mii_write(esw, 0, 27, 0x02ee);
679 rt305x_mii_write(esw, 0, 28, 0x0233);
680 rt305x_mii_write(esw, 0, 29, 0x000a);
681 rt305x_mii_write(esw, 0, 30, 0x0000);
682 } else {
683 rt305x_mii_write(esw, 0, 31, 0x8000);
684 for (i = 0; i < 5; i++) {
685 if (esw->ports[i].disable) {
686 rt305x_mii_write(esw, i, MII_BMCR, BMCR_PDOWN);
687 } else {
688 rt305x_mii_write(esw, i, MII_BMCR,
689 BMCR_FULLDPLX |
690 BMCR_ANENABLE |
691 BMCR_SPEED100);
692 }
693 /* TX10 waveform coefficient */
694 rt305x_mii_write(esw, i, 26, 0x1601);
695 /* TX100/TX10 AD/DA current bias */
696 rt305x_mii_write(esw, i, 29, 0x7058);
697 /* TX100 slew rate control */
698 rt305x_mii_write(esw, i, 30, 0x0018);
699 }
700
701 /* PHY IOT */
702 /* select global register */
703 rt305x_mii_write(esw, 0, 31, 0x0);
704 /* tune TP_IDL tail and head waveform */
705 rt305x_mii_write(esw, 0, 22, 0x052f);
706 /* set TX10 signal amplitude threshold to minimum */
707 rt305x_mii_write(esw, 0, 17, 0x0fe0);
708 /* set squelch amplitude to higher threshold */
709 rt305x_mii_write(esw, 0, 18, 0x40ba);
710 /* longer TP_IDL tail length */
711 rt305x_mii_write(esw, 0, 14, 0x65);
712 /* select local register */
713 rt305x_mii_write(esw, 0, 31, 0x8000);
714 }
715
716 if (esw->port_map)
717 port_map = esw->port_map;
718 else
719 port_map = RT305X_ESW_PMAP_LLLLLL;
720
721 /* Unused HW feature, but still nice to be consistent here...
722 * This is also exported to userspace ('lan' attribute) so it's
723 * conveniently usable to decide which ports go into the wan vlan by
724 * default.
725 */
726 esw_rmw(esw, RT305X_ESW_REG_SGC2,
727 RT305X_ESW_SGC2_LAN_PMAP_M << RT305X_ESW_SGC2_LAN_PMAP_S,
728 port_map << RT305X_ESW_SGC2_LAN_PMAP_S);
729
730 /* make the switch leds blink */
731 for (i = 0; i < RT305X_ESW_NUM_LEDS; i++)
732 esw->ports[i].led = 0x05;
733
734 /* Apply the empty config. */
735 esw_apply_config(&esw->swdev);
736
737 /* Only unmask the port change interrupt */
738 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
739 }
740
741
742 int rt3050_esw_has_carrier(struct fe_priv *priv)
743 {
744 struct rt305x_esw *esw = priv->soc->swpriv;
745 u32 link;
746 int i;
747 bool cpuport;
748
749 link = esw_r32(esw, RT305X_ESW_REG_POA);
750 link >>= RT305X_ESW_POA_LINK_SHIFT;
751 cpuport = link & BIT(RT305X_ESW_PORT6);
752 link &= RT305X_ESW_POA_LINK_MASK;
753 for (i = 0; i <= RT305X_ESW_PORT5; i++) {
754 if (priv->link[i] != (link & BIT(i)))
755 dev_info(esw->dev, "port %d link %s\n", i, link & BIT(i) ? "up" : "down");
756 priv->link[i] = link & BIT(i);
757 }
758
759 return !!link && cpuport;
760 }
761
762 static irqreturn_t esw_interrupt(int irq, void *_esw)
763 {
764 struct rt305x_esw *esw = (struct rt305x_esw *) _esw;
765 u32 status;
766 int i;
767
768 status = esw_r32(esw, RT305X_ESW_REG_ISR);
769 if (status & RT305X_ESW_PORT_ST_CHG) {
770 if (!esw->priv)
771 goto out;
772 if (rt3050_esw_has_carrier(esw->priv))
773 netif_carrier_on(esw->priv->netdev);
774 else
775 netif_carrier_off(esw->priv->netdev);
776 }
777
778 out:
779 esw_w32(esw, status, RT305X_ESW_REG_ISR);
780
781 return IRQ_HANDLED;
782 }
783
784 static int esw_apply_config(struct switch_dev *dev)
785 {
786 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
787 int i;
788 u8 disable = 0;
789 u8 doubletag = 0;
790 u8 en_vlan = 0;
791 u8 untag = 0;
792
793 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
794 u32 vid, vmsc;
795 if (esw->global_vlan_enable) {
796 vid = esw->vlans[i].vid;
797 vmsc = esw->vlans[i].ports;
798 } else {
799 vid = RT305X_ESW_VLAN_NONE;
800 vmsc = RT305X_ESW_PORTS_NONE;
801 }
802 esw_set_vlan_id(esw, i, vid);
803 esw_set_vmsc(esw, i, vmsc);
804 }
805
806 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
807 u32 pvid;
808 disable |= esw->ports[i].disable << i;
809 if (esw->global_vlan_enable) {
810 doubletag |= esw->ports[i].doubletag << i;
811 en_vlan |= 1 << i;
812 untag |= esw->ports[i].untag << i;
813 pvid = esw->ports[i].pvid;
814 } else {
815 int x = esw->alt_vlan_disable ? 0 : 1;
816 doubletag |= x << i;
817 en_vlan |= x << i;
818 untag |= x << i;
819 pvid = 0;
820 }
821 esw_set_pvid(esw, i, pvid);
822 if (i < RT305X_ESW_NUM_LEDS)
823 esw_w32(esw, esw->ports[i].led,
824 RT305X_ESW_REG_P0LED + 4*i);
825 }
826
827 esw_set_gsc(esw);
828 esw_set_port_disable(esw, disable);
829 esw_rmw(esw, RT305X_ESW_REG_SGC2,
830 (RT305X_ESW_SGC2_DOUBLE_TAG_M <<
831 RT305X_ESW_SGC2_DOUBLE_TAG_S),
832 doubletag << RT305X_ESW_SGC2_DOUBLE_TAG_S);
833 esw_rmw(esw, RT305X_ESW_REG_PFC1,
834 RT305X_ESW_PFC1_EN_VLAN_M << RT305X_ESW_PFC1_EN_VLAN_S,
835 en_vlan << RT305X_ESW_PFC1_EN_VLAN_S);
836 esw_rmw(esw, RT305X_ESW_REG_POC2,
837 RT305X_ESW_POC2_UNTAG_EN_M << RT305X_ESW_POC2_UNTAG_EN_S,
838 untag << RT305X_ESW_POC2_UNTAG_EN_S);
839
840 if (!esw->global_vlan_enable) {
841 /*
842 * Still need to put all ports into vlan 0 or they'll be
843 * isolated.
844 * NOTE: vlan 0 is special, no vlan tag is prepended
845 */
846 esw_set_vlan_id(esw, 0, 0);
847 esw_set_vmsc(esw, 0, RT305X_ESW_PORTS_ALL);
848 }
849
850 return 0;
851 }
852
853 static int esw_reset_switch(struct switch_dev *dev)
854 {
855 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
856
857 esw->global_vlan_enable = 0;
858 memset(esw->ports, 0, sizeof(esw->ports));
859 memset(esw->vlans, 0, sizeof(esw->vlans));
860 esw_hw_init(esw);
861
862 return 0;
863 }
864
865 static int esw_get_vlan_enable(struct switch_dev *dev,
866 const struct switch_attr *attr,
867 struct switch_val *val)
868 {
869 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
870
871 val->value.i = esw->global_vlan_enable;
872
873 return 0;
874 }
875
876 static int esw_set_vlan_enable(struct switch_dev *dev,
877 const struct switch_attr *attr,
878 struct switch_val *val)
879 {
880 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
881
882 esw->global_vlan_enable = val->value.i != 0;
883
884 return 0;
885 }
886
887 static int esw_get_alt_vlan_disable(struct switch_dev *dev,
888 const struct switch_attr *attr,
889 struct switch_val *val)
890 {
891 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
892
893 val->value.i = esw->alt_vlan_disable;
894
895 return 0;
896 }
897
898 static int esw_set_alt_vlan_disable(struct switch_dev *dev,
899 const struct switch_attr *attr,
900 struct switch_val *val)
901 {
902 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
903
904 esw->alt_vlan_disable = val->value.i != 0;
905
906 return 0;
907 }
908
909 static int
910 rt305x_esw_set_bc_status(struct switch_dev *dev,
911 const struct switch_attr *attr,
912 struct switch_val *val)
913 {
914 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
915
916 esw->bc_storm_protect = val->value.i & RT305X_ESW_GSC_BC_STROM_MASK;
917
918 return 0;
919 }
920
921 static int
922 rt305x_esw_get_bc_status(struct switch_dev *dev,
923 const struct switch_attr *attr,
924 struct switch_val *val)
925 {
926 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
927
928 val->value.i = esw->bc_storm_protect;
929
930 return 0;
931 }
932
933 static int
934 rt305x_esw_set_led_freq(struct switch_dev *dev,
935 const struct switch_attr *attr,
936 struct switch_val *val)
937 {
938 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
939
940 esw->led_frequency = val->value.i & RT305X_ESW_GSC_LED_FREQ_MASK;
941
942 return 0;
943 }
944
945 static int
946 rt305x_esw_get_led_freq(struct switch_dev *dev,
947 const struct switch_attr *attr,
948 struct switch_val *val)
949 {
950 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
951
952 val->value.i = esw->led_frequency;
953
954 return 0;
955 }
956
957 static int esw_get_port_link(struct switch_dev *dev,
958 int port,
959 struct switch_port_link *link)
960 {
961 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
962 u32 speed, poa;
963
964 if (port < 0 || port >= RT305X_ESW_NUM_PORTS)
965 return -EINVAL;
966
967 poa = esw_r32(esw, RT305X_ESW_REG_POA) >> port;
968
969 link->link = (poa >> RT305X_ESW_LINK_S) & 1;
970 link->duplex = (poa >> RT305X_ESW_DUPLEX_S) & 1;
971 if (port < RT305X_ESW_NUM_LEDS) {
972 speed = (poa >> RT305X_ESW_SPD_S) & 1;
973 } else {
974 if (port == RT305X_ESW_NUM_PORTS - 1)
975 poa >>= 1;
976 speed = (poa >> RT305X_ESW_SPD_S) & 3;
977 }
978 switch (speed) {
979 case 0:
980 link->speed = SWITCH_PORT_SPEED_10;
981 break;
982 case 1:
983 link->speed = SWITCH_PORT_SPEED_100;
984 break;
985 case 2:
986 case 3: /* forced gige speed can be 2 or 3 */
987 link->speed = SWITCH_PORT_SPEED_1000;
988 break;
989 default:
990 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
991 break;
992 }
993
994 return 0;
995 }
996
997 static int esw_get_port_bool(struct switch_dev *dev,
998 const struct switch_attr *attr,
999 struct switch_val *val)
1000 {
1001 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1002 int idx = val->port_vlan;
1003 u32 x, reg, shift;
1004
1005 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS)
1006 return -EINVAL;
1007
1008 switch (attr->id) {
1009 case RT305X_ESW_ATTR_PORT_DISABLE:
1010 reg = RT305X_ESW_REG_POC0;
1011 shift = RT305X_ESW_POC0_DIS_PORT_S;
1012 break;
1013 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1014 reg = RT305X_ESW_REG_SGC2;
1015 shift = RT305X_ESW_SGC2_DOUBLE_TAG_S;
1016 break;
1017 case RT305X_ESW_ATTR_PORT_UNTAG:
1018 reg = RT305X_ESW_REG_POC2;
1019 shift = RT305X_ESW_POC2_UNTAG_EN_S;
1020 break;
1021 case RT305X_ESW_ATTR_PORT_LAN:
1022 reg = RT305X_ESW_REG_SGC2;
1023 shift = RT305X_ESW_SGC2_LAN_PMAP_S;
1024 if (idx >= RT305X_ESW_NUM_LANWAN)
1025 return -EINVAL;
1026 break;
1027 default:
1028 return -EINVAL;
1029 }
1030
1031 x = esw_r32(esw, reg);
1032 val->value.i = (x >> (idx + shift)) & 1;
1033
1034 return 0;
1035 }
1036
1037 static int esw_set_port_bool(struct switch_dev *dev,
1038 const struct switch_attr *attr,
1039 struct switch_val *val)
1040 {
1041 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1042 int idx = val->port_vlan;
1043
1044 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1045 val->value.i < 0 || val->value.i > 1)
1046 return -EINVAL;
1047
1048 switch (attr->id) {
1049 case RT305X_ESW_ATTR_PORT_DISABLE:
1050 esw->ports[idx].disable = val->value.i;
1051 break;
1052 case RT305X_ESW_ATTR_PORT_DOUBLETAG:
1053 esw->ports[idx].doubletag = val->value.i;
1054 break;
1055 case RT305X_ESW_ATTR_PORT_UNTAG:
1056 esw->ports[idx].untag = val->value.i;
1057 break;
1058 default:
1059 return -EINVAL;
1060 }
1061
1062 return 0;
1063 }
1064
1065 static int esw_get_port_recv_badgood(struct switch_dev *dev,
1066 const struct switch_attr *attr,
1067 struct switch_val *val)
1068 {
1069 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1070 int idx = val->port_vlan;
1071 int shift = attr->id == RT305X_ESW_ATTR_PORT_RECV_GOOD ? 0 : 16;
1072 u32 reg;
1073
1074 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1075 return -EINVAL;
1076 reg = esw_r32(esw, RT305X_ESW_REG_PXPC(idx));
1077 val->value.i = (reg >> shift) & 0xffff;
1078
1079 return 0;
1080 }
1081
1082 static int
1083 esw_get_port_tr_badgood(struct switch_dev *dev,
1084 const struct switch_attr *attr,
1085 struct switch_val *val)
1086 {
1087 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1088
1089 int idx = val->port_vlan;
1090 int shift = attr->id == RT5350_ESW_ATTR_PORT_TR_GOOD ? 0 : 16;
1091 u32 reg;
1092
1093 if ((ralink_soc != RT305X_SOC_RT5350) && (ralink_soc != MT762X_SOC_MT7628AN) && (ralink_soc != MT762X_SOC_MT7688))
1094 return -EINVAL;
1095
1096 if (idx < 0 || idx >= RT305X_ESW_NUM_LANWAN)
1097 return -EINVAL;
1098
1099 reg = esw_r32(esw, RT5350_ESW_REG_PXTPC(idx));
1100 val->value.i = (reg >> shift) & 0xffff;
1101
1102 return 0;
1103 }
1104
1105 static int esw_get_port_led(struct switch_dev *dev,
1106 const struct switch_attr *attr,
1107 struct switch_val *val)
1108 {
1109 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1110 int idx = val->port_vlan;
1111
1112 if (idx < 0 || idx >= RT305X_ESW_NUM_PORTS ||
1113 idx >= RT305X_ESW_NUM_LEDS)
1114 return -EINVAL;
1115
1116 val->value.i = esw_r32(esw, RT305X_ESW_REG_P0LED + 4*idx);
1117
1118 return 0;
1119 }
1120
1121 static int esw_set_port_led(struct switch_dev *dev,
1122 const struct switch_attr *attr,
1123 struct switch_val *val)
1124 {
1125 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1126 int idx = val->port_vlan;
1127
1128 if (idx < 0 || idx >= RT305X_ESW_NUM_LEDS)
1129 return -EINVAL;
1130
1131 esw->ports[idx].led = val->value.i;
1132
1133 return 0;
1134 }
1135
1136 static int esw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1137 {
1138 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1139
1140 if (port >= RT305X_ESW_NUM_PORTS)
1141 return -EINVAL;
1142
1143 *val = esw_get_pvid(esw, port);
1144
1145 return 0;
1146 }
1147
1148 static int esw_set_port_pvid(struct switch_dev *dev, int port, int val)
1149 {
1150 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1151
1152 if (port >= RT305X_ESW_NUM_PORTS)
1153 return -EINVAL;
1154
1155 esw->ports[port].pvid = val;
1156
1157 return 0;
1158 }
1159
1160 static int esw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1161 {
1162 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1163 u32 vmsc, poc2;
1164 int vlan_idx = -1;
1165 int i;
1166
1167 val->len = 0;
1168
1169 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS)
1170 return -EINVAL;
1171
1172 /* valid vlan? */
1173 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1174 if (esw_get_vlan_id(esw, i) == val->port_vlan &&
1175 esw_get_vmsc(esw, i) != RT305X_ESW_PORTS_NONE) {
1176 vlan_idx = i;
1177 break;
1178 }
1179 }
1180
1181 if (vlan_idx == -1)
1182 return -EINVAL;
1183
1184 vmsc = esw_get_vmsc(esw, vlan_idx);
1185 poc2 = esw_r32(esw, RT305X_ESW_REG_POC2);
1186
1187 for (i = 0; i < RT305X_ESW_NUM_PORTS; i++) {
1188 struct switch_port *p;
1189 int port_mask = 1 << i;
1190
1191 if (!(vmsc & port_mask))
1192 continue;
1193
1194 p = &val->value.ports[val->len++];
1195 p->id = i;
1196 if (poc2 & (port_mask << RT305X_ESW_POC2_UNTAG_EN_S))
1197 p->flags = 0;
1198 else
1199 p->flags = 1 << SWITCH_PORT_FLAG_TAGGED;
1200 }
1201
1202 return 0;
1203 }
1204
1205 static int esw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
1206 {
1207 struct rt305x_esw *esw = container_of(dev, struct rt305x_esw, swdev);
1208 int ports;
1209 int vlan_idx = -1;
1210 int i;
1211
1212 if (val->port_vlan < 0 || val->port_vlan >= RT305X_ESW_NUM_VIDS ||
1213 val->len > RT305X_ESW_NUM_PORTS)
1214 return -EINVAL;
1215
1216 /* one of the already defined vlans? */
1217 for (i = 0; i < RT305X_ESW_NUM_VLANS; i++) {
1218 if (esw->vlans[i].vid == val->port_vlan &&
1219 esw->vlans[i].ports != RT305X_ESW_PORTS_NONE) {
1220 vlan_idx = i;
1221 break;
1222 }
1223 }
1224
1225 /* select a free slot */
1226 for (i = 0; vlan_idx == -1 && i < RT305X_ESW_NUM_VLANS; i++) {
1227 if (esw->vlans[i].ports == RT305X_ESW_PORTS_NONE)
1228 vlan_idx = i;
1229 }
1230
1231 /* bail if all slots are in use */
1232 if (vlan_idx == -1)
1233 return -EINVAL;
1234
1235 ports = RT305X_ESW_PORTS_NONE;
1236 for (i = 0; i < val->len; i++) {
1237 struct switch_port *p = &val->value.ports[i];
1238 int port_mask = 1 << p->id;
1239 bool untagged = !(p->flags & (1 << SWITCH_PORT_FLAG_TAGGED));
1240
1241 if (p->id >= RT305X_ESW_NUM_PORTS)
1242 return -EINVAL;
1243
1244 ports |= port_mask;
1245 esw->ports[p->id].untag = untagged;
1246 }
1247 esw->vlans[vlan_idx].ports = ports;
1248 if (ports == RT305X_ESW_PORTS_NONE)
1249 esw->vlans[vlan_idx].vid = RT305X_ESW_VLAN_NONE;
1250 else
1251 esw->vlans[vlan_idx].vid = val->port_vlan;
1252
1253 return 0;
1254 }
1255
1256 static const struct switch_attr esw_global[] = {
1257 {
1258 .type = SWITCH_TYPE_INT,
1259 .name = "enable_vlan",
1260 .description = "VLAN mode (1:enabled)",
1261 .max = 1,
1262 .id = RT305X_ESW_ATTR_ENABLE_VLAN,
1263 .get = esw_get_vlan_enable,
1264 .set = esw_set_vlan_enable,
1265 },
1266 {
1267 .type = SWITCH_TYPE_INT,
1268 .name = "alternate_vlan_disable",
1269 .description = "Use en_vlan instead of doubletag to disable"
1270 " VLAN mode",
1271 .max = 1,
1272 .id = RT305X_ESW_ATTR_ALT_VLAN_DISABLE,
1273 .get = esw_get_alt_vlan_disable,
1274 .set = esw_set_alt_vlan_disable,
1275 },
1276 {
1277 .type = SWITCH_TYPE_INT,
1278 .name = "bc_storm_protect",
1279 .description = "Global broadcast storm protection (0:Disable, 1:64 blocks, 2:96 blocks, 3:128 blocks)",
1280 .max = 3,
1281 .id = RT305X_ESW_ATTR_BC_STATUS,
1282 .get = rt305x_esw_get_bc_status,
1283 .set = rt305x_esw_set_bc_status,
1284 },
1285 {
1286 .type = SWITCH_TYPE_INT,
1287 .name = "led_frequency",
1288 .description = "LED Flash frequency (0:30mS, 1:60mS, 2:240mS, 3:480mS)",
1289 .max = 3,
1290 .id = RT305X_ESW_ATTR_LED_FREQ,
1291 .get = rt305x_esw_get_led_freq,
1292 .set = rt305x_esw_set_led_freq,
1293 }
1294 };
1295
1296 static const struct switch_attr esw_port[] = {
1297 {
1298 .type = SWITCH_TYPE_INT,
1299 .name = "disable",
1300 .description = "Port state (1:disabled)",
1301 .max = 1,
1302 .id = RT305X_ESW_ATTR_PORT_DISABLE,
1303 .get = esw_get_port_bool,
1304 .set = esw_set_port_bool,
1305 },
1306 {
1307 .type = SWITCH_TYPE_INT,
1308 .name = "doubletag",
1309 .description = "Double tagging for incoming vlan packets "
1310 "(1:enabled)",
1311 .max = 1,
1312 .id = RT305X_ESW_ATTR_PORT_DOUBLETAG,
1313 .get = esw_get_port_bool,
1314 .set = esw_set_port_bool,
1315 },
1316 {
1317 .type = SWITCH_TYPE_INT,
1318 .name = "untag",
1319 .description = "Untag (1:strip outgoing vlan tag)",
1320 .max = 1,
1321 .id = RT305X_ESW_ATTR_PORT_UNTAG,
1322 .get = esw_get_port_bool,
1323 .set = esw_set_port_bool,
1324 },
1325 {
1326 .type = SWITCH_TYPE_INT,
1327 .name = "led",
1328 .description = "LED mode (0:link, 1:100m, 2:duplex, 3:activity,"
1329 " 4:collision, 5:linkact, 6:duplcoll, 7:10mact,"
1330 " 8:100mact, 10:blink, 11:off, 12:on)",
1331 .max = 15,
1332 .id = RT305X_ESW_ATTR_PORT_LED,
1333 .get = esw_get_port_led,
1334 .set = esw_set_port_led,
1335 },
1336 {
1337 .type = SWITCH_TYPE_INT,
1338 .name = "lan",
1339 .description = "HW port group (0:wan, 1:lan)",
1340 .max = 1,
1341 .id = RT305X_ESW_ATTR_PORT_LAN,
1342 .get = esw_get_port_bool,
1343 },
1344 {
1345 .type = SWITCH_TYPE_INT,
1346 .name = "recv_bad",
1347 .description = "Receive bad packet counter",
1348 .id = RT305X_ESW_ATTR_PORT_RECV_BAD,
1349 .get = esw_get_port_recv_badgood,
1350 },
1351 {
1352 .type = SWITCH_TYPE_INT,
1353 .name = "recv_good",
1354 .description = "Receive good packet counter",
1355 .id = RT305X_ESW_ATTR_PORT_RECV_GOOD,
1356 .get = esw_get_port_recv_badgood,
1357 },
1358 {
1359 .type = SWITCH_TYPE_INT,
1360 .name = "tr_bad",
1361
1362 .description = "Transmit bad packet counter. rt5350 only",
1363 .id = RT5350_ESW_ATTR_PORT_TR_BAD,
1364 .get = esw_get_port_tr_badgood,
1365 },
1366 {
1367 .type = SWITCH_TYPE_INT,
1368 .name = "tr_good",
1369
1370 .description = "Transmit good packet counter. rt5350 only",
1371 .id = RT5350_ESW_ATTR_PORT_TR_GOOD,
1372 .get = esw_get_port_tr_badgood,
1373 },
1374 };
1375
1376 static const struct switch_attr esw_vlan[] = {
1377 };
1378
1379 static const struct switch_dev_ops esw_ops = {
1380 .attr_global = {
1381 .attr = esw_global,
1382 .n_attr = ARRAY_SIZE(esw_global),
1383 },
1384 .attr_port = {
1385 .attr = esw_port,
1386 .n_attr = ARRAY_SIZE(esw_port),
1387 },
1388 .attr_vlan = {
1389 .attr = esw_vlan,
1390 .n_attr = ARRAY_SIZE(esw_vlan),
1391 },
1392 .get_vlan_ports = esw_get_vlan_ports,
1393 .set_vlan_ports = esw_set_vlan_ports,
1394 .get_port_pvid = esw_get_port_pvid,
1395 .set_port_pvid = esw_set_port_pvid,
1396 .get_port_link = esw_get_port_link,
1397 .apply_config = esw_apply_config,
1398 .reset_switch = esw_reset_switch,
1399 };
1400
1401 static int esw_probe(struct platform_device *pdev)
1402 {
1403 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1404 struct device_node *np = pdev->dev.of_node;
1405 const __be32 *port_map, *port_disable, *reg_init;
1406 struct rt305x_esw *esw;
1407
1408 esw = devm_kzalloc(&pdev->dev, sizeof(*esw), GFP_KERNEL);
1409 if (!esw)
1410 return -ENOMEM;
1411
1412 esw->dev = &pdev->dev;
1413 esw->irq = irq_of_parse_and_map(np, 0);
1414 esw->base = devm_ioremap_resource(&pdev->dev, res);
1415 if (IS_ERR(esw->base))
1416 return PTR_ERR(esw->base);
1417
1418 port_map = of_get_property(np, "mediatek,portmap", NULL);
1419 if (port_map)
1420 esw->port_map = be32_to_cpu(*port_map);
1421
1422 port_disable = of_get_property(np, "mediatek,portdisable", NULL);
1423 if (port_disable)
1424 esw->port_disable = be32_to_cpu(*port_disable);
1425
1426 reg_init = of_get_property(np, "ralink,fct2", NULL);
1427 if (reg_init)
1428 esw->reg_initval_fct2 = be32_to_cpu(*reg_init);
1429
1430 reg_init = of_get_property(np, "ralink,fpa2", NULL);
1431 if (reg_init)
1432 esw->reg_initval_fpa2 = be32_to_cpu(*reg_init);
1433
1434 reg_init = of_get_property(np, "mediatek,led_polarity", NULL);
1435 if (reg_init)
1436 esw->reg_led_polarity = be32_to_cpu(*reg_init);
1437
1438 esw->rst_esw = devm_reset_control_get(&pdev->dev, "esw");
1439 if (IS_ERR(esw->rst_esw))
1440 esw->rst_esw = NULL;
1441 esw->rst_ephy = devm_reset_control_get(&pdev->dev, "ephy");
1442 if (IS_ERR(esw->rst_ephy))
1443 esw->rst_ephy = NULL;
1444
1445 spin_lock_init(&esw->reg_rw_lock);
1446 platform_set_drvdata(pdev, esw);
1447
1448 return 0;
1449 }
1450
1451 static int esw_remove(struct platform_device *pdev)
1452 {
1453 struct rt305x_esw *esw = platform_get_drvdata(pdev);
1454
1455 if (esw) {
1456 esw_w32(esw, ~0, RT305X_ESW_REG_IMR);
1457 platform_set_drvdata(pdev, NULL);
1458 }
1459
1460 return 0;
1461 }
1462
1463 static const struct of_device_id ralink_esw_match[] = {
1464 { .compatible = "ralink,rt3050-esw" },
1465 {},
1466 };
1467 MODULE_DEVICE_TABLE(of, ralink_esw_match);
1468
1469 /* called by the ethernet driver to bound with the switch driver */
1470 int rt3050_esw_init(struct fe_priv *priv)
1471 {
1472 struct device_node *np = priv->switch_np;
1473 struct platform_device *pdev = of_find_device_by_node(np);
1474 struct switch_dev *swdev;
1475 struct rt305x_esw *esw;
1476 const __be32 *rgmii;
1477 int ret;
1478
1479 if (!pdev)
1480 return -ENODEV;
1481
1482 if (!of_device_is_compatible(np, ralink_esw_match->compatible))
1483 return -EINVAL;
1484
1485 esw = platform_get_drvdata(pdev);
1486 if (!esw)
1487 return -EPROBE_DEFER;
1488
1489 priv->soc->swpriv = esw;
1490 esw->priv = priv;
1491
1492 esw_hw_init(esw);
1493
1494 rgmii = of_get_property(np, "ralink,rgmii", NULL);
1495 if (rgmii && be32_to_cpu(*rgmii) == 1) {
1496 /*
1497 * External switch connected to RGMII interface.
1498 * Unregister the switch device after initialization.
1499 */
1500 dev_err(&pdev->dev, "RGMII mode, not exporting switch device.\n");
1501 unregister_switch(&esw->swdev);
1502 platform_set_drvdata(pdev, NULL);
1503 return -ENODEV;
1504 }
1505
1506 swdev = &esw->swdev;
1507 swdev->of_node = pdev->dev.of_node;
1508 swdev->name = "rt305x-esw";
1509 swdev->alias = "rt305x";
1510 swdev->cpu_port = RT305X_ESW_PORT6;
1511 swdev->ports = RT305X_ESW_NUM_PORTS;
1512 swdev->vlans = RT305X_ESW_NUM_VIDS;
1513 swdev->ops = &esw_ops;
1514
1515 ret = register_switch(swdev, NULL);
1516 if (ret < 0) {
1517 dev_err(&pdev->dev, "register_switch failed\n");
1518 return ret;
1519 }
1520
1521 ret = devm_request_irq(&pdev->dev, esw->irq, esw_interrupt, 0, "esw",
1522 esw);
1523 if (!ret) {
1524 esw_w32(esw, RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_ISR);
1525 esw_w32(esw, ~RT305X_ESW_PORT_ST_CHG, RT305X_ESW_REG_IMR);
1526 }
1527
1528 dev_info(&pdev->dev, "mediatek esw at 0x%08lx, irq %d initialized\n",
1529 esw->base, esw->irq);
1530
1531 return 0;
1532 }
1533
1534 static struct platform_driver esw_driver = {
1535 .probe = esw_probe,
1536 .remove = esw_remove,
1537 .driver = {
1538 .name = "rt3050-esw",
1539 .owner = THIS_MODULE,
1540 .of_match_table = ralink_esw_match,
1541 },
1542 };
1543
1544 module_platform_driver(esw_driver);
1545
1546 MODULE_LICENSE("GPL");
1547 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1548 MODULE_DESCRIPTION("Switch driver for RT305X SoC");
1549 MODULE_VERSION(MTK_FE_DRV_VERSION);
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