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ramips: properly setup the FEATURES variable
[openwrt/staging/wigyori.git] / target / linux / ramips / files-3.7 / drivers / usb / dwc_otg / dwc_otg_hcd_intr.c
1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
3 * $Revision: 1.6.2.1 $
4 * $Date: 2009-04-22 03:48:22 $
5 * $Change: 1117667 $
6 *
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
10 *
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
20 *
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31 * DAMAGE.
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
34
35 #include <linux/version.h>
36
37 #include "dwc_otg_driver.h"
38 #include "dwc_otg_hcd.h"
39 #include "dwc_otg_regs.h"
40
41 /** @file
42 * This file contains the implementation of the HCD Interrupt handlers.
43 */
44
45 /** This function handles interrupts for the HCD. */
46 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t *dwc_otg_hcd)
47 {
48 int retval = 0;
49
50 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
51 gintsts_data_t gintsts;
52 #ifdef DEBUG
53 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
54 #endif
55
56 /* Check if HOST Mode */
57 if (dwc_otg_is_host_mode(core_if)) {
58 gintsts.d32 = dwc_otg_read_core_intr(core_if);
59 if (!gintsts.d32) {
60 return 0;
61 }
62
63 #ifdef DEBUG
64 /* Don't print debug message in the interrupt handler on SOF */
65 # ifndef DEBUG_SOF
66 if (gintsts.d32 != DWC_SOF_INTR_MASK)
67 # endif
68 DWC_DEBUGPL(DBG_HCD, "\n");
69 #endif
70
71 #ifdef DEBUG
72 # ifndef DEBUG_SOF
73 if (gintsts.d32 != DWC_SOF_INTR_MASK)
74 # endif
75 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32);
76 #endif
77 if (gintsts.b.usbreset) {
78 DWC_PRINT("Usb Reset In Host Mode\n");
79 }
80
81
82 if (gintsts.b.sofintr) {
83 retval |= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd);
84 }
85 if (gintsts.b.rxstsqlvl) {
86 retval |= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd);
87 }
88 if (gintsts.b.nptxfempty) {
89 retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd);
90 }
91 if (gintsts.b.i2cintr) {
92 /** @todo Implement i2cintr handler. */
93 }
94 if (gintsts.b.portintr) {
95 retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
96 }
97 if (gintsts.b.hcintr) {
98 retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
99 }
100 if (gintsts.b.ptxfempty) {
101 retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd);
102 }
103 #ifdef DEBUG
104 # ifndef DEBUG_SOF
105 if (gintsts.d32 != DWC_SOF_INTR_MASK)
106 # endif
107 {
108 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
109 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
110 dwc_read_reg32(&global_regs->gintsts));
111 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
112 dwc_read_reg32(&global_regs->gintmsk));
113 }
114 #endif
115
116 #ifdef DEBUG
117 # ifndef DEBUG_SOF
118 if (gintsts.d32 != DWC_SOF_INTR_MASK)
119 # endif
120 DWC_DEBUGPL(DBG_HCD, "\n");
121 #endif
122
123 }
124
125 S3C2410X_CLEAR_EINTPEND();
126
127 return retval;
128 }
129
130 #ifdef DWC_TRACK_MISSED_SOFS
131 #warning Compiling code to track missed SOFs
132 #define FRAME_NUM_ARRAY_SIZE 1000
133 /**
134 * This function is for debug only.
135 */
136 static inline void track_missed_sofs(uint16_t curr_frame_number)
137 {
138 static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE];
139 static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
140 static int frame_num_idx = 0;
141 static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM;
142 static int dumped_frame_num_array = 0;
143
144 if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
145 if (((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != curr_frame_number) {
146 frame_num_array[frame_num_idx] = curr_frame_number;
147 last_frame_num_array[frame_num_idx++] = last_frame_num;
148 }
149 } else if (!dumped_frame_num_array) {
150 int i;
151 printk(KERN_EMERG USB_DWC "Frame Last Frame\n");
152 printk(KERN_EMERG USB_DWC "----- ----------\n");
153 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
154 printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n",
155 frame_num_array[i], last_frame_num_array[i]);
156 }
157 dumped_frame_num_array = 1;
158 }
159 last_frame_num = curr_frame_number;
160 }
161 #endif
162
163 /**
164 * Handles the start-of-frame interrupt in host mode. Non-periodic
165 * transactions may be queued to the DWC_otg controller for the current
166 * (micro)frame. Periodic transactions may be queued to the controller for the
167 * next (micro)frame.
168 */
169 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t *hcd)
170 {
171 hfnum_data_t hfnum;
172 struct list_head *qh_entry;
173 dwc_otg_qh_t *qh;
174 dwc_otg_transaction_type_e tr_type;
175 gintsts_data_t gintsts = {.d32 = 0};
176
177 hfnum.d32 = dwc_read_reg32(&hcd->core_if->host_if->host_global_regs->hfnum);
178
179 #ifdef DEBUG_SOF
180 DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
181 #endif
182 hcd->frame_number = hfnum.b.frnum;
183
184 #ifdef DEBUG
185 hcd->frrem_accum += hfnum.b.frrem;
186 hcd->frrem_samples++;
187 #endif
188
189 #ifdef DWC_TRACK_MISSED_SOFS
190 track_missed_sofs(hcd->frame_number);
191 #endif
192
193 /* Determine whether any periodic QHs should be executed. */
194 qh_entry = hcd->periodic_sched_inactive.next;
195 while (qh_entry != &hcd->periodic_sched_inactive) {
196 qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
197 qh_entry = qh_entry->next;
198 if (dwc_frame_num_le(qh->sched_frame, hcd->frame_number)) {
199 /*
200 * Move QH to the ready list to be executed next
201 * (micro)frame.
202 */
203 list_move(&qh->qh_list_entry, &hcd->periodic_sched_ready);
204 }
205 }
206
207 tr_type = dwc_otg_hcd_select_transactions(hcd);
208 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
209 dwc_otg_hcd_queue_transactions(hcd, tr_type);
210 }
211
212 /* Clear interrupt */
213 gintsts.b.sofintr = 1;
214 dwc_write_reg32(&hcd->core_if->core_global_regs->gintsts, gintsts.d32);
215
216 return 1;
217 }
218
219 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
220 * least one packet in the Rx FIFO. The packets are moved from the FIFO to
221 * memory if the DWC_otg controller is operating in Slave mode. */
222 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t *dwc_otg_hcd)
223 {
224 host_grxsts_data_t grxsts;
225 dwc_hc_t *hc = NULL;
226
227 DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
228
229 grxsts.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->core_global_regs->grxstsp);
230
231 hc = dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
232
233 /* Packet Status */
234 DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum);
235 DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt);
236 DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
237 DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts);
238
239 switch (grxsts.b.pktsts) {
240 case DWC_GRXSTS_PKTSTS_IN:
241 /* Read the data into the host buffer. */
242 if (grxsts.b.bcnt > 0) {
243 dwc_otg_read_packet(dwc_otg_hcd->core_if,
244 hc->xfer_buff,
245 grxsts.b.bcnt);
246
247 /* Update the HC fields for the next packet received. */
248 hc->xfer_count += grxsts.b.bcnt;
249 hc->xfer_buff += grxsts.b.bcnt;
250 }
251
252 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
253 case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
254 case DWC_GRXSTS_PKTSTS_CH_HALTED:
255 /* Handled in interrupt, just ignore data */
256 break;
257 default:
258 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
259 break;
260 }
261
262 return 1;
263 }
264
265 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
266 * data packets may be written to the FIFO for OUT transfers. More requests
267 * may be written to the non-periodic request queue for IN transfers. This
268 * interrupt is enabled only in Slave mode. */
269 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
270 {
271 DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
272 dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
273 DWC_OTG_TRANSACTION_NON_PERIODIC);
274 return 1;
275 }
276
277 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
278 * packets may be written to the FIFO for OUT transfers. More requests may be
279 * written to the periodic request queue for IN transfers. This interrupt is
280 * enabled only in Slave mode. */
281 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t *dwc_otg_hcd)
282 {
283 DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
284 dwc_otg_hcd_queue_transactions(dwc_otg_hcd,
285 DWC_OTG_TRANSACTION_PERIODIC);
286 return 1;
287 }
288
289 /** There are multiple conditions that can cause a port interrupt. This function
290 * determines which interrupt conditions have occurred and handles them
291 * appropriately. */
292 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t *dwc_otg_hcd)
293 {
294 int retval = 0;
295 hprt0_data_t hprt0;
296 hprt0_data_t hprt0_modify;
297
298 hprt0.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
299 hprt0_modify.d32 = dwc_read_reg32(dwc_otg_hcd->core_if->host_if->hprt0);
300
301 /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
302 * GINTSTS */
303
304 hprt0_modify.b.prtena = 0;
305 hprt0_modify.b.prtconndet = 0;
306 hprt0_modify.b.prtenchng = 0;
307 hprt0_modify.b.prtovrcurrchng = 0;
308
309 /* Port Connect Detected
310 * Set flag and clear if detected */
311 if (hprt0.b.prtconndet) {
312 DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
313 "Port Connect Detected--\n", hprt0.d32);
314 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
315 dwc_otg_hcd->flags.b.port_connect_status = 1;
316 hprt0_modify.b.prtconndet = 1;
317
318 /* B-Device has connected, Delete the connection timer. */
319 del_timer( &dwc_otg_hcd->conn_timer );
320
321 /* The Hub driver asserts a reset when it sees port connect
322 * status change flag */
323 retval |= 1;
324 }
325
326 /* Port Enable Changed
327 * Clear if detected - Set internal flag if disabled */
328 if (hprt0.b.prtenchng) {
329 DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
330 "Port Enable Changed--\n", hprt0.d32);
331 hprt0_modify.b.prtenchng = 1;
332 if (hprt0.b.prtena == 1) {
333 int do_reset = 0;
334 dwc_otg_core_params_t *params = dwc_otg_hcd->core_if->core_params;
335 dwc_otg_core_global_regs_t *global_regs = dwc_otg_hcd->core_if->core_global_regs;
336 dwc_otg_host_if_t *host_if = dwc_otg_hcd->core_if->host_if;
337
338 /* Check if we need to adjust the PHY clock speed for
339 * low power and adjust it */
340 if (params->host_support_fs_ls_low_power) {
341 gusbcfg_data_t usbcfg;
342
343 usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg);
344
345 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED ||
346 hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED) {
347 /*
348 * Low power
349 */
350 hcfg_data_t hcfg;
351 if (usbcfg.b.phylpwrclksel == 0) {
352 /* Set PHY low power clock select for FS/LS devices */
353 usbcfg.b.phylpwrclksel = 1;
354 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
355 do_reset = 1;
356 }
357
358 hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
359
360 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED &&
361 params->host_ls_low_power_phy_clk ==
362 DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
363 /* 6 MHZ */
364 DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
365 if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
366 hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
367 dwc_write_reg32(&host_if->host_global_regs->hcfg,
368 hcfg.d32);
369 do_reset = 1;
370 }
371 } else {
372 /* 48 MHZ */
373 DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
374 if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
375 hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
376 dwc_write_reg32(&host_if->host_global_regs->hcfg,
377 hcfg.d32);
378 do_reset = 1;
379 }
380 }
381 } else {
382 /*
383 * Not low power
384 */
385 if (usbcfg.b.phylpwrclksel == 1) {
386 usbcfg.b.phylpwrclksel = 0;
387 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
388 do_reset = 1;
389 }
390 }
391
392 if (do_reset) {
393 tasklet_schedule(dwc_otg_hcd->reset_tasklet);
394 }
395 }
396
397 if (!do_reset) {
398 /* Port has been enabled set the reset change flag */
399 dwc_otg_hcd->flags.b.port_reset_change = 1;
400 }
401 } else {
402 dwc_otg_hcd->flags.b.port_enable_change = 1;
403 }
404 retval |= 1;
405 }
406
407 /** Overcurrent Change Interrupt */
408 if (hprt0.b.prtovrcurrchng) {
409 DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x "
410 "Port Overcurrent Changed--\n", hprt0.d32);
411 dwc_otg_hcd->flags.b.port_over_current_change = 1;
412 hprt0_modify.b.prtovrcurrchng = 1;
413 retval |= 1;
414 }
415
416 /* Clear Port Interrupts */
417 dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
418
419 return retval;
420 }
421
422 /** This interrupt indicates that one or more host channels has a pending
423 * interrupt. There are multiple conditions that can cause each host channel
424 * interrupt. This function determines which conditions have occurred for each
425 * host channel interrupt and handles them appropriately. */
426 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t *dwc_otg_hcd)
427 {
428 int i;
429 int retval = 0;
430 haint_data_t haint;
431
432 /* Clear appropriate bits in HCINTn to clear the interrupt bit in
433 * GINTSTS */
434
435 haint.d32 = dwc_otg_read_host_all_channels_intr(dwc_otg_hcd->core_if);
436
437 for (i = 0; i < dwc_otg_hcd->core_if->core_params->host_channels; i++) {
438 if (haint.b2.chint & (1 << i)) {
439 retval |= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd, i);
440 }
441 }
442
443 return retval;
444 }
445
446 /* Macro used to clear one channel interrupt */
447 #define clear_hc_int(_hc_regs_, _intr_) \
448 do { \
449 hcint_data_t hcint_clear = {.d32 = 0}; \
450 hcint_clear.b._intr_ = 1; \
451 dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
452 } while (0)
453
454 /*
455 * Macro used to disable one channel interrupt. Channel interrupts are
456 * disabled when the channel is halted or released by the interrupt handler.
457 * There is no need to handle further interrupts of that type until the
458 * channel is re-assigned. In fact, subsequent handling may cause crashes
459 * because the channel structures are cleaned up when the channel is released.
460 */
461 #define disable_hc_int(_hc_regs_, _intr_) \
462 do { \
463 hcintmsk_data_t hcintmsk = {.d32 = 0}; \
464 hcintmsk.b._intr_ = 1; \
465 dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
466 } while (0)
467
468 /**
469 * Gets the actual length of a transfer after the transfer halts. _halt_status
470 * holds the reason for the halt.
471 *
472 * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
473 * *short_read is set to 1 upon return if less than the requested
474 * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
475 * return. short_read may also be NULL on entry, in which case it remains
476 * unchanged.
477 */
478 static uint32_t get_actual_xfer_length(dwc_hc_t *hc,
479 dwc_otg_hc_regs_t *hc_regs,
480 dwc_otg_qtd_t *qtd,
481 dwc_otg_halt_status_e halt_status,
482 int *short_read)
483 {
484 hctsiz_data_t hctsiz;
485 uint32_t length;
486
487 if (short_read != NULL) {
488 *short_read = 0;
489 }
490 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
491
492 if (halt_status == DWC_OTG_HC_XFER_COMPLETE) {
493 if (hc->ep_is_in) {
494 length = hc->xfer_len - hctsiz.b.xfersize;
495 if (short_read != NULL) {
496 *short_read = (hctsiz.b.xfersize != 0);
497 }
498 } else if (hc->qh->do_split) {
499 length = qtd->ssplit_out_xfer_count;
500 } else {
501 length = hc->xfer_len;
502 }
503 } else {
504 /*
505 * Must use the hctsiz.pktcnt field to determine how much data
506 * has been transferred. This field reflects the number of
507 * packets that have been transferred via the USB. This is
508 * always an integral number of packets if the transfer was
509 * halted before its normal completion. (Can't use the
510 * hctsiz.xfersize field because that reflects the number of
511 * bytes transferred via the AHB, not the USB).
512 */
513 length = (hc->start_pkt_count - hctsiz.b.pktcnt) * hc->max_packet;
514 }
515
516 return length;
517 }
518
519 /**
520 * Updates the state of the URB after a Transfer Complete interrupt on the
521 * host channel. Updates the actual_length field of the URB based on the
522 * number of bytes transferred via the host channel. Sets the URB status
523 * if the data transfer is finished.
524 *
525 * @return 1 if the data transfer specified by the URB is completely finished,
526 * 0 otherwise.
527 */
528 static int update_urb_state_xfer_comp(dwc_hc_t *hc,
529 dwc_otg_hc_regs_t *hc_regs,
530 struct urb *urb,
531 dwc_otg_qtd_t *qtd)
532 {
533 int xfer_done = 0;
534 int short_read = 0;
535 int overflow_read=0;
536 uint32_t len = 0;
537 int max_packet;
538
539 len = get_actual_xfer_length(hc, hc_regs, qtd,
540 DWC_OTG_HC_XFER_COMPLETE,
541 &short_read);
542
543 /* Data overflow case: by Steven */
544 if (len > urb->transfer_buffer_length) {
545 len = urb->transfer_buffer_length;
546 overflow_read = 1;
547 }
548
549 /* non DWORD-aligned buffer case handling. */
550 if (((uint32_t)hc->xfer_buff & 0x3) && len && hc->qh->dw_align_buf && hc->ep_is_in) {
551 memcpy(urb->transfer_buffer + urb->actual_length, hc->qh->dw_align_buf, len);
552 }
553 urb->actual_length +=len;
554
555 max_packet = usb_maxpacket(urb->dev, urb->pipe, !usb_pipein(urb->pipe));
556 if((len) && usb_pipebulk(urb->pipe) &&
557 (urb->transfer_flags & URB_ZERO_PACKET) &&
558 (urb->actual_length == urb->transfer_buffer_length) &&
559 (!(urb->transfer_buffer_length % max_packet))) {
560 } else if (short_read || urb->actual_length == urb->transfer_buffer_length) {
561 xfer_done = 1;
562 if (short_read && (urb->transfer_flags & URB_SHORT_NOT_OK)) {
563 urb->status = -EREMOTEIO;
564 } else if (overflow_read) {
565 urb->status = -EOVERFLOW;
566 } else {
567 urb->status = 0;
568 }
569 }
570
571 #ifdef DEBUG
572 {
573 hctsiz_data_t hctsiz;
574 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
575 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
576 __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
577 DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", hc->xfer_len);
578 DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize);
579 DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
580 urb->transfer_buffer_length);
581 DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
582 DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n",
583 short_read, xfer_done);
584 }
585 #endif
586
587 return xfer_done;
588 }
589
590 /*
591 * Save the starting data toggle for the next transfer. The data toggle is
592 * saved in the QH for non-control transfers and it's saved in the QTD for
593 * control transfers.
594 */
595 static void save_data_toggle(dwc_hc_t *hc,
596 dwc_otg_hc_regs_t *hc_regs,
597 dwc_otg_qtd_t *qtd)
598 {
599 hctsiz_data_t hctsiz;
600 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
601
602 if (hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
603 dwc_otg_qh_t *qh = hc->qh;
604 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
605 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
606 } else {
607 qh->data_toggle = DWC_OTG_HC_PID_DATA1;
608 }
609 } else {
610 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
611 qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
612 } else {
613 qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
614 }
615 }
616 }
617
618 /**
619 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
620 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
621 * still linked to the QH, the QH is added to the end of the inactive
622 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
623 * schedule if no more QTDs are linked to the QH.
624 */
625 static void deactivate_qh(dwc_otg_hcd_t *hcd,
626 dwc_otg_qh_t *qh,
627 int free_qtd)
628 {
629 int continue_split = 0;
630 dwc_otg_qtd_t *qtd;
631
632 DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, hcd, qh, free_qtd);
633
634 qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
635
636 if (qtd->complete_split) {
637 continue_split = 1;
638 } else if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID ||
639 qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END) {
640 continue_split = 1;
641 }
642
643 if (free_qtd) {
644 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd);
645 continue_split = 0;
646 }
647
648 qh->channel = NULL;
649 qh->qtd_in_process = NULL;
650 dwc_otg_hcd_qh_deactivate(hcd, qh, continue_split);
651 }
652
653 /**
654 * Updates the state of an Isochronous URB when the transfer is stopped for
655 * any reason. The fields of the current entry in the frame descriptor array
656 * are set based on the transfer state and the input _halt_status. Completes
657 * the Isochronous URB if all the URB frames have been completed.
658 *
659 * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
660 * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
661 */
662 static dwc_otg_halt_status_e
663 update_isoc_urb_state(dwc_otg_hcd_t *hcd,
664 dwc_hc_t *hc,
665 dwc_otg_hc_regs_t *hc_regs,
666 dwc_otg_qtd_t *qtd,
667 dwc_otg_halt_status_e halt_status)
668 {
669 struct urb *urb = qtd->urb;
670 dwc_otg_halt_status_e ret_val = halt_status;
671 struct usb_iso_packet_descriptor *frame_desc;
672
673 frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
674 switch (halt_status) {
675 case DWC_OTG_HC_XFER_COMPLETE:
676 frame_desc->status = 0;
677 frame_desc->actual_length =
678 get_actual_xfer_length(hc, hc_regs, qtd,
679 halt_status, NULL);
680
681 /* non DWORD-aligned buffer case handling. */
682 if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) &&
683 hc->qh->dw_align_buf && hc->ep_is_in) {
684 memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset,
685 hc->qh->dw_align_buf, frame_desc->actual_length);
686
687 }
688
689 break;
690 case DWC_OTG_HC_XFER_FRAME_OVERRUN:
691 printk("DWC_OTG_HC_XFER_FRAME_OVERRUN: %d\n", halt_status);
692 urb->error_count++;
693 if (hc->ep_is_in) {
694 frame_desc->status = -ENOSR;
695 } else {
696 frame_desc->status = -ECOMM;
697 }
698 frame_desc->actual_length = 0;
699 break;
700 case DWC_OTG_HC_XFER_BABBLE_ERR:
701 printk("DWC_OTG_HC_XFER_BABBLE_ERR: %d\n", halt_status);
702 urb->error_count++;
703 frame_desc->status = -EOVERFLOW;
704 /* Don't need to update actual_length in this case. */
705 break;
706 case DWC_OTG_HC_XFER_XACT_ERR:
707 printk("DWC_OTG_HC_XFER_XACT_ERR: %d\n", halt_status);
708 urb->error_count++;
709 frame_desc->status = -EPROTO;
710 frame_desc->actual_length =
711 get_actual_xfer_length(hc, hc_regs, qtd,
712 halt_status, NULL);
713
714 /* non DWORD-aligned buffer case handling. */
715 if (frame_desc->actual_length && ((uint32_t)hc->xfer_buff & 0x3) &&
716 hc->qh->dw_align_buf && hc->ep_is_in) {
717 memcpy(urb->transfer_buffer + frame_desc->offset + qtd->isoc_split_offset,
718 hc->qh->dw_align_buf, frame_desc->actual_length);
719
720 }
721 break;
722 default:
723
724 DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
725 halt_status);
726 BUG();
727 break;
728 }
729
730 if (++qtd->isoc_frame_index == urb->number_of_packets) {
731 /*
732 * urb->status is not used for isoc transfers.
733 * The individual frame_desc statuses are used instead.
734 */
735 dwc_otg_hcd_complete_urb(hcd, urb, 0);
736 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
737 } else {
738 ret_val = DWC_OTG_HC_XFER_COMPLETE;
739 }
740
741 return ret_val;
742 }
743
744 /**
745 * Releases a host channel for use by other transfers. Attempts to select and
746 * queue more transactions since at least one host channel is available.
747 *
748 * @param hcd The HCD state structure.
749 * @param hc The host channel to release.
750 * @param qtd The QTD associated with the host channel. This QTD may be freed
751 * if the transfer is complete or an error has occurred.
752 * @param halt_status Reason the channel is being released. This status
753 * determines the actions taken by this function.
754 */
755 static void release_channel(dwc_otg_hcd_t *hcd,
756 dwc_hc_t *hc,
757 dwc_otg_qtd_t *qtd,
758 dwc_otg_halt_status_e halt_status)
759 {
760 dwc_otg_transaction_type_e tr_type;
761 int free_qtd;
762
763 DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n",
764 __func__, hc->hc_num, halt_status);
765
766 switch (halt_status) {
767 case DWC_OTG_HC_XFER_URB_COMPLETE:
768 free_qtd = 1;
769 break;
770 case DWC_OTG_HC_XFER_AHB_ERR:
771 case DWC_OTG_HC_XFER_STALL:
772 case DWC_OTG_HC_XFER_BABBLE_ERR:
773 free_qtd = 1;
774 break;
775 case DWC_OTG_HC_XFER_XACT_ERR:
776 if (qtd->error_count >= 3) {
777 DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n");
778 free_qtd = 1;
779 qtd->urb->status = -EPROTO;
780 dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EPROTO);
781 } else {
782 free_qtd = 0;
783 }
784 break;
785 case DWC_OTG_HC_XFER_URB_DEQUEUE:
786 /*
787 * The QTD has already been removed and the QH has been
788 * deactivated. Don't want to do anything except release the
789 * host channel and try to queue more transfers.
790 */
791 goto cleanup;
792 case DWC_OTG_HC_XFER_NO_HALT_STATUS:
793 DWC_ERROR("%s: No halt_status, channel %d\n", __func__, hc->hc_num);
794 free_qtd = 0;
795 break;
796 default:
797 free_qtd = 0;
798 break;
799 }
800
801 deactivate_qh(hcd, hc->qh, free_qtd);
802
803 cleanup:
804 /*
805 * Release the host channel for use by other transfers. The cleanup
806 * function clears the channel interrupt enables and conditions, so
807 * there's no need to clear the Channel Halted interrupt separately.
808 */
809 dwc_otg_hc_cleanup(hcd->core_if, hc);
810 list_add_tail(&hc->hc_list_entry, &hcd->free_hc_list);
811
812 switch (hc->ep_type) {
813 case DWC_OTG_EP_TYPE_CONTROL:
814 case DWC_OTG_EP_TYPE_BULK:
815 hcd->non_periodic_channels--;
816 break;
817
818 default:
819 /*
820 * Don't release reservations for periodic channels here.
821 * That's done when a periodic transfer is descheduled (i.e.
822 * when the QH is removed from the periodic schedule).
823 */
824 break;
825 }
826
827 /* Try to queue more transfers now that there's a free channel. */
828 tr_type = dwc_otg_hcd_select_transactions(hcd);
829 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
830 dwc_otg_hcd_queue_transactions(hcd, tr_type);
831 }
832 }
833
834 /**
835 * Halts a host channel. If the channel cannot be halted immediately because
836 * the request queue is full, this function ensures that the FIFO empty
837 * interrupt for the appropriate queue is enabled so that the halt request can
838 * be queued when there is space in the request queue.
839 *
840 * This function may also be called in DMA mode. In that case, the channel is
841 * simply released since the core always halts the channel automatically in
842 * DMA mode.
843 */
844 static void halt_channel(dwc_otg_hcd_t *hcd,
845 dwc_hc_t *hc,
846 dwc_otg_qtd_t *qtd,
847 dwc_otg_halt_status_e halt_status)
848 {
849 if (hcd->core_if->dma_enable) {
850 release_channel(hcd, hc, qtd, halt_status);
851 return;
852 }
853
854 /* Slave mode processing... */
855 dwc_otg_hc_halt(hcd->core_if, hc, halt_status);
856
857 if (hc->halt_on_queue) {
858 gintmsk_data_t gintmsk = {.d32 = 0};
859 dwc_otg_core_global_regs_t *global_regs;
860 global_regs = hcd->core_if->core_global_regs;
861
862 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
863 hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
864 /*
865 * Make sure the Non-periodic Tx FIFO empty interrupt
866 * is enabled so that the non-periodic schedule will
867 * be processed.
868 */
869 gintmsk.b.nptxfempty = 1;
870 dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
871 } else {
872 /*
873 * Move the QH from the periodic queued schedule to
874 * the periodic assigned schedule. This allows the
875 * halt to be queued when the periodic schedule is
876 * processed.
877 */
878 list_move(&hc->qh->qh_list_entry,
879 &hcd->periodic_sched_assigned);
880
881 /*
882 * Make sure the Periodic Tx FIFO Empty interrupt is
883 * enabled so that the periodic schedule will be
884 * processed.
885 */
886 gintmsk.b.ptxfempty = 1;
887 dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
888 }
889 }
890 }
891
892 /**
893 * Performs common cleanup for non-periodic transfers after a Transfer
894 * Complete interrupt. This function should be called after any endpoint type
895 * specific handling is finished to release the host channel.
896 */
897 static void complete_non_periodic_xfer(dwc_otg_hcd_t *hcd,
898 dwc_hc_t *hc,
899 dwc_otg_hc_regs_t *hc_regs,
900 dwc_otg_qtd_t *qtd,
901 dwc_otg_halt_status_e halt_status)
902 {
903 hcint_data_t hcint;
904
905 qtd->error_count = 0;
906
907 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
908 if (hcint.b.nyet) {
909 /*
910 * Got a NYET on the last transaction of the transfer. This
911 * means that the endpoint should be in the PING state at the
912 * beginning of the next transfer.
913 */
914 hc->qh->ping_state = 1;
915 clear_hc_int(hc_regs, nyet);
916 }
917
918 /*
919 * Always halt and release the host channel to make it available for
920 * more transfers. There may still be more phases for a control
921 * transfer or more data packets for a bulk transfer at this point,
922 * but the host channel is still halted. A channel will be reassigned
923 * to the transfer when the non-periodic schedule is processed after
924 * the channel is released. This allows transactions to be queued
925 * properly via dwc_otg_hcd_queue_transactions, which also enables the
926 * Tx FIFO Empty interrupt if necessary.
927 */
928 if (hc->ep_is_in) {
929 /*
930 * IN transfers in Slave mode require an explicit disable to
931 * halt the channel. (In DMA mode, this call simply releases
932 * the channel.)
933 */
934 halt_channel(hcd, hc, qtd, halt_status);
935 } else {
936 /*
937 * The channel is automatically disabled by the core for OUT
938 * transfers in Slave mode.
939 */
940 release_channel(hcd, hc, qtd, halt_status);
941 }
942 }
943
944 /**
945 * Performs common cleanup for periodic transfers after a Transfer Complete
946 * interrupt. This function should be called after any endpoint type specific
947 * handling is finished to release the host channel.
948 */
949 static void complete_periodic_xfer(dwc_otg_hcd_t *hcd,
950 dwc_hc_t *hc,
951 dwc_otg_hc_regs_t *hc_regs,
952 dwc_otg_qtd_t *qtd,
953 dwc_otg_halt_status_e halt_status)
954 {
955 hctsiz_data_t hctsiz;
956 qtd->error_count = 0;
957
958 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
959 if (!hc->ep_is_in || hctsiz.b.pktcnt == 0) {
960 /* Core halts channel in these cases. */
961 release_channel(hcd, hc, qtd, halt_status);
962 } else {
963 /* Flush any outstanding requests from the Tx queue. */
964 halt_channel(hcd, hc, qtd, halt_status);
965 }
966 }
967
968 /**
969 * Handles a host channel Transfer Complete interrupt. This handler may be
970 * called in either DMA mode or Slave mode.
971 */
972 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *hcd,
973 dwc_hc_t *hc,
974 dwc_otg_hc_regs_t *hc_regs,
975 dwc_otg_qtd_t *qtd)
976 {
977 int urb_xfer_done;
978 dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE;
979 struct urb *urb = qtd->urb;
980 int pipe_type = usb_pipetype(urb->pipe);
981
982 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
983 "Transfer Complete--\n", hc->hc_num);
984
985 /*
986 * Handle xfer complete on CSPLIT.
987 */
988 if (hc->qh->do_split) {
989 qtd->complete_split = 0;
990 }
991
992 /* Update the QTD and URB states. */
993 switch (pipe_type) {
994 case PIPE_CONTROL:
995 switch (qtd->control_phase) {
996 case DWC_OTG_CONTROL_SETUP:
997 if (urb->transfer_buffer_length > 0) {
998 qtd->control_phase = DWC_OTG_CONTROL_DATA;
999 } else {
1000 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1001 }
1002 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n");
1003 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1004 break;
1005 case DWC_OTG_CONTROL_DATA: {
1006 urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1007 if (urb_xfer_done) {
1008 qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1009 DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n");
1010 } else {
1011 save_data_toggle(hc, hc_regs, qtd);
1012 }
1013 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1014 break;
1015 }
1016 case DWC_OTG_CONTROL_STATUS:
1017 DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n");
1018 if (urb->status == -EINPROGRESS) {
1019 urb->status = 0;
1020 }
1021 dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
1022 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1023 break;
1024 }
1025
1026 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1027 break;
1028 case PIPE_BULK:
1029 DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n");
1030 urb_xfer_done = update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1031 if (urb_xfer_done) {
1032 dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
1033 halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1034 } else {
1035 halt_status = DWC_OTG_HC_XFER_COMPLETE;
1036 }
1037
1038 save_data_toggle(hc, hc_regs, qtd);
1039 complete_non_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1040 break;
1041 case PIPE_INTERRUPT:
1042 DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n");
1043 update_urb_state_xfer_comp(hc, hc_regs, urb, qtd);
1044
1045 /*
1046 * Interrupt URB is done on the first transfer complete
1047 * interrupt.
1048 */
1049 dwc_otg_hcd_complete_urb(hcd, urb, urb->status);
1050 save_data_toggle(hc, hc_regs, qtd);
1051 complete_periodic_xfer(hcd, hc, hc_regs, qtd,
1052 DWC_OTG_HC_XFER_URB_COMPLETE);
1053 break;
1054 case PIPE_ISOCHRONOUS:
1055 DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n");
1056 if (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1057 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1058 DWC_OTG_HC_XFER_COMPLETE);
1059 }
1060 complete_periodic_xfer(hcd, hc, hc_regs, qtd, halt_status);
1061 break;
1062 }
1063
1064 disable_hc_int(hc_regs, xfercompl);
1065
1066 return 1;
1067 }
1068
1069 /**
1070 * Handles a host channel STALL interrupt. This handler may be called in
1071 * either DMA mode or Slave mode.
1072 */
1073 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *hcd,
1074 dwc_hc_t *hc,
1075 dwc_otg_hc_regs_t *hc_regs,
1076 dwc_otg_qtd_t *qtd)
1077 {
1078 struct urb *urb = qtd->urb;
1079 int pipe_type = usb_pipetype(urb->pipe);
1080
1081 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1082 "STALL Received--\n", hc->hc_num);
1083
1084 if (pipe_type == PIPE_CONTROL) {
1085 dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
1086 }
1087
1088 if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
1089 dwc_otg_hcd_complete_urb(hcd, urb, -EPIPE);
1090 /*
1091 * USB protocol requires resetting the data toggle for bulk
1092 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1093 * setup command is issued to the endpoint. Anticipate the
1094 * CLEAR_FEATURE command since a STALL has occurred and reset
1095 * the data toggle now.
1096 */
1097 hc->qh->data_toggle = 0;
1098 }
1099
1100 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_STALL);
1101
1102 disable_hc_int(hc_regs, stall);
1103
1104 return 1;
1105 }
1106
1107 /*
1108 * Updates the state of the URB when a transfer has been stopped due to an
1109 * abnormal condition before the transfer completes. Modifies the
1110 * actual_length field of the URB to reflect the number of bytes that have
1111 * actually been transferred via the host channel.
1112 */
1113 static void update_urb_state_xfer_intr(dwc_hc_t *hc,
1114 dwc_otg_hc_regs_t *hc_regs,
1115 struct urb *urb,
1116 dwc_otg_qtd_t *qtd,
1117 dwc_otg_halt_status_e halt_status)
1118 {
1119 uint32_t bytes_transferred = get_actual_xfer_length(hc, hc_regs, qtd,
1120 halt_status, NULL);
1121 urb->actual_length += bytes_transferred;
1122
1123 #ifdef DEBUG
1124 {
1125 hctsiz_data_t hctsiz;
1126 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1127 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1128 __func__, (hc->ep_is_in ? "IN" : "OUT"), hc->hc_num);
1129 DWC_DEBUGPL(DBG_HCDV, " hc->start_pkt_count %d\n", hc->start_pkt_count);
1130 DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1131 DWC_DEBUGPL(DBG_HCDV, " hc->max_packet %d\n", hc->max_packet);
1132 DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred);
1133 DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", urb->actual_length);
1134 DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n",
1135 urb->transfer_buffer_length);
1136 }
1137 #endif
1138 }
1139
1140 /**
1141 * Handles a host channel NAK interrupt. This handler may be called in either
1142 * DMA mode or Slave mode.
1143 */
1144 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *hcd,
1145 dwc_hc_t *hc,
1146 dwc_otg_hc_regs_t *hc_regs,
1147 dwc_otg_qtd_t *qtd)
1148 {
1149 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1150 "NAK Received--\n", hc->hc_num);
1151
1152 /*
1153 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1154 * interrupt. Re-start the SSPLIT transfer.
1155 */
1156 if (hc->do_split) {
1157 if (hc->complete_split) {
1158 qtd->error_count = 0;
1159 }
1160 qtd->complete_split = 0;
1161 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1162 goto handle_nak_done;
1163 }
1164
1165 switch (usb_pipetype(qtd->urb->pipe)) {
1166 case PIPE_CONTROL:
1167 case PIPE_BULK:
1168 if (hcd->core_if->dma_enable && hc->ep_is_in) {
1169 /*
1170 * NAK interrupts are enabled on bulk/control IN
1171 * transfers in DMA mode for the sole purpose of
1172 * resetting the error count after a transaction error
1173 * occurs. The core will continue transferring data.
1174 */
1175 qtd->error_count = 0;
1176 goto handle_nak_done;
1177 }
1178
1179 /*
1180 * NAK interrupts normally occur during OUT transfers in DMA
1181 * or Slave mode. For IN transfers, more requests will be
1182 * queued as request queue space is available.
1183 */
1184 qtd->error_count = 0;
1185
1186 if (!hc->qh->ping_state) {
1187 update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
1188 qtd, DWC_OTG_HC_XFER_NAK);
1189 save_data_toggle(hc, hc_regs, qtd);
1190 if (qtd->urb->dev->speed == USB_SPEED_HIGH) {
1191 hc->qh->ping_state = 1;
1192 }
1193 }
1194
1195 /*
1196 * Halt the channel so the transfer can be re-started from
1197 * the appropriate point or the PING protocol will
1198 * start/continue.
1199 */
1200 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1201 break;
1202 case PIPE_INTERRUPT:
1203 qtd->error_count = 0;
1204 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NAK);
1205 break;
1206 case PIPE_ISOCHRONOUS:
1207 /* Should never get called for isochronous transfers. */
1208 BUG();
1209 break;
1210 }
1211
1212 handle_nak_done:
1213 disable_hc_int(hc_regs, nak);
1214
1215 return 1;
1216 }
1217
1218 /**
1219 * Handles a host channel ACK interrupt. This interrupt is enabled when
1220 * performing the PING protocol in Slave mode, when errors occur during
1221 * either Slave mode or DMA mode, and during Start Split transactions.
1222 */
1223 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *hcd,
1224 dwc_hc_t *hc,
1225 dwc_otg_hc_regs_t *hc_regs,
1226 dwc_otg_qtd_t *qtd)
1227 {
1228 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1229 "ACK Received--\n", hc->hc_num);
1230
1231 if (hc->do_split) {
1232 /*
1233 * Handle ACK on SSPLIT.
1234 * ACK should not occur in CSPLIT.
1235 */
1236 if (!hc->ep_is_in && hc->data_pid_start != DWC_OTG_HC_PID_SETUP) {
1237 qtd->ssplit_out_xfer_count = hc->xfer_len;
1238 }
1239 if (!(hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in)) {
1240 /* Don't need complete for isochronous out transfers. */
1241 qtd->complete_split = 1;
1242 }
1243
1244 /* ISOC OUT */
1245 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1246 switch (hc->xact_pos) {
1247 case DWC_HCSPLIT_XACTPOS_ALL:
1248 break;
1249 case DWC_HCSPLIT_XACTPOS_END:
1250 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1251 qtd->isoc_split_offset = 0;
1252 break;
1253 case DWC_HCSPLIT_XACTPOS_BEGIN:
1254 case DWC_HCSPLIT_XACTPOS_MID:
1255 /*
1256 * For BEGIN or MID, calculate the length for
1257 * the next microframe to determine the correct
1258 * SSPLIT token, either MID or END.
1259 */
1260 {
1261 struct usb_iso_packet_descriptor *frame_desc;
1262
1263 frame_desc = &qtd->urb->iso_frame_desc[qtd->isoc_frame_index];
1264 qtd->isoc_split_offset += 188;
1265
1266 if ((frame_desc->length - qtd->isoc_split_offset) <= 188) {
1267 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
1268 } else {
1269 qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
1270 }
1271
1272 }
1273 break;
1274 }
1275 } else {
1276 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1277 }
1278 } else {
1279 qtd->error_count = 0;
1280
1281 if (hc->qh->ping_state) {
1282 hc->qh->ping_state = 0;
1283 /*
1284 * Halt the channel so the transfer can be re-started
1285 * from the appropriate point. This only happens in
1286 * Slave mode. In DMA mode, the ping_state is cleared
1287 * when the transfer is started because the core
1288 * automatically executes the PING, then the transfer.
1289 */
1290 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_ACK);
1291 }
1292 }
1293
1294 /*
1295 * If the ACK occurred when _not_ in the PING state, let the channel
1296 * continue transferring data after clearing the error count.
1297 */
1298
1299 disable_hc_int(hc_regs, ack);
1300
1301 return 1;
1302 }
1303
1304 /**
1305 * Handles a host channel NYET interrupt. This interrupt should only occur on
1306 * Bulk and Control OUT endpoints and for complete split transactions. If a
1307 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1308 * handled in the xfercomp interrupt handler, not here. This handler may be
1309 * called in either DMA mode or Slave mode.
1310 */
1311 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *hcd,
1312 dwc_hc_t *hc,
1313 dwc_otg_hc_regs_t *hc_regs,
1314 dwc_otg_qtd_t *qtd)
1315 {
1316 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1317 "NYET Received--\n", hc->hc_num);
1318
1319 /*
1320 * NYET on CSPLIT
1321 * re-do the CSPLIT immediately on non-periodic
1322 */
1323 if (hc->do_split && hc->complete_split) {
1324 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1325 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1326 int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd));
1327
1328 if (dwc_full_frame_num(frnum) !=
1329 dwc_full_frame_num(hc->qh->sched_frame)) {
1330 /*
1331 * No longer in the same full speed frame.
1332 * Treat this as a transaction error.
1333 */
1334 #if 0
1335 /** @todo Fix system performance so this can
1336 * be treated as an error. Right now complete
1337 * splits cannot be scheduled precisely enough
1338 * due to other system activity, so this error
1339 * occurs regularly in Slave mode.
1340 */
1341 qtd->error_count++;
1342 #endif
1343 qtd->complete_split = 0;
1344 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1345 /** @todo add support for isoc release */
1346 goto handle_nyet_done;
1347 }
1348 }
1349
1350 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1351 goto handle_nyet_done;
1352 }
1353
1354 hc->qh->ping_state = 1;
1355 qtd->error_count = 0;
1356
1357 update_urb_state_xfer_intr(hc, hc_regs, qtd->urb, qtd,
1358 DWC_OTG_HC_XFER_NYET);
1359 save_data_toggle(hc, hc_regs, qtd);
1360
1361 /*
1362 * Halt the channel and re-start the transfer so the PING
1363 * protocol will start.
1364 */
1365 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_NYET);
1366
1367 handle_nyet_done:
1368 disable_hc_int(hc_regs, nyet);
1369 return 1;
1370 }
1371
1372 /**
1373 * Handles a host channel babble interrupt. This handler may be called in
1374 * either DMA mode or Slave mode.
1375 */
1376 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *hcd,
1377 dwc_hc_t *hc,
1378 dwc_otg_hc_regs_t *hc_regs,
1379 dwc_otg_qtd_t *qtd)
1380 {
1381 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1382 "Babble Error--\n", hc->hc_num);
1383 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1384 dwc_otg_hcd_complete_urb(hcd, qtd->urb, -EOVERFLOW);
1385 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1386 } else {
1387 dwc_otg_halt_status_e halt_status;
1388 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1389 DWC_OTG_HC_XFER_BABBLE_ERR);
1390 halt_channel(hcd, hc, qtd, halt_status);
1391 }
1392 disable_hc_int(hc_regs, bblerr);
1393 return 1;
1394 }
1395
1396 /**
1397 * Handles a host channel AHB error interrupt. This handler is only called in
1398 * DMA mode.
1399 */
1400 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *hcd,
1401 dwc_hc_t *hc,
1402 dwc_otg_hc_regs_t *hc_regs,
1403 dwc_otg_qtd_t *qtd)
1404 {
1405 hcchar_data_t hcchar;
1406 hcsplt_data_t hcsplt;
1407 hctsiz_data_t hctsiz;
1408 uint32_t hcdma;
1409 struct urb *urb = qtd->urb;
1410
1411 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1412 "AHB Error--\n", hc->hc_num);
1413
1414 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1415 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1416 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1417 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1418
1419 DWC_ERROR("AHB ERROR, Channel %d\n", hc->hc_num);
1420 DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1421 DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1422 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1423 DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe));
1424 DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
1425 (usb_pipein(urb->pipe) ? "IN" : "OUT"));
1426 DWC_ERROR(" Endpoint type: %s\n",
1427 ({char *pipetype;
1428 switch (usb_pipetype(urb->pipe)) {
1429 case PIPE_CONTROL: pipetype = "CONTROL"; break;
1430 case PIPE_BULK: pipetype = "BULK"; break;
1431 case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1432 case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1433 default: pipetype = "UNKNOWN"; break;
1434 }; pipetype;}));
1435 DWC_ERROR(" Speed: %s\n",
1436 ({char *speed;
1437 switch (urb->dev->speed) {
1438 case USB_SPEED_HIGH: speed = "HIGH"; break;
1439 case USB_SPEED_FULL: speed = "FULL"; break;
1440 case USB_SPEED_LOW: speed = "LOW"; break;
1441 default: speed = "UNKNOWN"; break;
1442 }; speed;}));
1443 DWC_ERROR(" Max packet size: %d\n",
1444 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
1445 DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length);
1446 DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
1447 urb->transfer_buffer, (void *)urb->transfer_dma);
1448 DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
1449 urb->setup_packet, (void *)urb->setup_dma);
1450 DWC_ERROR(" Interval: %d\n", urb->interval);
1451
1452 dwc_otg_hcd_complete_urb(hcd, urb, -EIO);
1453
1454 /*
1455 * Force a channel halt. Don't call halt_channel because that won't
1456 * write to the HCCHARn register in DMA mode to force the halt.
1457 */
1458 dwc_otg_hc_halt(hcd->core_if, hc, DWC_OTG_HC_XFER_AHB_ERR);
1459
1460 disable_hc_int(hc_regs, ahberr);
1461 return 1;
1462 }
1463
1464 /**
1465 * Handles a host channel transaction error interrupt. This handler may be
1466 * called in either DMA mode or Slave mode.
1467 */
1468 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *hcd,
1469 dwc_hc_t *hc,
1470 dwc_otg_hc_regs_t *hc_regs,
1471 dwc_otg_qtd_t *qtd)
1472 {
1473 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1474 "Transaction Error--\n", hc->hc_num);
1475
1476 switch (usb_pipetype(qtd->urb->pipe)) {
1477 case PIPE_CONTROL:
1478 case PIPE_BULK:
1479 qtd->error_count++;
1480 if (!hc->qh->ping_state) {
1481 update_urb_state_xfer_intr(hc, hc_regs, qtd->urb,
1482 qtd, DWC_OTG_HC_XFER_XACT_ERR);
1483 save_data_toggle(hc, hc_regs, qtd);
1484 if (!hc->ep_is_in && qtd->urb->dev->speed == USB_SPEED_HIGH) {
1485 hc->qh->ping_state = 1;
1486 }
1487 }
1488
1489 /*
1490 * Halt the channel so the transfer can be re-started from
1491 * the appropriate point or the PING protocol will start.
1492 */
1493 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1494 break;
1495 case PIPE_INTERRUPT:
1496 qtd->error_count++;
1497 if (hc->do_split && hc->complete_split) {
1498 qtd->complete_split = 0;
1499 }
1500 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_XACT_ERR);
1501 break;
1502 case PIPE_ISOCHRONOUS:
1503 {
1504 dwc_otg_halt_status_e halt_status;
1505 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1506 DWC_OTG_HC_XFER_XACT_ERR);
1507
1508 halt_channel(hcd, hc, qtd, halt_status);
1509 }
1510 break;
1511 }
1512
1513 disable_hc_int(hc_regs, xacterr);
1514
1515 return 1;
1516 }
1517
1518 /**
1519 * Handles a host channel frame overrun interrupt. This handler may be called
1520 * in either DMA mode or Slave mode.
1521 */
1522 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *hcd,
1523 dwc_hc_t *hc,
1524 dwc_otg_hc_regs_t *hc_regs,
1525 dwc_otg_qtd_t *qtd)
1526 {
1527 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1528 "Frame Overrun--\n", hc->hc_num);
1529
1530 switch (usb_pipetype(qtd->urb->pipe)) {
1531 case PIPE_CONTROL:
1532 case PIPE_BULK:
1533 break;
1534 case PIPE_INTERRUPT:
1535 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1536 break;
1537 case PIPE_ISOCHRONOUS:
1538 {
1539 dwc_otg_halt_status_e halt_status;
1540 halt_status = update_isoc_urb_state(hcd, hc, hc_regs, qtd,
1541 DWC_OTG_HC_XFER_FRAME_OVERRUN);
1542
1543 halt_channel(hcd, hc, qtd, halt_status);
1544 }
1545 break;
1546 }
1547
1548 disable_hc_int(hc_regs, frmovrun);
1549
1550 return 1;
1551 }
1552
1553 /**
1554 * Handles a host channel data toggle error interrupt. This handler may be
1555 * called in either DMA mode or Slave mode.
1556 */
1557 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *hcd,
1558 dwc_hc_t *hc,
1559 dwc_otg_hc_regs_t *hc_regs,
1560 dwc_otg_qtd_t *qtd)
1561 {
1562 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1563 "Data Toggle Error--\n", hc->hc_num);
1564
1565 if (hc->ep_is_in) {
1566 qtd->error_count = 0;
1567 } else {
1568 DWC_ERROR("Data Toggle Error on OUT transfer,"
1569 "channel %d\n", hc->hc_num);
1570 }
1571
1572 disable_hc_int(hc_regs, datatglerr);
1573
1574 return 1;
1575 }
1576
1577 #ifdef DEBUG
1578 /**
1579 * This function is for debug only. It checks that a valid halt status is set
1580 * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1581 * taken and a warning is issued.
1582 * @return 1 if halt status is ok, 0 otherwise.
1583 */
1584 static inline int halt_status_ok(dwc_otg_hcd_t *hcd,
1585 dwc_hc_t *hc,
1586 dwc_otg_hc_regs_t *hc_regs,
1587 dwc_otg_qtd_t *qtd)
1588 {
1589 hcchar_data_t hcchar;
1590 hctsiz_data_t hctsiz;
1591 hcint_data_t hcint;
1592 hcintmsk_data_t hcintmsk;
1593 hcsplt_data_t hcsplt;
1594
1595 if (hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1596 /*
1597 * This code is here only as a check. This condition should
1598 * never happen. Ignore the halt if it does occur.
1599 */
1600 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1601 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1602 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1603 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1604 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1605 DWC_WARN("%s: hc->halt_status == DWC_OTG"
1606 "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1607 "hcint 0x%08x, hcintmsk 0x%08x, "
1608 "hcsplt 0x%08x, qtd->complete_split %d\n",
1609 __func__, hc->hc_num, hcchar.d32, hctsiz.d32,
1610 hcint.d32, hcintmsk.d32,
1611 hcsplt.d32, qtd->complete_split);
1612
1613 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1614 __func__, hc->hc_num);
1615 DWC_WARN("\n");
1616 clear_hc_int(hc_regs, chhltd);
1617 return 0;
1618 }
1619
1620 /*
1621 * This code is here only as a check. hcchar.chdis should
1622 * never be set when the halt interrupt occurs. Halt the
1623 * channel again if it does occur.
1624 */
1625 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1626 if (hcchar.b.chdis) {
1627 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1628 "hcchar 0x%08x, trying to halt again\n",
1629 __func__, hcchar.d32);
1630 clear_hc_int(hc_regs, chhltd);
1631 hc->halt_pending = 0;
1632 halt_channel(hcd, hc, qtd, hc->halt_status);
1633 return 0;
1634 }
1635
1636 return 1;
1637 }
1638 #endif
1639
1640 /**
1641 * Handles a host Channel Halted interrupt in DMA mode. This handler
1642 * determines the reason the channel halted and proceeds accordingly.
1643 */
1644 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *hcd,
1645 dwc_hc_t *hc,
1646 dwc_otg_hc_regs_t *hc_regs,
1647 dwc_otg_qtd_t *qtd)
1648 {
1649 hcint_data_t hcint;
1650 hcintmsk_data_t hcintmsk;
1651 int out_nak_enh = 0;
1652
1653 /* For core with OUT NAK enhancement, the flow for high-
1654 * speed CONTROL/BULK OUT is handled a little differently.
1655 */
1656 if (hcd->core_if->snpsid >= 0x4F54271A) {
1657 if (hc->speed == DWC_OTG_EP_SPEED_HIGH && !hc->ep_is_in &&
1658 (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
1659 hc->ep_type == DWC_OTG_EP_TYPE_BULK)) {
1660 printk(KERN_DEBUG "OUT NAK enhancement enabled\n");
1661 out_nak_enh = 1;
1662 } else {
1663 printk(KERN_DEBUG "OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
1664 }
1665 } else {
1666 // printk(KERN_DEBUG "OUT NAK enhancement disabled, no core support\n");
1667 }
1668
1669 if (hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1670 hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1671 /*
1672 * Just release the channel. A dequeue can happen on a
1673 * transfer timeout. In the case of an AHB Error, the channel
1674 * was forced to halt because there's no way to gracefully
1675 * recover.
1676 */
1677 release_channel(hcd, hc, qtd, hc->halt_status);
1678 return;
1679 }
1680
1681 /* Read the HCINTn register to determine the cause for the halt. */
1682 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1683 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1684
1685 if (hcint.b.xfercomp) {
1686 /** @todo This is here because of a possible hardware bug. Spec
1687 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1688 * interrupt w/ACK bit set should occur, but I only see the
1689 * XFERCOMP bit, even with it masked out. This is a workaround
1690 * for that behavior. Should fix this when hardware is fixed.
1691 */
1692 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !hc->ep_is_in) {
1693 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1694 }
1695 handle_hc_xfercomp_intr(hcd, hc, hc_regs, qtd);
1696 } else if (hcint.b.stall) {
1697 handle_hc_stall_intr(hcd, hc, hc_regs, qtd);
1698 } else if (hcint.b.xacterr) {
1699 if (out_nak_enh) {
1700 if (hcint.b.nyet || hcint.b.nak || hcint.b.ack) {
1701 printk(KERN_DEBUG "XactErr with NYET/NAK/ACK\n");
1702 qtd->error_count = 0;
1703 } else {
1704 printk(KERN_DEBUG "XactErr without NYET/NAK/ACK\n");
1705 }
1706 }
1707
1708 /*
1709 * Must handle xacterr before nak or ack. Could get a xacterr
1710 * at the same time as either of these on a BULK/CONTROL OUT
1711 * that started with a PING. The xacterr takes precedence.
1712 */
1713 handle_hc_xacterr_intr(hcd, hc, hc_regs, qtd);
1714 } else if (!out_nak_enh) {
1715 if (hcint.b.nyet) {
1716 /*
1717 * Must handle nyet before nak or ack. Could get a nyet at the
1718 * same time as either of those on a BULK/CONTROL OUT that
1719 * started with a PING. The nyet takes precedence.
1720 */
1721 handle_hc_nyet_intr(hcd, hc, hc_regs, qtd);
1722 } else if (hcint.b.bblerr) {
1723 handle_hc_babble_intr(hcd, hc, hc_regs, qtd);
1724 } else if (hcint.b.frmovrun) {
1725 handle_hc_frmovrun_intr(hcd, hc, hc_regs, qtd);
1726 } else if (hcint.b.nak && !hcintmsk.b.nak) {
1727 /*
1728 * If nak is not masked, it's because a non-split IN transfer
1729 * is in an error state. In that case, the nak is handled by
1730 * the nak interrupt handler, not here. Handle nak here for
1731 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1732 * rewinding the buffer pointer.
1733 */
1734 handle_hc_nak_intr(hcd, hc, hc_regs, qtd);
1735 } else if (hcint.b.ack && !hcintmsk.b.ack) {
1736 /*
1737 * If ack is not masked, it's because a non-split IN transfer
1738 * is in an error state. In that case, the ack is handled by
1739 * the ack interrupt handler, not here. Handle ack here for
1740 * split transfers. Start splits halt on ACK.
1741 */
1742 handle_hc_ack_intr(hcd, hc, hc_regs, qtd);
1743 } else {
1744 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1745 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1746 /*
1747 * A periodic transfer halted with no other channel
1748 * interrupts set. Assume it was halted by the core
1749 * because it could not be completed in its scheduled
1750 * (micro)frame.
1751 */
1752 #ifdef DEBUG
1753 DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1754 __func__, hc->hc_num);
1755 #endif
1756 halt_channel(hcd, hc, qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
1757 } else {
1758 DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1759 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1760 __func__, hc->hc_num, hcint.d32,
1761 dwc_read_reg32(&hcd->core_if->core_global_regs->gintsts));
1762 }
1763 }
1764 } else {
1765 printk(KERN_DEBUG "NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint.d32);
1766 }
1767 }
1768
1769 /**
1770 * Handles a host channel Channel Halted interrupt.
1771 *
1772 * In slave mode, this handler is called only when the driver specifically
1773 * requests a halt. This occurs during handling other host channel interrupts
1774 * (e.g. nak, xacterr, stall, nyet, etc.).
1775 *
1776 * In DMA mode, this is the interrupt that occurs when the core has finished
1777 * processing a transfer on a channel. Other host channel interrupts (except
1778 * ahberr) are disabled in DMA mode.
1779 */
1780 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *hcd,
1781 dwc_hc_t *hc,
1782 dwc_otg_hc_regs_t *hc_regs,
1783 dwc_otg_qtd_t *qtd)
1784 {
1785 DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1786 "Channel Halted--\n", hc->hc_num);
1787
1788 if (hcd->core_if->dma_enable) {
1789 handle_hc_chhltd_intr_dma(hcd, hc, hc_regs, qtd);
1790 } else {
1791 #ifdef DEBUG
1792 if (!halt_status_ok(hcd, hc, hc_regs, qtd)) {
1793 return 1;
1794 }
1795 #endif
1796 release_channel(hcd, hc, qtd, hc->halt_status);
1797 }
1798
1799 return 1;
1800 }
1801
1802 /** Handles interrupt for a specific Host Channel */
1803 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t *dwc_otg_hcd, uint32_t num)
1804 {
1805 int retval = 0;
1806 hcint_data_t hcint;
1807 hcintmsk_data_t hcintmsk;
1808 dwc_hc_t *hc;
1809 dwc_otg_hc_regs_t *hc_regs;
1810 dwc_otg_qtd_t *qtd;
1811
1812 DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", num);
1813
1814 hc = dwc_otg_hcd->hc_ptr_array[num];
1815 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[num];
1816 qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
1817
1818 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1819 hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1820 DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1821 hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
1822 hcint.d32 = hcint.d32 & hcintmsk.d32;
1823
1824 if (!dwc_otg_hcd->core_if->dma_enable) {
1825 if (hcint.b.chhltd && hcint.d32 != 0x2) {
1826 hcint.b.chhltd = 0;
1827 }
1828 }
1829
1830 if (hcint.b.xfercomp) {
1831 retval |= handle_hc_xfercomp_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1832 /*
1833 * If NYET occurred at same time as Xfer Complete, the NYET is
1834 * handled by the Xfer Complete interrupt handler. Don't want
1835 * to call the NYET interrupt handler in this case.
1836 */
1837 hcint.b.nyet = 0;
1838 }
1839 if (hcint.b.chhltd) {
1840 retval |= handle_hc_chhltd_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1841 }
1842 if (hcint.b.ahberr) {
1843 retval |= handle_hc_ahberr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1844 }
1845 if (hcint.b.stall) {
1846 retval |= handle_hc_stall_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1847 }
1848 if (hcint.b.nak) {
1849 retval |= handle_hc_nak_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1850 }
1851 if (hcint.b.ack) {
1852 retval |= handle_hc_ack_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1853 }
1854 if (hcint.b.nyet) {
1855 retval |= handle_hc_nyet_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1856 }
1857 if (hcint.b.xacterr) {
1858 retval |= handle_hc_xacterr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1859 }
1860 if (hcint.b.bblerr) {
1861 retval |= handle_hc_babble_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1862 }
1863 if (hcint.b.frmovrun) {
1864 retval |= handle_hc_frmovrun_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1865 }
1866 if (hcint.b.datatglerr) {
1867 retval |= handle_hc_datatglerr_intr(dwc_otg_hcd, hc, hc_regs, qtd);
1868 }
1869
1870 return retval;
1871 }
1872
1873 #endif /* DWC_DEVICE_ONLY */
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