1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd_intr.c $
4 * $Date: 2009-04-22 03:48:22 $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
35 #include <linux/version.h>
37 #include "dwc_otg_driver.h"
38 #include "dwc_otg_hcd.h"
39 #include "dwc_otg_regs.h"
42 * This file contains the implementation of the HCD Interrupt handlers.
45 /** This function handles interrupts for the HCD. */
46 int32_t dwc_otg_hcd_handle_intr(dwc_otg_hcd_t
*dwc_otg_hcd
)
50 dwc_otg_core_if_t
*core_if
= dwc_otg_hcd
->core_if
;
51 gintsts_data_t gintsts
;
53 dwc_otg_core_global_regs_t
*global_regs
= core_if
->core_global_regs
;
56 /* Check if HOST Mode */
57 if (dwc_otg_is_host_mode(core_if
)) {
58 gintsts
.d32
= dwc_otg_read_core_intr(core_if
);
64 /* Don't print debug message in the interrupt handler on SOF */
66 if (gintsts
.d32
!= DWC_SOF_INTR_MASK
)
68 DWC_DEBUGPL(DBG_HCD
, "\n");
73 if (gintsts
.d32
!= DWC_SOF_INTR_MASK
)
75 DWC_DEBUGPL(DBG_HCD
, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts
.d32
);
77 if (gintsts
.b
.usbreset
) {
78 DWC_PRINT("Usb Reset In Host Mode\n");
82 if (gintsts
.b
.sofintr
) {
83 retval
|= dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd
);
85 if (gintsts
.b
.rxstsqlvl
) {
86 retval
|= dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd
);
88 if (gintsts
.b
.nptxfempty
) {
89 retval
|= dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd
);
91 if (gintsts
.b
.i2cintr
) {
92 /** @todo Implement i2cintr handler. */
94 if (gintsts
.b
.portintr
) {
95 retval
|= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd
);
97 if (gintsts
.b
.hcintr
) {
98 retval
|= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd
);
100 if (gintsts
.b
.ptxfempty
) {
101 retval
|= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd
);
105 if (gintsts
.d32
!= DWC_SOF_INTR_MASK
)
108 DWC_DEBUGPL(DBG_HCD
, "DWC OTG HCD Finished Servicing Interrupts\n");
109 DWC_DEBUGPL(DBG_HCDV
, "DWC OTG HCD gintsts=0x%08x\n",
110 dwc_read_reg32(&global_regs
->gintsts
));
111 DWC_DEBUGPL(DBG_HCDV
, "DWC OTG HCD gintmsk=0x%08x\n",
112 dwc_read_reg32(&global_regs
->gintmsk
));
118 if (gintsts
.d32
!= DWC_SOF_INTR_MASK
)
120 DWC_DEBUGPL(DBG_HCD
, "\n");
125 S3C2410X_CLEAR_EINTPEND();
130 #ifdef DWC_TRACK_MISSED_SOFS
131 #warning Compiling code to track missed SOFs
132 #define FRAME_NUM_ARRAY_SIZE 1000
134 * This function is for debug only.
136 static inline void track_missed_sofs(uint16_t curr_frame_number
)
138 static uint16_t frame_num_array
[FRAME_NUM_ARRAY_SIZE
];
139 static uint16_t last_frame_num_array
[FRAME_NUM_ARRAY_SIZE
];
140 static int frame_num_idx
= 0;
141 static uint16_t last_frame_num
= DWC_HFNUM_MAX_FRNUM
;
142 static int dumped_frame_num_array
= 0;
144 if (frame_num_idx
< FRAME_NUM_ARRAY_SIZE
) {
145 if (((last_frame_num
+ 1) & DWC_HFNUM_MAX_FRNUM
) != curr_frame_number
) {
146 frame_num_array
[frame_num_idx
] = curr_frame_number
;
147 last_frame_num_array
[frame_num_idx
++] = last_frame_num
;
149 } else if (!dumped_frame_num_array
) {
151 printk(KERN_EMERG USB_DWC
"Frame Last Frame\n");
152 printk(KERN_EMERG USB_DWC
"----- ----------\n");
153 for (i
= 0; i
< FRAME_NUM_ARRAY_SIZE
; i
++) {
154 printk(KERN_EMERG USB_DWC
"0x%04x 0x%04x\n",
155 frame_num_array
[i
], last_frame_num_array
[i
]);
157 dumped_frame_num_array
= 1;
159 last_frame_num
= curr_frame_number
;
164 * Handles the start-of-frame interrupt in host mode. Non-periodic
165 * transactions may be queued to the DWC_otg controller for the current
166 * (micro)frame. Periodic transactions may be queued to the controller for the
169 int32_t dwc_otg_hcd_handle_sof_intr(dwc_otg_hcd_t
*hcd
)
172 struct list_head
*qh_entry
;
174 dwc_otg_transaction_type_e tr_type
;
175 gintsts_data_t gintsts
= {.d32
= 0};
177 hfnum
.d32
= dwc_read_reg32(&hcd
->core_if
->host_if
->host_global_regs
->hfnum
);
180 DWC_DEBUGPL(DBG_HCD
, "--Start of Frame Interrupt--\n");
182 hcd
->frame_number
= hfnum
.b
.frnum
;
185 hcd
->frrem_accum
+= hfnum
.b
.frrem
;
186 hcd
->frrem_samples
++;
189 #ifdef DWC_TRACK_MISSED_SOFS
190 track_missed_sofs(hcd
->frame_number
);
193 /* Determine whether any periodic QHs should be executed. */
194 qh_entry
= hcd
->periodic_sched_inactive
.next
;
195 while (qh_entry
!= &hcd
->periodic_sched_inactive
) {
196 qh
= list_entry(qh_entry
, dwc_otg_qh_t
, qh_list_entry
);
197 qh_entry
= qh_entry
->next
;
198 if (dwc_frame_num_le(qh
->sched_frame
, hcd
->frame_number
)) {
200 * Move QH to the ready list to be executed next
203 list_move(&qh
->qh_list_entry
, &hcd
->periodic_sched_ready
);
207 tr_type
= dwc_otg_hcd_select_transactions(hcd
);
208 if (tr_type
!= DWC_OTG_TRANSACTION_NONE
) {
209 dwc_otg_hcd_queue_transactions(hcd
, tr_type
);
212 /* Clear interrupt */
213 gintsts
.b
.sofintr
= 1;
214 dwc_write_reg32(&hcd
->core_if
->core_global_regs
->gintsts
, gintsts
.d32
);
219 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
220 * least one packet in the Rx FIFO. The packets are moved from the FIFO to
221 * memory if the DWC_otg controller is operating in Slave mode. */
222 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr(dwc_otg_hcd_t
*dwc_otg_hcd
)
224 host_grxsts_data_t grxsts
;
227 DWC_DEBUGPL(DBG_HCD
, "--RxStsQ Level Interrupt--\n");
229 grxsts
.d32
= dwc_read_reg32(&dwc_otg_hcd
->core_if
->core_global_regs
->grxstsp
);
231 hc
= dwc_otg_hcd
->hc_ptr_array
[grxsts
.b
.chnum
];
234 DWC_DEBUGPL(DBG_HCDV
, " Ch num = %d\n", grxsts
.b
.chnum
);
235 DWC_DEBUGPL(DBG_HCDV
, " Count = %d\n", grxsts
.b
.bcnt
);
236 DWC_DEBUGPL(DBG_HCDV
, " DPID = %d, hc.dpid = %d\n", grxsts
.b
.dpid
, hc
->data_pid_start
);
237 DWC_DEBUGPL(DBG_HCDV
, " PStatus = %d\n", grxsts
.b
.pktsts
);
239 switch (grxsts
.b
.pktsts
) {
240 case DWC_GRXSTS_PKTSTS_IN
:
241 /* Read the data into the host buffer. */
242 if (grxsts
.b
.bcnt
> 0) {
243 dwc_otg_read_packet(dwc_otg_hcd
->core_if
,
247 /* Update the HC fields for the next packet received. */
248 hc
->xfer_count
+= grxsts
.b
.bcnt
;
249 hc
->xfer_buff
+= grxsts
.b
.bcnt
;
252 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP
:
253 case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR
:
254 case DWC_GRXSTS_PKTSTS_CH_HALTED
:
255 /* Handled in interrupt, just ignore data */
258 DWC_ERROR("RX_STS_Q Interrupt: Unknown status %d\n", grxsts
.b
.pktsts
);
265 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
266 * data packets may be written to the FIFO for OUT transfers. More requests
267 * may be written to the non-periodic request queue for IN transfers. This
268 * interrupt is enabled only in Slave mode. */
269 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr(dwc_otg_hcd_t
*dwc_otg_hcd
)
271 DWC_DEBUGPL(DBG_HCD
, "--Non-Periodic TxFIFO Empty Interrupt--\n");
272 dwc_otg_hcd_queue_transactions(dwc_otg_hcd
,
273 DWC_OTG_TRANSACTION_NON_PERIODIC
);
277 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
278 * packets may be written to the FIFO for OUT transfers. More requests may be
279 * written to the periodic request queue for IN transfers. This interrupt is
280 * enabled only in Slave mode. */
281 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr(dwc_otg_hcd_t
*dwc_otg_hcd
)
283 DWC_DEBUGPL(DBG_HCD
, "--Periodic TxFIFO Empty Interrupt--\n");
284 dwc_otg_hcd_queue_transactions(dwc_otg_hcd
,
285 DWC_OTG_TRANSACTION_PERIODIC
);
289 /** There are multiple conditions that can cause a port interrupt. This function
290 * determines which interrupt conditions have occurred and handles them
292 int32_t dwc_otg_hcd_handle_port_intr(dwc_otg_hcd_t
*dwc_otg_hcd
)
296 hprt0_data_t hprt0_modify
;
298 hprt0
.d32
= dwc_read_reg32(dwc_otg_hcd
->core_if
->host_if
->hprt0
);
299 hprt0_modify
.d32
= dwc_read_reg32(dwc_otg_hcd
->core_if
->host_if
->hprt0
);
301 /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
304 hprt0_modify
.b
.prtena
= 0;
305 hprt0_modify
.b
.prtconndet
= 0;
306 hprt0_modify
.b
.prtenchng
= 0;
307 hprt0_modify
.b
.prtovrcurrchng
= 0;
309 /* Port Connect Detected
310 * Set flag and clear if detected */
311 if (hprt0
.b
.prtconndet
) {
312 DWC_DEBUGPL(DBG_HCD
, "--Port Interrupt HPRT0=0x%08x "
313 "Port Connect Detected--\n", hprt0
.d32
);
314 dwc_otg_hcd
->flags
.b
.port_connect_status_change
= 1;
315 dwc_otg_hcd
->flags
.b
.port_connect_status
= 1;
316 hprt0_modify
.b
.prtconndet
= 1;
318 /* B-Device has connected, Delete the connection timer. */
319 del_timer( &dwc_otg_hcd
->conn_timer
);
321 /* The Hub driver asserts a reset when it sees port connect
322 * status change flag */
326 /* Port Enable Changed
327 * Clear if detected - Set internal flag if disabled */
328 if (hprt0
.b
.prtenchng
) {
329 DWC_DEBUGPL(DBG_HCD
, " --Port Interrupt HPRT0=0x%08x "
330 "Port Enable Changed--\n", hprt0
.d32
);
331 hprt0_modify
.b
.prtenchng
= 1;
332 if (hprt0
.b
.prtena
== 1) {
334 dwc_otg_core_params_t
*params
= dwc_otg_hcd
->core_if
->core_params
;
335 dwc_otg_core_global_regs_t
*global_regs
= dwc_otg_hcd
->core_if
->core_global_regs
;
336 dwc_otg_host_if_t
*host_if
= dwc_otg_hcd
->core_if
->host_if
;
338 /* Check if we need to adjust the PHY clock speed for
339 * low power and adjust it */
340 if (params
->host_support_fs_ls_low_power
) {
341 gusbcfg_data_t usbcfg
;
343 usbcfg
.d32
= dwc_read_reg32(&global_regs
->gusbcfg
);
345 if (hprt0
.b
.prtspd
== DWC_HPRT0_PRTSPD_LOW_SPEED
||
346 hprt0
.b
.prtspd
== DWC_HPRT0_PRTSPD_FULL_SPEED
) {
351 if (usbcfg
.b
.phylpwrclksel
== 0) {
352 /* Set PHY low power clock select for FS/LS devices */
353 usbcfg
.b
.phylpwrclksel
= 1;
354 dwc_write_reg32(&global_regs
->gusbcfg
, usbcfg
.d32
);
358 hcfg
.d32
= dwc_read_reg32(&host_if
->host_global_regs
->hcfg
);
360 if (hprt0
.b
.prtspd
== DWC_HPRT0_PRTSPD_LOW_SPEED
&&
361 params
->host_ls_low_power_phy_clk
==
362 DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
) {
364 DWC_DEBUGPL(DBG_CIL
, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
365 if (hcfg
.b
.fslspclksel
!= DWC_HCFG_6_MHZ
) {
366 hcfg
.b
.fslspclksel
= DWC_HCFG_6_MHZ
;
367 dwc_write_reg32(&host_if
->host_global_regs
->hcfg
,
373 DWC_DEBUGPL(DBG_CIL
, "FS_PHY programming HCFG to 48 MHz ()\n");
374 if (hcfg
.b
.fslspclksel
!= DWC_HCFG_48_MHZ
) {
375 hcfg
.b
.fslspclksel
= DWC_HCFG_48_MHZ
;
376 dwc_write_reg32(&host_if
->host_global_regs
->hcfg
,
385 if (usbcfg
.b
.phylpwrclksel
== 1) {
386 usbcfg
.b
.phylpwrclksel
= 0;
387 dwc_write_reg32(&global_regs
->gusbcfg
, usbcfg
.d32
);
393 tasklet_schedule(dwc_otg_hcd
->reset_tasklet
);
398 /* Port has been enabled set the reset change flag */
399 dwc_otg_hcd
->flags
.b
.port_reset_change
= 1;
402 dwc_otg_hcd
->flags
.b
.port_enable_change
= 1;
407 /** Overcurrent Change Interrupt */
408 if (hprt0
.b
.prtovrcurrchng
) {
409 DWC_DEBUGPL(DBG_HCD
, " --Port Interrupt HPRT0=0x%08x "
410 "Port Overcurrent Changed--\n", hprt0
.d32
);
411 dwc_otg_hcd
->flags
.b
.port_over_current_change
= 1;
412 hprt0_modify
.b
.prtovrcurrchng
= 1;
416 /* Clear Port Interrupts */
417 dwc_write_reg32(dwc_otg_hcd
->core_if
->host_if
->hprt0
, hprt0_modify
.d32
);
422 /** This interrupt indicates that one or more host channels has a pending
423 * interrupt. There are multiple conditions that can cause each host channel
424 * interrupt. This function determines which conditions have occurred for each
425 * host channel interrupt and handles them appropriately. */
426 int32_t dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd_t
*dwc_otg_hcd
)
432 /* Clear appropriate bits in HCINTn to clear the interrupt bit in
435 haint
.d32
= dwc_otg_read_host_all_channels_intr(dwc_otg_hcd
->core_if
);
437 for (i
= 0; i
< dwc_otg_hcd
->core_if
->core_params
->host_channels
; i
++) {
438 if (haint
.b2
.chint
& (1 << i
)) {
439 retval
|= dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd
, i
);
446 /* Macro used to clear one channel interrupt */
447 #define clear_hc_int(_hc_regs_, _intr_) \
449 hcint_data_t hcint_clear = {.d32 = 0}; \
450 hcint_clear.b._intr_ = 1; \
451 dwc_write_reg32(&(_hc_regs_)->hcint, hcint_clear.d32); \
455 * Macro used to disable one channel interrupt. Channel interrupts are
456 * disabled when the channel is halted or released by the interrupt handler.
457 * There is no need to handle further interrupts of that type until the
458 * channel is re-assigned. In fact, subsequent handling may cause crashes
459 * because the channel structures are cleaned up when the channel is released.
461 #define disable_hc_int(_hc_regs_, _intr_) \
463 hcintmsk_data_t hcintmsk = {.d32 = 0}; \
464 hcintmsk.b._intr_ = 1; \
465 dwc_modify_reg32(&(_hc_regs_)->hcintmsk, hcintmsk.d32, 0); \
469 * Gets the actual length of a transfer after the transfer halts. _halt_status
470 * holds the reason for the halt.
472 * For IN transfers where halt_status is DWC_OTG_HC_XFER_COMPLETE,
473 * *short_read is set to 1 upon return if less than the requested
474 * number of bytes were transferred. Otherwise, *short_read is set to 0 upon
475 * return. short_read may also be NULL on entry, in which case it remains
478 static uint32_t get_actual_xfer_length(dwc_hc_t
*hc
,
479 dwc_otg_hc_regs_t
*hc_regs
,
481 dwc_otg_halt_status_e halt_status
,
484 hctsiz_data_t hctsiz
;
487 if (short_read
!= NULL
) {
490 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
492 if (halt_status
== DWC_OTG_HC_XFER_COMPLETE
) {
494 length
= hc
->xfer_len
- hctsiz
.b
.xfersize
;
495 if (short_read
!= NULL
) {
496 *short_read
= (hctsiz
.b
.xfersize
!= 0);
498 } else if (hc
->qh
->do_split
) {
499 length
= qtd
->ssplit_out_xfer_count
;
501 length
= hc
->xfer_len
;
505 * Must use the hctsiz.pktcnt field to determine how much data
506 * has been transferred. This field reflects the number of
507 * packets that have been transferred via the USB. This is
508 * always an integral number of packets if the transfer was
509 * halted before its normal completion. (Can't use the
510 * hctsiz.xfersize field because that reflects the number of
511 * bytes transferred via the AHB, not the USB).
513 length
= (hc
->start_pkt_count
- hctsiz
.b
.pktcnt
) * hc
->max_packet
;
520 * Updates the state of the URB after a Transfer Complete interrupt on the
521 * host channel. Updates the actual_length field of the URB based on the
522 * number of bytes transferred via the host channel. Sets the URB status
523 * if the data transfer is finished.
525 * @return 1 if the data transfer specified by the URB is completely finished,
528 static int update_urb_state_xfer_comp(dwc_hc_t
*hc
,
529 dwc_otg_hc_regs_t
*hc_regs
,
539 len
= get_actual_xfer_length(hc
, hc_regs
, qtd
,
540 DWC_OTG_HC_XFER_COMPLETE
,
543 /* Data overflow case: by Steven */
544 if (len
> urb
->transfer_buffer_length
) {
545 len
= urb
->transfer_buffer_length
;
549 /* non DWORD-aligned buffer case handling. */
550 if (((uint32_t)hc
->xfer_buff
& 0x3) && len
&& hc
->qh
->dw_align_buf
&& hc
->ep_is_in
) {
551 memcpy(urb
->transfer_buffer
+ urb
->actual_length
, hc
->qh
->dw_align_buf
, len
);
553 urb
->actual_length
+=len
;
555 max_packet
= usb_maxpacket(urb
->dev
, urb
->pipe
, !usb_pipein(urb
->pipe
));
556 if((len
) && usb_pipebulk(urb
->pipe
) &&
557 (urb
->transfer_flags
& URB_ZERO_PACKET
) &&
558 (urb
->actual_length
== urb
->transfer_buffer_length
) &&
559 (!(urb
->transfer_buffer_length
% max_packet
))) {
560 } else if (short_read
|| urb
->actual_length
== urb
->transfer_buffer_length
) {
562 if (short_read
&& (urb
->transfer_flags
& URB_SHORT_NOT_OK
)) {
563 urb
->status
= -EREMOTEIO
;
564 } else if (overflow_read
) {
565 urb
->status
= -EOVERFLOW
;
573 hctsiz_data_t hctsiz
;
574 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
575 DWC_DEBUGPL(DBG_HCDV
, "DWC_otg: %s: %s, channel %d\n",
576 __func__
, (hc
->ep_is_in
? "IN" : "OUT"), hc
->hc_num
);
577 DWC_DEBUGPL(DBG_HCDV
, " hc->xfer_len %d\n", hc
->xfer_len
);
578 DWC_DEBUGPL(DBG_HCDV
, " hctsiz.xfersize %d\n", hctsiz
.b
.xfersize
);
579 DWC_DEBUGPL(DBG_HCDV
, " urb->transfer_buffer_length %d\n",
580 urb
->transfer_buffer_length
);
581 DWC_DEBUGPL(DBG_HCDV
, " urb->actual_length %d\n", urb
->actual_length
);
582 DWC_DEBUGPL(DBG_HCDV
, " short_read %d, xfer_done %d\n",
583 short_read
, xfer_done
);
591 * Save the starting data toggle for the next transfer. The data toggle is
592 * saved in the QH for non-control transfers and it's saved in the QTD for
595 static void save_data_toggle(dwc_hc_t
*hc
,
596 dwc_otg_hc_regs_t
*hc_regs
,
599 hctsiz_data_t hctsiz
;
600 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
602 if (hc
->ep_type
!= DWC_OTG_EP_TYPE_CONTROL
) {
603 dwc_otg_qh_t
*qh
= hc
->qh
;
604 if (hctsiz
.b
.pid
== DWC_HCTSIZ_DATA0
) {
605 qh
->data_toggle
= DWC_OTG_HC_PID_DATA0
;
607 qh
->data_toggle
= DWC_OTG_HC_PID_DATA1
;
610 if (hctsiz
.b
.pid
== DWC_HCTSIZ_DATA0
) {
611 qtd
->data_toggle
= DWC_OTG_HC_PID_DATA0
;
613 qtd
->data_toggle
= DWC_OTG_HC_PID_DATA1
;
619 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
620 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
621 * still linked to the QH, the QH is added to the end of the inactive
622 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
623 * schedule if no more QTDs are linked to the QH.
625 static void deactivate_qh(dwc_otg_hcd_t
*hcd
,
629 int continue_split
= 0;
632 DWC_DEBUGPL(DBG_HCDV
, " %s(%p,%p,%d)\n", __func__
, hcd
, qh
, free_qtd
);
634 qtd
= list_entry(qh
->qtd_list
.next
, dwc_otg_qtd_t
, qtd_list_entry
);
636 if (qtd
->complete_split
) {
638 } else if (qtd
->isoc_split_pos
== DWC_HCSPLIT_XACTPOS_MID
||
639 qtd
->isoc_split_pos
== DWC_HCSPLIT_XACTPOS_END
) {
644 dwc_otg_hcd_qtd_remove_and_free(hcd
, qtd
);
649 qh
->qtd_in_process
= NULL
;
650 dwc_otg_hcd_qh_deactivate(hcd
, qh
, continue_split
);
654 * Updates the state of an Isochronous URB when the transfer is stopped for
655 * any reason. The fields of the current entry in the frame descriptor array
656 * are set based on the transfer state and the input _halt_status. Completes
657 * the Isochronous URB if all the URB frames have been completed.
659 * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
660 * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
662 static dwc_otg_halt_status_e
663 update_isoc_urb_state(dwc_otg_hcd_t
*hcd
,
665 dwc_otg_hc_regs_t
*hc_regs
,
667 dwc_otg_halt_status_e halt_status
)
669 struct urb
*urb
= qtd
->urb
;
670 dwc_otg_halt_status_e ret_val
= halt_status
;
671 struct usb_iso_packet_descriptor
*frame_desc
;
673 frame_desc
= &urb
->iso_frame_desc
[qtd
->isoc_frame_index
];
674 switch (halt_status
) {
675 case DWC_OTG_HC_XFER_COMPLETE
:
676 frame_desc
->status
= 0;
677 frame_desc
->actual_length
=
678 get_actual_xfer_length(hc
, hc_regs
, qtd
,
681 /* non DWORD-aligned buffer case handling. */
682 if (frame_desc
->actual_length
&& ((uint32_t)hc
->xfer_buff
& 0x3) &&
683 hc
->qh
->dw_align_buf
&& hc
->ep_is_in
) {
684 memcpy(urb
->transfer_buffer
+ frame_desc
->offset
+ qtd
->isoc_split_offset
,
685 hc
->qh
->dw_align_buf
, frame_desc
->actual_length
);
690 case DWC_OTG_HC_XFER_FRAME_OVERRUN
:
691 printk("DWC_OTG_HC_XFER_FRAME_OVERRUN: %d\n", halt_status
);
694 frame_desc
->status
= -ENOSR
;
696 frame_desc
->status
= -ECOMM
;
698 frame_desc
->actual_length
= 0;
700 case DWC_OTG_HC_XFER_BABBLE_ERR
:
701 printk("DWC_OTG_HC_XFER_BABBLE_ERR: %d\n", halt_status
);
703 frame_desc
->status
= -EOVERFLOW
;
704 /* Don't need to update actual_length in this case. */
706 case DWC_OTG_HC_XFER_XACT_ERR
:
707 printk("DWC_OTG_HC_XFER_XACT_ERR: %d\n", halt_status
);
709 frame_desc
->status
= -EPROTO
;
710 frame_desc
->actual_length
=
711 get_actual_xfer_length(hc
, hc_regs
, qtd
,
714 /* non DWORD-aligned buffer case handling. */
715 if (frame_desc
->actual_length
&& ((uint32_t)hc
->xfer_buff
& 0x3) &&
716 hc
->qh
->dw_align_buf
&& hc
->ep_is_in
) {
717 memcpy(urb
->transfer_buffer
+ frame_desc
->offset
+ qtd
->isoc_split_offset
,
718 hc
->qh
->dw_align_buf
, frame_desc
->actual_length
);
724 DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__
,
730 if (++qtd
->isoc_frame_index
== urb
->number_of_packets
) {
732 * urb->status is not used for isoc transfers.
733 * The individual frame_desc statuses are used instead.
735 dwc_otg_hcd_complete_urb(hcd
, urb
, 0);
736 ret_val
= DWC_OTG_HC_XFER_URB_COMPLETE
;
738 ret_val
= DWC_OTG_HC_XFER_COMPLETE
;
745 * Releases a host channel for use by other transfers. Attempts to select and
746 * queue more transactions since at least one host channel is available.
748 * @param hcd The HCD state structure.
749 * @param hc The host channel to release.
750 * @param qtd The QTD associated with the host channel. This QTD may be freed
751 * if the transfer is complete or an error has occurred.
752 * @param halt_status Reason the channel is being released. This status
753 * determines the actions taken by this function.
755 static void release_channel(dwc_otg_hcd_t
*hcd
,
758 dwc_otg_halt_status_e halt_status
)
760 dwc_otg_transaction_type_e tr_type
;
763 DWC_DEBUGPL(DBG_HCDV
, " %s: channel %d, halt_status %d\n",
764 __func__
, hc
->hc_num
, halt_status
);
766 switch (halt_status
) {
767 case DWC_OTG_HC_XFER_URB_COMPLETE
:
770 case DWC_OTG_HC_XFER_AHB_ERR
:
771 case DWC_OTG_HC_XFER_STALL
:
772 case DWC_OTG_HC_XFER_BABBLE_ERR
:
775 case DWC_OTG_HC_XFER_XACT_ERR
:
776 if (qtd
->error_count
>= 3) {
777 DWC_DEBUGPL(DBG_HCDV
, " Complete URB with transaction error\n");
779 qtd
->urb
->status
= -EPROTO
;
780 dwc_otg_hcd_complete_urb(hcd
, qtd
->urb
, -EPROTO
);
785 case DWC_OTG_HC_XFER_URB_DEQUEUE
:
787 * The QTD has already been removed and the QH has been
788 * deactivated. Don't want to do anything except release the
789 * host channel and try to queue more transfers.
792 case DWC_OTG_HC_XFER_NO_HALT_STATUS
:
793 DWC_ERROR("%s: No halt_status, channel %d\n", __func__
, hc
->hc_num
);
801 deactivate_qh(hcd
, hc
->qh
, free_qtd
);
805 * Release the host channel for use by other transfers. The cleanup
806 * function clears the channel interrupt enables and conditions, so
807 * there's no need to clear the Channel Halted interrupt separately.
809 dwc_otg_hc_cleanup(hcd
->core_if
, hc
);
810 list_add_tail(&hc
->hc_list_entry
, &hcd
->free_hc_list
);
812 switch (hc
->ep_type
) {
813 case DWC_OTG_EP_TYPE_CONTROL
:
814 case DWC_OTG_EP_TYPE_BULK
:
815 hcd
->non_periodic_channels
--;
820 * Don't release reservations for periodic channels here.
821 * That's done when a periodic transfer is descheduled (i.e.
822 * when the QH is removed from the periodic schedule).
827 /* Try to queue more transfers now that there's a free channel. */
828 tr_type
= dwc_otg_hcd_select_transactions(hcd
);
829 if (tr_type
!= DWC_OTG_TRANSACTION_NONE
) {
830 dwc_otg_hcd_queue_transactions(hcd
, tr_type
);
835 * Halts a host channel. If the channel cannot be halted immediately because
836 * the request queue is full, this function ensures that the FIFO empty
837 * interrupt for the appropriate queue is enabled so that the halt request can
838 * be queued when there is space in the request queue.
840 * This function may also be called in DMA mode. In that case, the channel is
841 * simply released since the core always halts the channel automatically in
844 static void halt_channel(dwc_otg_hcd_t
*hcd
,
847 dwc_otg_halt_status_e halt_status
)
849 if (hcd
->core_if
->dma_enable
) {
850 release_channel(hcd
, hc
, qtd
, halt_status
);
854 /* Slave mode processing... */
855 dwc_otg_hc_halt(hcd
->core_if
, hc
, halt_status
);
857 if (hc
->halt_on_queue
) {
858 gintmsk_data_t gintmsk
= {.d32
= 0};
859 dwc_otg_core_global_regs_t
*global_regs
;
860 global_regs
= hcd
->core_if
->core_global_regs
;
862 if (hc
->ep_type
== DWC_OTG_EP_TYPE_CONTROL
||
863 hc
->ep_type
== DWC_OTG_EP_TYPE_BULK
) {
865 * Make sure the Non-periodic Tx FIFO empty interrupt
866 * is enabled so that the non-periodic schedule will
869 gintmsk
.b
.nptxfempty
= 1;
870 dwc_modify_reg32(&global_regs
->gintmsk
, 0, gintmsk
.d32
);
873 * Move the QH from the periodic queued schedule to
874 * the periodic assigned schedule. This allows the
875 * halt to be queued when the periodic schedule is
878 list_move(&hc
->qh
->qh_list_entry
,
879 &hcd
->periodic_sched_assigned
);
882 * Make sure the Periodic Tx FIFO Empty interrupt is
883 * enabled so that the periodic schedule will be
886 gintmsk
.b
.ptxfempty
= 1;
887 dwc_modify_reg32(&global_regs
->gintmsk
, 0, gintmsk
.d32
);
893 * Performs common cleanup for non-periodic transfers after a Transfer
894 * Complete interrupt. This function should be called after any endpoint type
895 * specific handling is finished to release the host channel.
897 static void complete_non_periodic_xfer(dwc_otg_hcd_t
*hcd
,
899 dwc_otg_hc_regs_t
*hc_regs
,
901 dwc_otg_halt_status_e halt_status
)
905 qtd
->error_count
= 0;
907 hcint
.d32
= dwc_read_reg32(&hc_regs
->hcint
);
910 * Got a NYET on the last transaction of the transfer. This
911 * means that the endpoint should be in the PING state at the
912 * beginning of the next transfer.
914 hc
->qh
->ping_state
= 1;
915 clear_hc_int(hc_regs
, nyet
);
919 * Always halt and release the host channel to make it available for
920 * more transfers. There may still be more phases for a control
921 * transfer or more data packets for a bulk transfer at this point,
922 * but the host channel is still halted. A channel will be reassigned
923 * to the transfer when the non-periodic schedule is processed after
924 * the channel is released. This allows transactions to be queued
925 * properly via dwc_otg_hcd_queue_transactions, which also enables the
926 * Tx FIFO Empty interrupt if necessary.
930 * IN transfers in Slave mode require an explicit disable to
931 * halt the channel. (In DMA mode, this call simply releases
934 halt_channel(hcd
, hc
, qtd
, halt_status
);
937 * The channel is automatically disabled by the core for OUT
938 * transfers in Slave mode.
940 release_channel(hcd
, hc
, qtd
, halt_status
);
945 * Performs common cleanup for periodic transfers after a Transfer Complete
946 * interrupt. This function should be called after any endpoint type specific
947 * handling is finished to release the host channel.
949 static void complete_periodic_xfer(dwc_otg_hcd_t
*hcd
,
951 dwc_otg_hc_regs_t
*hc_regs
,
953 dwc_otg_halt_status_e halt_status
)
955 hctsiz_data_t hctsiz
;
956 qtd
->error_count
= 0;
958 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
959 if (!hc
->ep_is_in
|| hctsiz
.b
.pktcnt
== 0) {
960 /* Core halts channel in these cases. */
961 release_channel(hcd
, hc
, qtd
, halt_status
);
963 /* Flush any outstanding requests from the Tx queue. */
964 halt_channel(hcd
, hc
, qtd
, halt_status
);
969 * Handles a host channel Transfer Complete interrupt. This handler may be
970 * called in either DMA mode or Slave mode.
972 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t
*hcd
,
974 dwc_otg_hc_regs_t
*hc_regs
,
978 dwc_otg_halt_status_e halt_status
= DWC_OTG_HC_XFER_COMPLETE
;
979 struct urb
*urb
= qtd
->urb
;
980 int pipe_type
= usb_pipetype(urb
->pipe
);
982 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
983 "Transfer Complete--\n", hc
->hc_num
);
986 * Handle xfer complete on CSPLIT.
988 if (hc
->qh
->do_split
) {
989 qtd
->complete_split
= 0;
992 /* Update the QTD and URB states. */
995 switch (qtd
->control_phase
) {
996 case DWC_OTG_CONTROL_SETUP
:
997 if (urb
->transfer_buffer_length
> 0) {
998 qtd
->control_phase
= DWC_OTG_CONTROL_DATA
;
1000 qtd
->control_phase
= DWC_OTG_CONTROL_STATUS
;
1002 DWC_DEBUGPL(DBG_HCDV
, " Control setup transaction done\n");
1003 halt_status
= DWC_OTG_HC_XFER_COMPLETE
;
1005 case DWC_OTG_CONTROL_DATA
: {
1006 urb_xfer_done
= update_urb_state_xfer_comp(hc
, hc_regs
, urb
, qtd
);
1007 if (urb_xfer_done
) {
1008 qtd
->control_phase
= DWC_OTG_CONTROL_STATUS
;
1009 DWC_DEBUGPL(DBG_HCDV
, " Control data transfer done\n");
1011 save_data_toggle(hc
, hc_regs
, qtd
);
1013 halt_status
= DWC_OTG_HC_XFER_COMPLETE
;
1016 case DWC_OTG_CONTROL_STATUS
:
1017 DWC_DEBUGPL(DBG_HCDV
, " Control transfer complete\n");
1018 if (urb
->status
== -EINPROGRESS
) {
1021 dwc_otg_hcd_complete_urb(hcd
, urb
, urb
->status
);
1022 halt_status
= DWC_OTG_HC_XFER_URB_COMPLETE
;
1026 complete_non_periodic_xfer(hcd
, hc
, hc_regs
, qtd
, halt_status
);
1029 DWC_DEBUGPL(DBG_HCDV
, " Bulk transfer complete\n");
1030 urb_xfer_done
= update_urb_state_xfer_comp(hc
, hc_regs
, urb
, qtd
);
1031 if (urb_xfer_done
) {
1032 dwc_otg_hcd_complete_urb(hcd
, urb
, urb
->status
);
1033 halt_status
= DWC_OTG_HC_XFER_URB_COMPLETE
;
1035 halt_status
= DWC_OTG_HC_XFER_COMPLETE
;
1038 save_data_toggle(hc
, hc_regs
, qtd
);
1039 complete_non_periodic_xfer(hcd
, hc
, hc_regs
, qtd
, halt_status
);
1041 case PIPE_INTERRUPT
:
1042 DWC_DEBUGPL(DBG_HCDV
, " Interrupt transfer complete\n");
1043 update_urb_state_xfer_comp(hc
, hc_regs
, urb
, qtd
);
1046 * Interrupt URB is done on the first transfer complete
1049 dwc_otg_hcd_complete_urb(hcd
, urb
, urb
->status
);
1050 save_data_toggle(hc
, hc_regs
, qtd
);
1051 complete_periodic_xfer(hcd
, hc
, hc_regs
, qtd
,
1052 DWC_OTG_HC_XFER_URB_COMPLETE
);
1054 case PIPE_ISOCHRONOUS
:
1055 DWC_DEBUGPL(DBG_HCDV
, " Isochronous transfer complete\n");
1056 if (qtd
->isoc_split_pos
== DWC_HCSPLIT_XACTPOS_ALL
) {
1057 halt_status
= update_isoc_urb_state(hcd
, hc
, hc_regs
, qtd
,
1058 DWC_OTG_HC_XFER_COMPLETE
);
1060 complete_periodic_xfer(hcd
, hc
, hc_regs
, qtd
, halt_status
);
1064 disable_hc_int(hc_regs
, xfercompl
);
1070 * Handles a host channel STALL interrupt. This handler may be called in
1071 * either DMA mode or Slave mode.
1073 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t
*hcd
,
1075 dwc_otg_hc_regs_t
*hc_regs
,
1078 struct urb
*urb
= qtd
->urb
;
1079 int pipe_type
= usb_pipetype(urb
->pipe
);
1081 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1082 "STALL Received--\n", hc
->hc_num
);
1084 if (pipe_type
== PIPE_CONTROL
) {
1085 dwc_otg_hcd_complete_urb(hcd
, urb
, -EPIPE
);
1088 if (pipe_type
== PIPE_BULK
|| pipe_type
== PIPE_INTERRUPT
) {
1089 dwc_otg_hcd_complete_urb(hcd
, urb
, -EPIPE
);
1091 * USB protocol requires resetting the data toggle for bulk
1092 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1093 * setup command is issued to the endpoint. Anticipate the
1094 * CLEAR_FEATURE command since a STALL has occurred and reset
1095 * the data toggle now.
1097 hc
->qh
->data_toggle
= 0;
1100 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_STALL
);
1102 disable_hc_int(hc_regs
, stall
);
1108 * Updates the state of the URB when a transfer has been stopped due to an
1109 * abnormal condition before the transfer completes. Modifies the
1110 * actual_length field of the URB to reflect the number of bytes that have
1111 * actually been transferred via the host channel.
1113 static void update_urb_state_xfer_intr(dwc_hc_t
*hc
,
1114 dwc_otg_hc_regs_t
*hc_regs
,
1117 dwc_otg_halt_status_e halt_status
)
1119 uint32_t bytes_transferred
= get_actual_xfer_length(hc
, hc_regs
, qtd
,
1121 urb
->actual_length
+= bytes_transferred
;
1125 hctsiz_data_t hctsiz
;
1126 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
1127 DWC_DEBUGPL(DBG_HCDV
, "DWC_otg: %s: %s, channel %d\n",
1128 __func__
, (hc
->ep_is_in
? "IN" : "OUT"), hc
->hc_num
);
1129 DWC_DEBUGPL(DBG_HCDV
, " hc->start_pkt_count %d\n", hc
->start_pkt_count
);
1130 DWC_DEBUGPL(DBG_HCDV
, " hctsiz.pktcnt %d\n", hctsiz
.b
.pktcnt
);
1131 DWC_DEBUGPL(DBG_HCDV
, " hc->max_packet %d\n", hc
->max_packet
);
1132 DWC_DEBUGPL(DBG_HCDV
, " bytes_transferred %d\n", bytes_transferred
);
1133 DWC_DEBUGPL(DBG_HCDV
, " urb->actual_length %d\n", urb
->actual_length
);
1134 DWC_DEBUGPL(DBG_HCDV
, " urb->transfer_buffer_length %d\n",
1135 urb
->transfer_buffer_length
);
1141 * Handles a host channel NAK interrupt. This handler may be called in either
1142 * DMA mode or Slave mode.
1144 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t
*hcd
,
1146 dwc_otg_hc_regs_t
*hc_regs
,
1149 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1150 "NAK Received--\n", hc
->hc_num
);
1153 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1154 * interrupt. Re-start the SSPLIT transfer.
1157 if (hc
->complete_split
) {
1158 qtd
->error_count
= 0;
1160 qtd
->complete_split
= 0;
1161 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_NAK
);
1162 goto handle_nak_done
;
1165 switch (usb_pipetype(qtd
->urb
->pipe
)) {
1168 if (hcd
->core_if
->dma_enable
&& hc
->ep_is_in
) {
1170 * NAK interrupts are enabled on bulk/control IN
1171 * transfers in DMA mode for the sole purpose of
1172 * resetting the error count after a transaction error
1173 * occurs. The core will continue transferring data.
1175 qtd
->error_count
= 0;
1176 goto handle_nak_done
;
1180 * NAK interrupts normally occur during OUT transfers in DMA
1181 * or Slave mode. For IN transfers, more requests will be
1182 * queued as request queue space is available.
1184 qtd
->error_count
= 0;
1186 if (!hc
->qh
->ping_state
) {
1187 update_urb_state_xfer_intr(hc
, hc_regs
, qtd
->urb
,
1188 qtd
, DWC_OTG_HC_XFER_NAK
);
1189 save_data_toggle(hc
, hc_regs
, qtd
);
1190 if (qtd
->urb
->dev
->speed
== USB_SPEED_HIGH
) {
1191 hc
->qh
->ping_state
= 1;
1196 * Halt the channel so the transfer can be re-started from
1197 * the appropriate point or the PING protocol will
1200 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_NAK
);
1202 case PIPE_INTERRUPT
:
1203 qtd
->error_count
= 0;
1204 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_NAK
);
1206 case PIPE_ISOCHRONOUS
:
1207 /* Should never get called for isochronous transfers. */
1213 disable_hc_int(hc_regs
, nak
);
1219 * Handles a host channel ACK interrupt. This interrupt is enabled when
1220 * performing the PING protocol in Slave mode, when errors occur during
1221 * either Slave mode or DMA mode, and during Start Split transactions.
1223 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t
*hcd
,
1225 dwc_otg_hc_regs_t
*hc_regs
,
1228 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1229 "ACK Received--\n", hc
->hc_num
);
1233 * Handle ACK on SSPLIT.
1234 * ACK should not occur in CSPLIT.
1236 if (!hc
->ep_is_in
&& hc
->data_pid_start
!= DWC_OTG_HC_PID_SETUP
) {
1237 qtd
->ssplit_out_xfer_count
= hc
->xfer_len
;
1239 if (!(hc
->ep_type
== DWC_OTG_EP_TYPE_ISOC
&& !hc
->ep_is_in
)) {
1240 /* Don't need complete for isochronous out transfers. */
1241 qtd
->complete_split
= 1;
1245 if (hc
->ep_type
== DWC_OTG_EP_TYPE_ISOC
&& !hc
->ep_is_in
) {
1246 switch (hc
->xact_pos
) {
1247 case DWC_HCSPLIT_XACTPOS_ALL
:
1249 case DWC_HCSPLIT_XACTPOS_END
:
1250 qtd
->isoc_split_pos
= DWC_HCSPLIT_XACTPOS_ALL
;
1251 qtd
->isoc_split_offset
= 0;
1253 case DWC_HCSPLIT_XACTPOS_BEGIN
:
1254 case DWC_HCSPLIT_XACTPOS_MID
:
1256 * For BEGIN or MID, calculate the length for
1257 * the next microframe to determine the correct
1258 * SSPLIT token, either MID or END.
1261 struct usb_iso_packet_descriptor
*frame_desc
;
1263 frame_desc
= &qtd
->urb
->iso_frame_desc
[qtd
->isoc_frame_index
];
1264 qtd
->isoc_split_offset
+= 188;
1266 if ((frame_desc
->length
- qtd
->isoc_split_offset
) <= 188) {
1267 qtd
->isoc_split_pos
= DWC_HCSPLIT_XACTPOS_END
;
1269 qtd
->isoc_split_pos
= DWC_HCSPLIT_XACTPOS_MID
;
1276 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_ACK
);
1279 qtd
->error_count
= 0;
1281 if (hc
->qh
->ping_state
) {
1282 hc
->qh
->ping_state
= 0;
1284 * Halt the channel so the transfer can be re-started
1285 * from the appropriate point. This only happens in
1286 * Slave mode. In DMA mode, the ping_state is cleared
1287 * when the transfer is started because the core
1288 * automatically executes the PING, then the transfer.
1290 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_ACK
);
1295 * If the ACK occurred when _not_ in the PING state, let the channel
1296 * continue transferring data after clearing the error count.
1299 disable_hc_int(hc_regs
, ack
);
1305 * Handles a host channel NYET interrupt. This interrupt should only occur on
1306 * Bulk and Control OUT endpoints and for complete split transactions. If a
1307 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1308 * handled in the xfercomp interrupt handler, not here. This handler may be
1309 * called in either DMA mode or Slave mode.
1311 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t
*hcd
,
1313 dwc_otg_hc_regs_t
*hc_regs
,
1316 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1317 "NYET Received--\n", hc
->hc_num
);
1321 * re-do the CSPLIT immediately on non-periodic
1323 if (hc
->do_split
&& hc
->complete_split
) {
1324 if (hc
->ep_type
== DWC_OTG_EP_TYPE_INTR
||
1325 hc
->ep_type
== DWC_OTG_EP_TYPE_ISOC
) {
1326 int frnum
= dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(hcd
));
1328 if (dwc_full_frame_num(frnum
) !=
1329 dwc_full_frame_num(hc
->qh
->sched_frame
)) {
1331 * No longer in the same full speed frame.
1332 * Treat this as a transaction error.
1335 /** @todo Fix system performance so this can
1336 * be treated as an error. Right now complete
1337 * splits cannot be scheduled precisely enough
1338 * due to other system activity, so this error
1339 * occurs regularly in Slave mode.
1343 qtd
->complete_split
= 0;
1344 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_XACT_ERR
);
1345 /** @todo add support for isoc release */
1346 goto handle_nyet_done
;
1350 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_NYET
);
1351 goto handle_nyet_done
;
1354 hc
->qh
->ping_state
= 1;
1355 qtd
->error_count
= 0;
1357 update_urb_state_xfer_intr(hc
, hc_regs
, qtd
->urb
, qtd
,
1358 DWC_OTG_HC_XFER_NYET
);
1359 save_data_toggle(hc
, hc_regs
, qtd
);
1362 * Halt the channel and re-start the transfer so the PING
1363 * protocol will start.
1365 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_NYET
);
1368 disable_hc_int(hc_regs
, nyet
);
1373 * Handles a host channel babble interrupt. This handler may be called in
1374 * either DMA mode or Slave mode.
1376 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t
*hcd
,
1378 dwc_otg_hc_regs_t
*hc_regs
,
1381 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1382 "Babble Error--\n", hc
->hc_num
);
1383 if (hc
->ep_type
!= DWC_OTG_EP_TYPE_ISOC
) {
1384 dwc_otg_hcd_complete_urb(hcd
, qtd
->urb
, -EOVERFLOW
);
1385 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_BABBLE_ERR
);
1387 dwc_otg_halt_status_e halt_status
;
1388 halt_status
= update_isoc_urb_state(hcd
, hc
, hc_regs
, qtd
,
1389 DWC_OTG_HC_XFER_BABBLE_ERR
);
1390 halt_channel(hcd
, hc
, qtd
, halt_status
);
1392 disable_hc_int(hc_regs
, bblerr
);
1397 * Handles a host channel AHB error interrupt. This handler is only called in
1400 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t
*hcd
,
1402 dwc_otg_hc_regs_t
*hc_regs
,
1405 hcchar_data_t hcchar
;
1406 hcsplt_data_t hcsplt
;
1407 hctsiz_data_t hctsiz
;
1409 struct urb
*urb
= qtd
->urb
;
1411 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1412 "AHB Error--\n", hc
->hc_num
);
1414 hcchar
.d32
= dwc_read_reg32(&hc_regs
->hcchar
);
1415 hcsplt
.d32
= dwc_read_reg32(&hc_regs
->hcsplt
);
1416 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
1417 hcdma
= dwc_read_reg32(&hc_regs
->hcdma
);
1419 DWC_ERROR("AHB ERROR, Channel %d\n", hc
->hc_num
);
1420 DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar
.d32
, hcsplt
.d32
);
1421 DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz
.d32
, hcdma
);
1422 DWC_DEBUGPL(DBG_HCD
, "DWC OTG HCD URB Enqueue\n");
1423 DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb
->pipe
));
1424 DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb
->pipe
),
1425 (usb_pipein(urb
->pipe
) ? "IN" : "OUT"));
1426 DWC_ERROR(" Endpoint type: %s\n",
1428 switch (usb_pipetype(urb
->pipe
)) {
1429 case PIPE_CONTROL
: pipetype
= "CONTROL"; break;
1430 case PIPE_BULK
: pipetype
= "BULK"; break;
1431 case PIPE_INTERRUPT
: pipetype
= "INTERRUPT"; break;
1432 case PIPE_ISOCHRONOUS
: pipetype
= "ISOCHRONOUS"; break;
1433 default: pipetype
= "UNKNOWN"; break;
1435 DWC_ERROR(" Speed: %s\n",
1437 switch (urb
->dev
->speed
) {
1438 case USB_SPEED_HIGH
: speed
= "HIGH"; break;
1439 case USB_SPEED_FULL
: speed
= "FULL"; break;
1440 case USB_SPEED_LOW
: speed
= "LOW"; break;
1441 default: speed
= "UNKNOWN"; break;
1443 DWC_ERROR(" Max packet size: %d\n",
1444 usb_maxpacket(urb
->dev
, urb
->pipe
, usb_pipeout(urb
->pipe
)));
1445 DWC_ERROR(" Data buffer length: %d\n", urb
->transfer_buffer_length
);
1446 DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n",
1447 urb
->transfer_buffer
, (void *)urb
->transfer_dma
);
1448 DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n",
1449 urb
->setup_packet
, (void *)urb
->setup_dma
);
1450 DWC_ERROR(" Interval: %d\n", urb
->interval
);
1452 dwc_otg_hcd_complete_urb(hcd
, urb
, -EIO
);
1455 * Force a channel halt. Don't call halt_channel because that won't
1456 * write to the HCCHARn register in DMA mode to force the halt.
1458 dwc_otg_hc_halt(hcd
->core_if
, hc
, DWC_OTG_HC_XFER_AHB_ERR
);
1460 disable_hc_int(hc_regs
, ahberr
);
1465 * Handles a host channel transaction error interrupt. This handler may be
1466 * called in either DMA mode or Slave mode.
1468 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t
*hcd
,
1470 dwc_otg_hc_regs_t
*hc_regs
,
1473 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1474 "Transaction Error--\n", hc
->hc_num
);
1476 switch (usb_pipetype(qtd
->urb
->pipe
)) {
1480 if (!hc
->qh
->ping_state
) {
1481 update_urb_state_xfer_intr(hc
, hc_regs
, qtd
->urb
,
1482 qtd
, DWC_OTG_HC_XFER_XACT_ERR
);
1483 save_data_toggle(hc
, hc_regs
, qtd
);
1484 if (!hc
->ep_is_in
&& qtd
->urb
->dev
->speed
== USB_SPEED_HIGH
) {
1485 hc
->qh
->ping_state
= 1;
1490 * Halt the channel so the transfer can be re-started from
1491 * the appropriate point or the PING protocol will start.
1493 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_XACT_ERR
);
1495 case PIPE_INTERRUPT
:
1497 if (hc
->do_split
&& hc
->complete_split
) {
1498 qtd
->complete_split
= 0;
1500 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_XACT_ERR
);
1502 case PIPE_ISOCHRONOUS
:
1504 dwc_otg_halt_status_e halt_status
;
1505 halt_status
= update_isoc_urb_state(hcd
, hc
, hc_regs
, qtd
,
1506 DWC_OTG_HC_XFER_XACT_ERR
);
1508 halt_channel(hcd
, hc
, qtd
, halt_status
);
1513 disable_hc_int(hc_regs
, xacterr
);
1519 * Handles a host channel frame overrun interrupt. This handler may be called
1520 * in either DMA mode or Slave mode.
1522 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t
*hcd
,
1524 dwc_otg_hc_regs_t
*hc_regs
,
1527 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1528 "Frame Overrun--\n", hc
->hc_num
);
1530 switch (usb_pipetype(qtd
->urb
->pipe
)) {
1534 case PIPE_INTERRUPT
:
1535 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_FRAME_OVERRUN
);
1537 case PIPE_ISOCHRONOUS
:
1539 dwc_otg_halt_status_e halt_status
;
1540 halt_status
= update_isoc_urb_state(hcd
, hc
, hc_regs
, qtd
,
1541 DWC_OTG_HC_XFER_FRAME_OVERRUN
);
1543 halt_channel(hcd
, hc
, qtd
, halt_status
);
1548 disable_hc_int(hc_regs
, frmovrun
);
1554 * Handles a host channel data toggle error interrupt. This handler may be
1555 * called in either DMA mode or Slave mode.
1557 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t
*hcd
,
1559 dwc_otg_hc_regs_t
*hc_regs
,
1562 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1563 "Data Toggle Error--\n", hc
->hc_num
);
1566 qtd
->error_count
= 0;
1568 DWC_ERROR("Data Toggle Error on OUT transfer,"
1569 "channel %d\n", hc
->hc_num
);
1572 disable_hc_int(hc_regs
, datatglerr
);
1579 * This function is for debug only. It checks that a valid halt status is set
1580 * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1581 * taken and a warning is issued.
1582 * @return 1 if halt status is ok, 0 otherwise.
1584 static inline int halt_status_ok(dwc_otg_hcd_t
*hcd
,
1586 dwc_otg_hc_regs_t
*hc_regs
,
1589 hcchar_data_t hcchar
;
1590 hctsiz_data_t hctsiz
;
1592 hcintmsk_data_t hcintmsk
;
1593 hcsplt_data_t hcsplt
;
1595 if (hc
->halt_status
== DWC_OTG_HC_XFER_NO_HALT_STATUS
) {
1597 * This code is here only as a check. This condition should
1598 * never happen. Ignore the halt if it does occur.
1600 hcchar
.d32
= dwc_read_reg32(&hc_regs
->hcchar
);
1601 hctsiz
.d32
= dwc_read_reg32(&hc_regs
->hctsiz
);
1602 hcint
.d32
= dwc_read_reg32(&hc_regs
->hcint
);
1603 hcintmsk
.d32
= dwc_read_reg32(&hc_regs
->hcintmsk
);
1604 hcsplt
.d32
= dwc_read_reg32(&hc_regs
->hcsplt
);
1605 DWC_WARN("%s: hc->halt_status == DWC_OTG"
1606 "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1607 "hcint 0x%08x, hcintmsk 0x%08x, "
1608 "hcsplt 0x%08x, qtd->complete_split %d\n",
1609 __func__
, hc
->hc_num
, hcchar
.d32
, hctsiz
.d32
,
1610 hcint
.d32
, hcintmsk
.d32
,
1611 hcsplt
.d32
, qtd
->complete_split
);
1613 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1614 __func__
, hc
->hc_num
);
1616 clear_hc_int(hc_regs
, chhltd
);
1621 * This code is here only as a check. hcchar.chdis should
1622 * never be set when the halt interrupt occurs. Halt the
1623 * channel again if it does occur.
1625 hcchar
.d32
= dwc_read_reg32(&hc_regs
->hcchar
);
1626 if (hcchar
.b
.chdis
) {
1627 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1628 "hcchar 0x%08x, trying to halt again\n",
1629 __func__
, hcchar
.d32
);
1630 clear_hc_int(hc_regs
, chhltd
);
1631 hc
->halt_pending
= 0;
1632 halt_channel(hcd
, hc
, qtd
, hc
->halt_status
);
1641 * Handles a host Channel Halted interrupt in DMA mode. This handler
1642 * determines the reason the channel halted and proceeds accordingly.
1644 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t
*hcd
,
1646 dwc_otg_hc_regs_t
*hc_regs
,
1650 hcintmsk_data_t hcintmsk
;
1651 int out_nak_enh
= 0;
1653 /* For core with OUT NAK enhancement, the flow for high-
1654 * speed CONTROL/BULK OUT is handled a little differently.
1656 if (hcd
->core_if
->snpsid
>= 0x4F54271A) {
1657 if (hc
->speed
== DWC_OTG_EP_SPEED_HIGH
&& !hc
->ep_is_in
&&
1658 (hc
->ep_type
== DWC_OTG_EP_TYPE_CONTROL
||
1659 hc
->ep_type
== DWC_OTG_EP_TYPE_BULK
)) {
1660 printk(KERN_DEBUG
"OUT NAK enhancement enabled\n");
1663 printk(KERN_DEBUG
"OUT NAK enhancement disabled, not HS Ctrl/Bulk OUT EP\n");
1666 // printk(KERN_DEBUG "OUT NAK enhancement disabled, no core support\n");
1669 if (hc
->halt_status
== DWC_OTG_HC_XFER_URB_DEQUEUE
||
1670 hc
->halt_status
== DWC_OTG_HC_XFER_AHB_ERR
) {
1672 * Just release the channel. A dequeue can happen on a
1673 * transfer timeout. In the case of an AHB Error, the channel
1674 * was forced to halt because there's no way to gracefully
1677 release_channel(hcd
, hc
, qtd
, hc
->halt_status
);
1681 /* Read the HCINTn register to determine the cause for the halt. */
1682 hcint
.d32
= dwc_read_reg32(&hc_regs
->hcint
);
1683 hcintmsk
.d32
= dwc_read_reg32(&hc_regs
->hcintmsk
);
1685 if (hcint
.b
.xfercomp
) {
1686 /** @todo This is here because of a possible hardware bug. Spec
1687 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1688 * interrupt w/ACK bit set should occur, but I only see the
1689 * XFERCOMP bit, even with it masked out. This is a workaround
1690 * for that behavior. Should fix this when hardware is fixed.
1692 if (hc
->ep_type
== DWC_OTG_EP_TYPE_ISOC
&& !hc
->ep_is_in
) {
1693 handle_hc_ack_intr(hcd
, hc
, hc_regs
, qtd
);
1695 handle_hc_xfercomp_intr(hcd
, hc
, hc_regs
, qtd
);
1696 } else if (hcint
.b
.stall
) {
1697 handle_hc_stall_intr(hcd
, hc
, hc_regs
, qtd
);
1698 } else if (hcint
.b
.xacterr
) {
1700 if (hcint
.b
.nyet
|| hcint
.b
.nak
|| hcint
.b
.ack
) {
1701 printk(KERN_DEBUG
"XactErr with NYET/NAK/ACK\n");
1702 qtd
->error_count
= 0;
1704 printk(KERN_DEBUG
"XactErr without NYET/NAK/ACK\n");
1709 * Must handle xacterr before nak or ack. Could get a xacterr
1710 * at the same time as either of these on a BULK/CONTROL OUT
1711 * that started with a PING. The xacterr takes precedence.
1713 handle_hc_xacterr_intr(hcd
, hc
, hc_regs
, qtd
);
1714 } else if (!out_nak_enh
) {
1717 * Must handle nyet before nak or ack. Could get a nyet at the
1718 * same time as either of those on a BULK/CONTROL OUT that
1719 * started with a PING. The nyet takes precedence.
1721 handle_hc_nyet_intr(hcd
, hc
, hc_regs
, qtd
);
1722 } else if (hcint
.b
.bblerr
) {
1723 handle_hc_babble_intr(hcd
, hc
, hc_regs
, qtd
);
1724 } else if (hcint
.b
.frmovrun
) {
1725 handle_hc_frmovrun_intr(hcd
, hc
, hc_regs
, qtd
);
1726 } else if (hcint
.b
.nak
&& !hcintmsk
.b
.nak
) {
1728 * If nak is not masked, it's because a non-split IN transfer
1729 * is in an error state. In that case, the nak is handled by
1730 * the nak interrupt handler, not here. Handle nak here for
1731 * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1732 * rewinding the buffer pointer.
1734 handle_hc_nak_intr(hcd
, hc
, hc_regs
, qtd
);
1735 } else if (hcint
.b
.ack
&& !hcintmsk
.b
.ack
) {
1737 * If ack is not masked, it's because a non-split IN transfer
1738 * is in an error state. In that case, the ack is handled by
1739 * the ack interrupt handler, not here. Handle ack here for
1740 * split transfers. Start splits halt on ACK.
1742 handle_hc_ack_intr(hcd
, hc
, hc_regs
, qtd
);
1744 if (hc
->ep_type
== DWC_OTG_EP_TYPE_INTR
||
1745 hc
->ep_type
== DWC_OTG_EP_TYPE_ISOC
) {
1747 * A periodic transfer halted with no other channel
1748 * interrupts set. Assume it was halted by the core
1749 * because it could not be completed in its scheduled
1753 DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1754 __func__
, hc
->hc_num
);
1756 halt_channel(hcd
, hc
, qtd
, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE
);
1758 DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1759 "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1760 __func__
, hc
->hc_num
, hcint
.d32
,
1761 dwc_read_reg32(&hcd
->core_if
->core_global_regs
->gintsts
));
1765 printk(KERN_DEBUG
"NYET/NAK/ACK/other in non-error case, 0x%08x\n", hcint
.d32
);
1770 * Handles a host channel Channel Halted interrupt.
1772 * In slave mode, this handler is called only when the driver specifically
1773 * requests a halt. This occurs during handling other host channel interrupts
1774 * (e.g. nak, xacterr, stall, nyet, etc.).
1776 * In DMA mode, this is the interrupt that occurs when the core has finished
1777 * processing a transfer on a channel. Other host channel interrupts (except
1778 * ahberr) are disabled in DMA mode.
1780 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t
*hcd
,
1782 dwc_otg_hc_regs_t
*hc_regs
,
1785 DWC_DEBUGPL(DBG_HCD
, "--Host Channel %d Interrupt: "
1786 "Channel Halted--\n", hc
->hc_num
);
1788 if (hcd
->core_if
->dma_enable
) {
1789 handle_hc_chhltd_intr_dma(hcd
, hc
, hc_regs
, qtd
);
1792 if (!halt_status_ok(hcd
, hc
, hc_regs
, qtd
)) {
1796 release_channel(hcd
, hc
, qtd
, hc
->halt_status
);
1802 /** Handles interrupt for a specific Host Channel */
1803 int32_t dwc_otg_hcd_handle_hc_n_intr(dwc_otg_hcd_t
*dwc_otg_hcd
, uint32_t num
)
1807 hcintmsk_data_t hcintmsk
;
1809 dwc_otg_hc_regs_t
*hc_regs
;
1812 DWC_DEBUGPL(DBG_HCDV
, "--Host Channel Interrupt--, Channel %d\n", num
);
1814 hc
= dwc_otg_hcd
->hc_ptr_array
[num
];
1815 hc_regs
= dwc_otg_hcd
->core_if
->host_if
->hc_regs
[num
];
1816 qtd
= list_entry(hc
->qh
->qtd_list
.next
, dwc_otg_qtd_t
, qtd_list_entry
);
1818 hcint
.d32
= dwc_read_reg32(&hc_regs
->hcint
);
1819 hcintmsk
.d32
= dwc_read_reg32(&hc_regs
->hcintmsk
);
1820 DWC_DEBUGPL(DBG_HCDV
, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1821 hcint
.d32
, hcintmsk
.d32
, (hcint
.d32
& hcintmsk
.d32
));
1822 hcint
.d32
= hcint
.d32
& hcintmsk
.d32
;
1824 if (!dwc_otg_hcd
->core_if
->dma_enable
) {
1825 if (hcint
.b
.chhltd
&& hcint
.d32
!= 0x2) {
1830 if (hcint
.b
.xfercomp
) {
1831 retval
|= handle_hc_xfercomp_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1833 * If NYET occurred at same time as Xfer Complete, the NYET is
1834 * handled by the Xfer Complete interrupt handler. Don't want
1835 * to call the NYET interrupt handler in this case.
1839 if (hcint
.b
.chhltd
) {
1840 retval
|= handle_hc_chhltd_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1842 if (hcint
.b
.ahberr
) {
1843 retval
|= handle_hc_ahberr_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1845 if (hcint
.b
.stall
) {
1846 retval
|= handle_hc_stall_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1849 retval
|= handle_hc_nak_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1852 retval
|= handle_hc_ack_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1855 retval
|= handle_hc_nyet_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1857 if (hcint
.b
.xacterr
) {
1858 retval
|= handle_hc_xacterr_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1860 if (hcint
.b
.bblerr
) {
1861 retval
|= handle_hc_babble_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1863 if (hcint
.b
.frmovrun
) {
1864 retval
|= handle_hc_frmovrun_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1866 if (hcint
.b
.datatglerr
) {
1867 retval
|= handle_hc_datatglerr_intr(dwc_otg_hcd
, hc
, hc_regs
, qtd
);
1873 #endif /* DWC_DEVICE_ONLY */