target/linux/ramips/files-4.14/drivers/net/ethernet/mediatek/soc_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/of_net.h>
  19
  20 #include <asm/mach-ralink/ralink_regs.h>
  21
  22 #include <mt7620.h>
  23 #include "mtk_eth_soc.h"
  24 #include "gsw_mt7620.h"
  25 #include "mt7530.h"
  26 #include "mdio.h"
  27
  28 #define MT7620A_CDMA_CSG_CFG    0x400
  29 #define MT7620_DMA_VID          (MT7620A_CDMA_CSG_CFG | 0x30)
  30 #define MT7621_CDMP_IG_CTRL     (MT7620A_CDMA_CSG_CFG + 0x00)
  31 #define MT7621_CDMP_EG_CTRL     (MT7620A_CDMA_CSG_CFG + 0x04)
  32 #define MT7620A_RESET_FE        BIT(21)
  33 #define MT7621_RESET_FE         BIT(6)
  34 #define MT7620A_RESET_ESW       BIT(23)
  35 #define MT7620_L4_VALID         BIT(23)
  36 #define MT7621_L4_VALID         BIT(24)
  37
  38 #define MT7620_TX_DMA_UDF       BIT(15)
  39 #define MT7621_TX_DMA_UDF       BIT(19)
  40 #define TX_DMA_FP_BMAP          ((0xff) << 19)
  41
  42 #define CDMA_ICS_EN             BIT(2)
  43 #define CDMA_UCS_EN             BIT(1)
  44 #define CDMA_TCS_EN             BIT(0)
  45
  46 #define GDMA_ICS_EN             BIT(22)
  47 #define GDMA_TCS_EN             BIT(21)
  48 #define GDMA_UCS_EN             BIT(20)
  49
  50 /* frame engine counters */
  51 #define MT7620_REG_MIB_OFFSET   0x1000
  52 #define MT7620_PPE_AC_BCNT0     (MT7620_REG_MIB_OFFSET + 0x00)
  53 #define MT7620_GDM1_TX_GBCNT    (MT7620_REG_MIB_OFFSET + 0x300)
  54 #define MT7620_GDM2_TX_GBCNT    (MT7620_GDM1_TX_GBCNT + 0x40)
  55
  56 #define MT7621_REG_MIB_OFFSET   0x2000
  57 #define MT7621_PPE_AC_BCNT0     (MT7621_REG_MIB_OFFSET + 0x00)
  58 #define MT7621_GDM1_TX_GBCNT    (MT7621_REG_MIB_OFFSET + 0x400)
  59 #define MT7621_GDM2_TX_GBCNT    (MT7621_GDM1_TX_GBCNT + 0x40)
  60
  61 #define GSW_REG_GDMA1_MAC_ADRL  0x508
  62 #define GSW_REG_GDMA1_MAC_ADRH  0x50C
  63
  64 #define MT7621_FE_RST_GL        (FE_FE_OFFSET + 0x04)
  65 #define MT7620_FE_INT_STATUS2   (FE_FE_OFFSET + 0x08)
  66
  67 /* FE_INT_STATUS reg on mt7620 define CNT_GDM1_AF at BIT(29)
  68  * but after test it should be BIT(13).
  69  */
  70 #define MT7620_FE_GDM1_AF       BIT(13)
  71 #define MT7621_FE_GDM1_AF       BIT(28)
  72 #define MT7621_FE_GDM2_AF       BIT(29)
  73
  74 static const u16 mt7620_reg_table[FE_REG_COUNT] = {
  75         [FE_REG_PDMA_GLO_CFG] = RT5350_PDMA_GLO_CFG,
  76         [FE_REG_PDMA_RST_CFG] = RT5350_PDMA_RST_CFG,
  77         [FE_REG_DLY_INT_CFG] = RT5350_DLY_INT_CFG,
  78         [FE_REG_TX_BASE_PTR0] = RT5350_TX_BASE_PTR0,
  79         [FE_REG_TX_MAX_CNT0] = RT5350_TX_MAX_CNT0,
  80         [FE_REG_TX_CTX_IDX0] = RT5350_TX_CTX_IDX0,
  81         [FE_REG_TX_DTX_IDX0] = RT5350_TX_DTX_IDX0,
  82         [FE_REG_RX_BASE_PTR0] = RT5350_RX_BASE_PTR0,
  83         [FE_REG_RX_MAX_CNT0] = RT5350_RX_MAX_CNT0,
  84         [FE_REG_RX_CALC_IDX0] = RT5350_RX_CALC_IDX0,
  85         [FE_REG_RX_DRX_IDX0] = RT5350_RX_DRX_IDX0,
  86         [FE_REG_FE_INT_ENABLE] = RT5350_FE_INT_ENABLE,
  87         [FE_REG_FE_INT_STATUS] = RT5350_FE_INT_STATUS,
  88         [FE_REG_FE_DMA_VID_BASE] = MT7620_DMA_VID,
  89         [FE_REG_FE_COUNTER_BASE] = MT7620_GDM1_TX_GBCNT,
  90         [FE_REG_FE_RST_GL] = MT7621_FE_RST_GL,
  91         [FE_REG_FE_INT_STATUS2] = MT7620_FE_INT_STATUS2,
  92 };
  93
  94 static int mt7620_gsw_config(struct fe_priv *priv)
  95 {
  96         struct mt7620_gsw *gsw = (struct mt7620_gsw *) priv->soc->swpriv;
  97
  98         /* is the mt7530 internal or external */
  99         if (priv->mii_bus && mdiobus_get_phy(priv->mii_bus, 0x1f)) {
 100                 mt7530_probe(priv->dev, gsw->base, NULL, 0);
 101                 mt7530_probe(priv->dev, NULL, priv->mii_bus, 1);
 102         } else {
 103                 mt7530_probe(priv->dev, gsw->base, NULL, 1);
 104         }
 105
 106         return 0;
 107 }
 108
 109 static void mt7620_set_mac(struct fe_priv *priv, unsigned char *mac)
 110 {
 111         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 112         unsigned long flags;
 113
 114         spin_lock_irqsave(&priv->page_lock, flags);
 115         mtk_switch_w32(gsw, (mac[0] << 8) | mac[1], GSW_REG_SMACCR1);
 116         mtk_switch_w32(gsw, (mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
 117                 GSW_REG_SMACCR0);
 118         spin_unlock_irqrestore(&priv->page_lock, flags);
 119 }
 120
 121 static void mt7620_auto_poll(struct mt7620_gsw *gsw, int port)
 122 {
 123         int phy;
 124         int lsb = -1, msb = 0;
 125
 126         for_each_set_bit(phy, &gsw->autopoll, 32) {
 127                 if (lsb < 0)
 128                         lsb = phy;
 129                 msb = phy;
 130         }
 131
 132         if (lsb == msb && port ==  4)
 133                 msb++;
 134         else if (lsb == msb && port ==  5)
 135                 lsb--;
 136
 137         mtk_switch_w32(gsw, PHY_AN_EN | PHY_PRE_EN | PMY_MDC_CONF(5) |
 138                 (msb << 8) | lsb, ESW_PHY_POLLING);
 139 }
 140
 141 static void mt7620_port_init(struct fe_priv *priv, struct device_node *np)
 142 {
 143         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
 144         const __be32 *_id = of_get_property(np, "reg", NULL);
 145         const __be32 *phy_addr;
 146         int phy_mode, size, id;
 147         int shift = 12;
 148         u32 val, mask = 0;
 149         u32 val_delay = 0;
 150         u32 mask_delay = GSW_REG_GPCx_TXDELAY | GSW_REG_GPCx_RXDELAY;
 151         int min = (gsw->port4 == PORT4_EPHY) ? (5) : (4);
 152
 153         if (!_id || (be32_to_cpu(*_id) < min) || (be32_to_cpu(*_id) > 5)) {
 154                 if (_id)
 155                         pr_err("%s: invalid port id %d\n", np->name,
 156                                be32_to_cpu(*_id));
 157                 else
 158                         pr_err("%s: invalid port id\n", np->name);
 159                 return;
 160         }
 161
 162         id = be32_to_cpu(*_id);
 163
 164         if (id == 4)
 165                 shift = 14;
 166
 167         priv->phy->phy_fixed[id] = of_get_property(np, "mediatek,fixed-link",
 168                                                    &size);
 169         if (priv->phy->phy_fixed[id] &&
 170             (size != (4 * sizeof(*priv->phy->phy_fixed[id])))) {
 171                 pr_err("%s: invalid fixed link property\n", np->name);
 172                 priv->phy->phy_fixed[id] = NULL;
 173                 return;
 174         }
 175
 176         phy_mode = of_get_phy_mode(np);
 177         switch (phy_mode) {
 178         case PHY_INTERFACE_MODE_RGMII:
 179                 mask = 0;
 180                 /* Do not touch rx/tx delay in this state to avoid problems with
 181                  * backward compability.
 182                  */
 183                 mask_delay = 0;
 184                 break;
 185         case PHY_INTERFACE_MODE_RGMII_ID:
 186                 mask = 0;
 187                 val_delay |= GSW_REG_GPCx_TXDELAY;
 188                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 189                 break;
 190         case PHY_INTERFACE_MODE_RGMII_RXID:
 191                 mask = 0;
 192                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 193                 val_delay &= ~GSW_REG_GPCx_RXDELAY;
 194                 break;
 195         case PHY_INTERFACE_MODE_RGMII_TXID:
 196                 mask = 0;
 197                 val_delay &= ~GSW_REG_GPCx_TXDELAY;
 198                 val_delay |= GSW_REG_GPCx_RXDELAY;
 199                 break;
 200         case PHY_INTERFACE_MODE_MII:
 201                 mask = 1;
 202                 break;
 203         case PHY_INTERFACE_MODE_RMII:
 204                 mask = 2;
 205                 break;
 206         default:
 207                 dev_err(priv->dev, "port %d - invalid phy mode\n", id);
 208                 return;
 209         }
 210
 211         priv->phy->phy_node[id] = of_parse_phandle(np, "phy-handle", 0);
 212         if (!priv->phy->phy_node[id] && !priv->phy->phy_fixed[id])
 213                 return;
 214
 215         val = rt_sysc_r32(SYSC_REG_CFG1);
 216         val &= ~(3 << shift);
 217         val |= mask << shift;
 218         rt_sysc_w32(val, SYSC_REG_CFG1);
 219
 220         if (id == 4) {
 221                 val = mtk_switch_r32(gsw, GSW_REG_GPC2);
 222                 val &= ~(mask_delay);
 223                 val |= val_delay & mask_delay;
 224                 mtk_switch_w32(gsw, val, GSW_REG_GPC2);
 225         }
 226         else if (id == 5) {
 227                 val = mtk_switch_r32(gsw, GSW_REG_GPC1);
 228                 val &= ~(mask_delay);
 229                 val |= val_delay & mask_delay;
 230                 mtk_switch_w32(gsw, val, GSW_REG_GPC1);
 231         }
 232
 233         if (priv->phy->phy_fixed[id]) {
 234                 const __be32 *link = priv->phy->phy_fixed[id];
 235                 int tx_fc, rx_fc;
 236                 u32 val = 0;
 237
 238                 priv->phy->speed[id] = be32_to_cpup(link++);
 239                 tx_fc = be32_to_cpup(link++);
 240                 rx_fc = be32_to_cpup(link++);
 241                 priv->phy->duplex[id] = be32_to_cpup(link++);
 242                 priv->link[id] = 1;
 243
 244                 switch (priv->phy->speed[id]) {
 245                 case SPEED_10:
 246                         val = 0;
 247                         break;
 248                 case SPEED_100:
 249                         val = 1;
 250                         break;
 251                 case SPEED_1000:
 252                         val = 2;
 253                         break;
 254                 default:
 255                         dev_err(priv->dev, "invalid link speed: %d\n",
 256                                 priv->phy->speed[id]);
 257                         priv->phy->phy_fixed[id] = 0;
 258                         return;
 259                 }
 260                 val = PMCR_SPEED(val);
 261                 val |= PMCR_LINK | PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 262                         PMCR_TX_EN | PMCR_FORCE | PMCR_MAC_MODE | PMCR_IPG;
 263                 if (tx_fc)
 264                         val |= PMCR_TX_FC;
 265                 if (rx_fc)
 266                         val |= PMCR_RX_FC;
 267                 if (priv->phy->duplex[id])
 268                         val |= PMCR_DUPLEX;
 269                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 270                 dev_info(priv->dev, "using fixed link parameters\n");
 271                 return;
 272         }
 273
 274         phy_addr = of_get_property(priv->phy->phy_node[id], "reg", NULL);
 275         if (phy_addr && mdiobus_get_phy(priv->mii_bus, be32_to_cpup(phy_addr))) {
 276                 u32 val = PMCR_BACKPRES | PMCR_BACKOFF | PMCR_RX_EN |
 277                         PMCR_TX_EN |  PMCR_MAC_MODE | PMCR_IPG;
 278
 279                 mtk_switch_w32(gsw, val, GSW_REG_PORT_PMCR(id));
 280                 fe_connect_phy_node(priv, priv->phy->phy_node[id], id);
 281                 gsw->autopoll |= BIT(be32_to_cpup(phy_addr));
 282                 mt7620_auto_poll(gsw,id);
 283                 return;
 284         }
 285 }
 286
 287 static void mt7620_fe_reset(void)
 288 {
 289         fe_reset(MT7620A_RESET_FE | MT7620A_RESET_ESW);
 290 }
 291
 292 static void mt7620_rxcsum_config(bool enable)
 293 {
 294         if (enable)
 295                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) | (GDMA_ICS_EN |
 296                                         GDMA_TCS_EN | GDMA_UCS_EN),
 297                                 MT7620A_GDMA1_FWD_CFG);
 298         else
 299                 fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~(GDMA_ICS_EN |
 300                                         GDMA_TCS_EN | GDMA_UCS_EN),
 301                                 MT7620A_GDMA1_FWD_CFG);
 302 }
 303
 304 static void mt7620_txcsum_config(bool enable)
 305 {
 306         if (enable)
 307                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) | (CDMA_ICS_EN |
 308                                         CDMA_UCS_EN | CDMA_TCS_EN),
 309                                 MT7620A_CDMA_CSG_CFG);
 310         else
 311                 fe_w32(fe_r32(MT7620A_CDMA_CSG_CFG) & ~(CDMA_ICS_EN |
 312                                         CDMA_UCS_EN | CDMA_TCS_EN),
 313                                 MT7620A_CDMA_CSG_CFG);
 314 }
 315
 316 static int mt7620_fwd_config(struct fe_priv *priv)
 317 {
 318         struct net_device *dev = priv_netdev(priv);
 319
 320         fe_w32(fe_r32(MT7620A_GDMA1_FWD_CFG) & ~7, MT7620A_GDMA1_FWD_CFG);
 321
 322         mt7620_txcsum_config((dev->features & NETIF_F_IP_CSUM));
 323         mt7620_rxcsum_config((dev->features & NETIF_F_RXCSUM));
 324
 325         return 0;
 326 }
 327
 328 static void mt7620_tx_dma(struct fe_tx_dma *txd)
 329 {
 330 }
 331
 332 static void mt7620_init_data(struct fe_soc_data *data,
 333                              struct net_device *netdev)
 334 {
 335         struct fe_priv *priv = netdev_priv(netdev);
 336
 337         priv->flags = FE_FLAG_PADDING_64B | FE_FLAG_RX_2B_OFFSET |
 338                 FE_FLAG_RX_SG_DMA | FE_FLAG_HAS_SWITCH;
 339
 340         netdev->hw_features = NETIF_F_IP_CSUM | NETIF_F_RXCSUM |
 341                 NETIF_F_HW_VLAN_CTAG_TX;
 342         if (mt7620_get_eco() >= 5)
 343                 netdev->hw_features |= NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 |
 344                         NETIF_F_IPV6_CSUM;
 345 }
 346
 347 static struct fe_soc_data mt7620_data = {
 348         .init_data = mt7620_init_data,
 349         .reset_fe = mt7620_fe_reset,
 350         .set_mac = mt7620_set_mac,
 351         .fwd_config = mt7620_fwd_config,
 352         .tx_dma = mt7620_tx_dma,
 353         .switch_init = mtk_gsw_init,
 354         .switch_config = mt7620_gsw_config,
 355         .port_init = mt7620_port_init,
 356         .reg_table = mt7620_reg_table,
 357         .pdma_glo_cfg = FE_PDMA_SIZE_16DWORDS,
 358         .rx_int = RT5350_RX_DONE_INT,
 359         .tx_int = RT5350_TX_DONE_INT,
 360         .status_int = MT7620_FE_GDM1_AF,
 361         .checksum_bit = MT7620_L4_VALID,
 362         .has_carrier = mt7620_has_carrier,
 363         .mdio_read = mt7620_mdio_read,
 364         .mdio_write = mt7620_mdio_write,
 365         .mdio_adjust_link = mt7620_mdio_link_adjust,
 366 };
 367
 368 const struct of_device_id of_fe_match[] = {
 369         { .compatible = "mediatek,mt7620-eth", .data = &mt7620_data },
 370         {},
 371 };
 372
 373 MODULE_DEVICE_TABLE(of, of_fe_match);