1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
32 #include <linux/bug.h>
34 #include <asm/mach-ralink/ralink_regs.h>
36 #include "mtk_eth_soc.h"
40 #define MAX_RX_LENGTH 1536
41 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
42 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
43 #define DMA_DUMMY_DESC 0xffffffff
44 #define FE_DEFAULT_MSG_ENABLE \
54 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
55 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
56 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
57 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
59 #define SYSC_REG_RSTCTRL 0x34
61 static int fe_msg_level
= -1;
62 module_param_named(msg_level
, fe_msg_level
, int, 0);
63 MODULE_PARM_DESC(msg_level
, "Message level (-1=defaults,0=none,...,16=all)");
65 static const u16 fe_reg_table_default
[FE_REG_COUNT
] = {
66 [FE_REG_PDMA_GLO_CFG
] = FE_PDMA_GLO_CFG
,
67 [FE_REG_PDMA_RST_CFG
] = FE_PDMA_RST_CFG
,
68 [FE_REG_DLY_INT_CFG
] = FE_DLY_INT_CFG
,
69 [FE_REG_TX_BASE_PTR0
] = FE_TX_BASE_PTR0
,
70 [FE_REG_TX_MAX_CNT0
] = FE_TX_MAX_CNT0
,
71 [FE_REG_TX_CTX_IDX0
] = FE_TX_CTX_IDX0
,
72 [FE_REG_TX_DTX_IDX0
] = FE_TX_DTX_IDX0
,
73 [FE_REG_RX_BASE_PTR0
] = FE_RX_BASE_PTR0
,
74 [FE_REG_RX_MAX_CNT0
] = FE_RX_MAX_CNT0
,
75 [FE_REG_RX_CALC_IDX0
] = FE_RX_CALC_IDX0
,
76 [FE_REG_RX_DRX_IDX0
] = FE_RX_DRX_IDX0
,
77 [FE_REG_FE_INT_ENABLE
] = FE_FE_INT_ENABLE
,
78 [FE_REG_FE_INT_STATUS
] = FE_FE_INT_STATUS
,
79 [FE_REG_FE_DMA_VID_BASE
] = FE_DMA_VID0
,
80 [FE_REG_FE_COUNTER_BASE
] = FE_GDMA1_TX_GBCNT
,
81 [FE_REG_FE_RST_GL
] = FE_FE_RST_GL
,
84 static const u16
*fe_reg_table
= fe_reg_table_default
;
88 void (*action
)(struct fe_priv
*);
91 static void __iomem
*fe_base
;
93 void fe_w32(u32 val
, unsigned reg
)
95 __raw_writel(val
, fe_base
+ reg
);
98 u32
fe_r32(unsigned reg
)
100 return __raw_readl(fe_base
+ reg
);
103 void fe_reg_w32(u32 val
, enum fe_reg reg
)
105 fe_w32(val
, fe_reg_table
[reg
]);
108 u32
fe_reg_r32(enum fe_reg reg
)
110 return fe_r32(fe_reg_table
[reg
]);
113 void fe_reset(u32 reset_bits
)
117 t
= rt_sysc_r32(SYSC_REG_RSTCTRL
);
119 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
120 usleep_range(10, 20);
123 rt_sysc_w32(t
, SYSC_REG_RSTCTRL
);
124 usleep_range(10, 20);
127 static inline void fe_int_disable(u32 mask
)
129 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) & ~mask
,
130 FE_REG_FE_INT_ENABLE
);
132 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
135 static inline void fe_int_enable(u32 mask
)
137 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE
) | mask
,
138 FE_REG_FE_INT_ENABLE
);
140 fe_reg_r32(FE_REG_FE_INT_ENABLE
);
143 static inline void fe_hw_set_macaddr(struct fe_priv
*priv
, unsigned char *mac
)
147 spin_lock_irqsave(&priv
->page_lock
, flags
);
148 fe_w32((mac
[0] << 8) | mac
[1], FE_GDMA1_MAC_ADRH
);
149 fe_w32((mac
[2] << 24) | (mac
[3] << 16) | (mac
[4] << 8) | mac
[5],
151 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
154 static int fe_set_mac_address(struct net_device
*dev
, void *p
)
156 int ret
= eth_mac_addr(dev
, p
);
159 struct fe_priv
*priv
= netdev_priv(dev
);
161 if (priv
->soc
->set_mac
)
162 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
164 fe_hw_set_macaddr(priv
, p
);
170 static inline int fe_max_frag_size(int mtu
)
172 /* make sure buf_size will be at least MAX_RX_LENGTH */
173 if (mtu
+ FE_RX_ETH_HLEN
< MAX_RX_LENGTH
)
174 mtu
= MAX_RX_LENGTH
- FE_RX_ETH_HLEN
;
176 return SKB_DATA_ALIGN(FE_RX_HLEN
+ mtu
) +
177 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
180 static inline int fe_max_buf_size(int frag_size
)
182 int buf_size
= frag_size
- NET_SKB_PAD
- NET_IP_ALIGN
-
183 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
185 BUG_ON(buf_size
< MAX_RX_LENGTH
);
189 static inline void fe_get_rxd(struct fe_rx_dma
*rxd
, struct fe_rx_dma
*dma_rxd
)
191 rxd
->rxd1
= dma_rxd
->rxd1
;
192 rxd
->rxd2
= dma_rxd
->rxd2
;
193 rxd
->rxd3
= dma_rxd
->rxd3
;
194 rxd
->rxd4
= dma_rxd
->rxd4
;
197 static inline void fe_set_txd(struct fe_tx_dma
*txd
, struct fe_tx_dma
*dma_txd
)
199 dma_txd
->txd1
= txd
->txd1
;
200 dma_txd
->txd3
= txd
->txd3
;
201 dma_txd
->txd4
= txd
->txd4
;
202 /* clean dma done flag last */
203 dma_txd
->txd2
= txd
->txd2
;
206 static void fe_clean_rx(struct fe_priv
*priv
)
209 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
212 for (i
= 0; i
< ring
->rx_ring_size
; i
++)
213 if (ring
->rx_data
[i
]) {
214 if (ring
->rx_dma
&& ring
->rx_dma
[i
].rxd1
)
215 dma_unmap_single(&priv
->netdev
->dev
,
216 ring
->rx_dma
[i
].rxd1
,
219 put_page(virt_to_head_page(ring
->rx_data
[i
]));
222 kfree(ring
->rx_data
);
223 ring
->rx_data
= NULL
;
227 dma_free_coherent(&priv
->netdev
->dev
,
228 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
235 static int fe_alloc_rx(struct fe_priv
*priv
)
237 struct net_device
*netdev
= priv
->netdev
;
238 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
241 ring
->rx_data
= kcalloc(ring
->rx_ring_size
, sizeof(*ring
->rx_data
),
246 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
247 ring
->rx_data
[i
] = netdev_alloc_frag(ring
->frag_size
);
248 if (!ring
->rx_data
[i
])
252 ring
->rx_dma
= dma_alloc_coherent(&netdev
->dev
,
253 ring
->rx_ring_size
* sizeof(*ring
->rx_dma
),
255 GFP_ATOMIC
| __GFP_ZERO
);
259 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
263 for (i
= 0; i
< ring
->rx_ring_size
; i
++) {
264 dma_addr_t dma_addr
= dma_map_single(&netdev
->dev
,
265 ring
->rx_data
[i
] + NET_SKB_PAD
+ pad
,
268 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
)))
270 ring
->rx_dma
[i
].rxd1
= (unsigned int)dma_addr
;
272 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
273 ring
->rx_dma
[i
].rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
275 ring
->rx_dma
[i
].rxd2
= RX_DMA_LSO
;
277 ring
->rx_calc_idx
= ring
->rx_ring_size
- 1;
278 /* make sure that all changes to the dma ring are flushed before we
283 fe_reg_w32(ring
->rx_phys
, FE_REG_RX_BASE_PTR0
);
284 fe_reg_w32(ring
->rx_ring_size
, FE_REG_RX_MAX_CNT0
);
285 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
286 fe_reg_w32(FE_PST_DRX_IDX0
, FE_REG_PDMA_RST_CFG
);
294 static void fe_txd_unmap(struct device
*dev
, struct fe_tx_buf
*tx_buf
)
296 if (tx_buf
->flags
& FE_TX_FLAGS_SINGLE0
) {
297 dma_unmap_single(dev
,
298 dma_unmap_addr(tx_buf
, dma_addr0
),
299 dma_unmap_len(tx_buf
, dma_len0
),
301 } else if (tx_buf
->flags
& FE_TX_FLAGS_PAGE0
) {
303 dma_unmap_addr(tx_buf
, dma_addr0
),
304 dma_unmap_len(tx_buf
, dma_len0
),
307 if (tx_buf
->flags
& FE_TX_FLAGS_PAGE1
)
309 dma_unmap_addr(tx_buf
, dma_addr1
),
310 dma_unmap_len(tx_buf
, dma_len1
),
314 if (tx_buf
->skb
&& (tx_buf
->skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
))
315 dev_kfree_skb_any(tx_buf
->skb
);
319 static void fe_clean_tx(struct fe_priv
*priv
)
322 struct device
*dev
= &priv
->netdev
->dev
;
323 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
326 for (i
= 0; i
< ring
->tx_ring_size
; i
++)
327 fe_txd_unmap(dev
, &ring
->tx_buf
[i
]);
333 dma_free_coherent(dev
,
334 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
340 netdev_reset_queue(priv
->netdev
);
343 static int fe_alloc_tx(struct fe_priv
*priv
)
346 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
348 ring
->tx_free_idx
= 0;
349 ring
->tx_next_idx
= 0;
350 ring
->tx_thresh
= max((unsigned long)ring
->tx_ring_size
>> 2,
353 ring
->tx_buf
= kcalloc(ring
->tx_ring_size
, sizeof(*ring
->tx_buf
),
358 ring
->tx_dma
= dma_alloc_coherent(&priv
->netdev
->dev
,
359 ring
->tx_ring_size
* sizeof(*ring
->tx_dma
),
361 GFP_ATOMIC
| __GFP_ZERO
);
365 for (i
= 0; i
< ring
->tx_ring_size
; i
++) {
366 if (priv
->soc
->tx_dma
)
367 priv
->soc
->tx_dma(&ring
->tx_dma
[i
]);
368 ring
->tx_dma
[i
].txd2
= TX_DMA_DESP2_DEF
;
370 /* make sure that all changes to the dma ring are flushed before we
375 fe_reg_w32(ring
->tx_phys
, FE_REG_TX_BASE_PTR0
);
376 fe_reg_w32(ring
->tx_ring_size
, FE_REG_TX_MAX_CNT0
);
377 fe_reg_w32(0, FE_REG_TX_CTX_IDX0
);
378 fe_reg_w32(FE_PST_DTX_IDX0
, FE_REG_PDMA_RST_CFG
);
386 static int fe_init_dma(struct fe_priv
*priv
)
390 err
= fe_alloc_tx(priv
);
394 err
= fe_alloc_rx(priv
);
401 static void fe_free_dma(struct fe_priv
*priv
)
407 void fe_stats_update(struct fe_priv
*priv
)
409 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
410 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
413 u64_stats_update_begin(&hwstats
->syncp
);
415 if (IS_ENABLED(CONFIG_SOC_MT7621
)) {
416 hwstats
->rx_bytes
+= fe_r32(base
);
417 stats
= fe_r32(base
+ 0x04);
419 hwstats
->rx_bytes
+= (stats
<< 32);
420 hwstats
->rx_packets
+= fe_r32(base
+ 0x08);
421 hwstats
->rx_overflow
+= fe_r32(base
+ 0x10);
422 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x14);
423 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x18);
424 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x1c);
425 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x20);
426 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x24);
427 hwstats
->tx_skip
+= fe_r32(base
+ 0x28);
428 hwstats
->tx_collisions
+= fe_r32(base
+ 0x2c);
429 hwstats
->tx_bytes
+= fe_r32(base
+ 0x30);
430 stats
= fe_r32(base
+ 0x34);
432 hwstats
->tx_bytes
+= (stats
<< 32);
433 hwstats
->tx_packets
+= fe_r32(base
+ 0x38);
435 hwstats
->tx_bytes
+= fe_r32(base
);
436 hwstats
->tx_packets
+= fe_r32(base
+ 0x04);
437 hwstats
->tx_skip
+= fe_r32(base
+ 0x08);
438 hwstats
->tx_collisions
+= fe_r32(base
+ 0x0c);
439 hwstats
->rx_bytes
+= fe_r32(base
+ 0x20);
440 hwstats
->rx_packets
+= fe_r32(base
+ 0x24);
441 hwstats
->rx_overflow
+= fe_r32(base
+ 0x28);
442 hwstats
->rx_fcs_errors
+= fe_r32(base
+ 0x2c);
443 hwstats
->rx_short_errors
+= fe_r32(base
+ 0x30);
444 hwstats
->rx_long_errors
+= fe_r32(base
+ 0x34);
445 hwstats
->rx_checksum_errors
+= fe_r32(base
+ 0x38);
446 hwstats
->rx_flow_control_packets
+= fe_r32(base
+ 0x3c);
449 u64_stats_update_end(&hwstats
->syncp
);
452 static void fe_get_stats64(struct net_device
*dev
,
453 struct rtnl_link_stats64
*storage
)
455 struct fe_priv
*priv
= netdev_priv(dev
);
456 struct fe_hw_stats
*hwstats
= priv
->hw_stats
;
457 unsigned int base
= fe_reg_table
[FE_REG_FE_COUNTER_BASE
];
461 netdev_stats_to_stats64(storage
, &dev
->stats
);
465 if (netif_running(dev
) && netif_device_present(dev
)) {
466 if (spin_trylock(&hwstats
->stats_lock
)) {
467 fe_stats_update(priv
);
468 spin_unlock(&hwstats
->stats_lock
);
473 start
= u64_stats_fetch_begin_irq(&hwstats
->syncp
);
474 storage
->rx_packets
= hwstats
->rx_packets
;
475 storage
->tx_packets
= hwstats
->tx_packets
;
476 storage
->rx_bytes
= hwstats
->rx_bytes
;
477 storage
->tx_bytes
= hwstats
->tx_bytes
;
478 storage
->collisions
= hwstats
->tx_collisions
;
479 storage
->rx_length_errors
= hwstats
->rx_short_errors
+
480 hwstats
->rx_long_errors
;
481 storage
->rx_over_errors
= hwstats
->rx_overflow
;
482 storage
->rx_crc_errors
= hwstats
->rx_fcs_errors
;
483 storage
->rx_errors
= hwstats
->rx_checksum_errors
;
484 storage
->tx_aborted_errors
= hwstats
->tx_skip
;
485 } while (u64_stats_fetch_retry_irq(&hwstats
->syncp
, start
));
487 storage
->tx_errors
= priv
->netdev
->stats
.tx_errors
;
488 storage
->rx_dropped
= priv
->netdev
->stats
.rx_dropped
;
489 storage
->tx_dropped
= priv
->netdev
->stats
.tx_dropped
;
492 static int fe_vlan_rx_add_vid(struct net_device
*dev
,
493 __be16 proto
, u16 vid
)
495 struct fe_priv
*priv
= netdev_priv(dev
);
496 u32 idx
= (vid
& 0xf);
499 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
500 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
503 if (test_bit(idx
, &priv
->vlan_map
)) {
504 netdev_warn(dev
, "disable tx vlan offload\n");
505 dev
->wanted_features
&= ~NETIF_F_HW_VLAN_CTAG_TX
;
506 netdev_update_features(dev
);
508 vlan_cfg
= fe_r32(fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
512 vlan_cfg
|= (vid
<< 16);
514 vlan_cfg
&= 0xffff0000;
517 fe_w32(vlan_cfg
, fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
519 set_bit(idx
, &priv
->vlan_map
);
525 static int fe_vlan_rx_kill_vid(struct net_device
*dev
,
526 __be16 proto
, u16 vid
)
528 struct fe_priv
*priv
= netdev_priv(dev
);
529 u32 idx
= (vid
& 0xf);
531 if (!((fe_reg_table
[FE_REG_FE_DMA_VID_BASE
]) &&
532 (dev
->features
& NETIF_F_HW_VLAN_CTAG_TX
)))
535 clear_bit(idx
, &priv
->vlan_map
);
540 static inline u32
fe_empty_txd(struct fe_tx_ring
*ring
)
543 return (u32
)(ring
->tx_ring_size
-
544 ((ring
->tx_next_idx
- ring
->tx_free_idx
) &
545 (ring
->tx_ring_size
- 1)));
548 static int fe_tx_map_dma(struct sk_buff
*skb
, struct net_device
*dev
,
549 int tx_num
, struct fe_tx_ring
*ring
)
551 struct fe_priv
*priv
= netdev_priv(dev
);
552 struct skb_frag_struct
*frag
;
553 struct fe_tx_dma txd
, *ptxd
;
554 struct fe_tx_buf
*tx_buf
;
555 dma_addr_t mapped_addr
;
556 unsigned int nr_frags
;
558 int i
, j
, k
, frag_size
, frag_map_size
, offset
;
560 tx_buf
= &ring
->tx_buf
[ring
->tx_next_idx
];
561 memset(tx_buf
, 0, sizeof(*tx_buf
));
562 memset(&txd
, 0, sizeof(txd
));
563 nr_frags
= skb_shinfo(skb
)->nr_frags
;
565 /* init tx descriptor */
566 if (priv
->soc
->tx_dma
)
567 priv
->soc
->tx_dma(&txd
);
569 txd
.txd4
= TX_DMA_DESP4_DEF
;
572 /* TX Checksum offload */
573 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
574 txd
.txd4
|= TX_DMA_CHKSUM
;
576 /* VLAN header offload */
577 if (skb_vlan_tag_present(skb
)) {
578 u16 tag
= skb_vlan_tag_get(skb
);
580 if (IS_ENABLED(CONFIG_SOC_MT7621
))
581 txd
.txd4
|= TX_DMA_INS_VLAN_MT7621
| tag
;
583 txd
.txd4
|= TX_DMA_INS_VLAN
|
584 ((tag
>> VLAN_PRIO_SHIFT
) << 4) |
588 /* TSO: fill MSS info in tcp checksum field */
589 if (skb_is_gso(skb
)) {
590 if (skb_cow_head(skb
, 0)) {
591 netif_warn(priv
, tx_err
, dev
,
592 "GSO expand head fail.\n");
595 if (skb_shinfo(skb
)->gso_type
&
596 (SKB_GSO_TCPV4
| SKB_GSO_TCPV6
)) {
597 txd
.txd4
|= TX_DMA_TSO
;
598 tcp_hdr(skb
)->check
= htons(skb_shinfo(skb
)->gso_size
);
602 mapped_addr
= dma_map_single(&dev
->dev
, skb
->data
,
603 skb_headlen(skb
), DMA_TO_DEVICE
);
604 if (unlikely(dma_mapping_error(&dev
->dev
, mapped_addr
)))
606 txd
.txd1
= mapped_addr
;
607 txd
.txd2
= TX_DMA_PLEN0(skb_headlen(skb
));
609 tx_buf
->flags
|= FE_TX_FLAGS_SINGLE0
;
610 dma_unmap_addr_set(tx_buf
, dma_addr0
, mapped_addr
);
611 dma_unmap_len_set(tx_buf
, dma_len0
, skb_headlen(skb
));
614 j
= ring
->tx_next_idx
;
616 for (i
= 0; i
< nr_frags
; i
++) {
618 frag
= &skb_shinfo(skb
)->frags
[i
];
619 frag_size
= skb_frag_size(frag
);
621 while (frag_size
> 0) {
622 frag_map_size
= min(frag_size
, TX_DMA_BUF_LEN
);
623 mapped_addr
= skb_frag_dma_map(&dev
->dev
, frag
, offset
,
626 if (unlikely(dma_mapping_error(&dev
->dev
, mapped_addr
)))
630 j
= NEXT_TX_DESP_IDX(j
);
631 txd
.txd1
= mapped_addr
;
632 txd
.txd2
= TX_DMA_PLEN0(frag_map_size
);
635 tx_buf
= &ring
->tx_buf
[j
];
636 memset(tx_buf
, 0, sizeof(*tx_buf
));
638 tx_buf
->flags
|= FE_TX_FLAGS_PAGE0
;
639 dma_unmap_addr_set(tx_buf
, dma_addr0
,
641 dma_unmap_len_set(tx_buf
, dma_len0
,
644 txd
.txd3
= mapped_addr
;
645 txd
.txd2
|= TX_DMA_PLEN1(frag_map_size
);
647 tx_buf
->skb
= (struct sk_buff
*)DMA_DUMMY_DESC
;
648 tx_buf
->flags
|= FE_TX_FLAGS_PAGE1
;
649 dma_unmap_addr_set(tx_buf
, dma_addr1
,
651 dma_unmap_len_set(tx_buf
, dma_len1
,
654 if (!((i
== (nr_frags
- 1)) &&
655 (frag_map_size
== frag_size
))) {
656 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
657 memset(&txd
, 0, sizeof(txd
));
660 frag_size
-= frag_map_size
;
661 offset
+= frag_map_size
;
666 /* set last segment */
668 txd
.txd2
|= TX_DMA_LS1
;
670 txd
.txd2
|= TX_DMA_LS0
;
671 fe_set_txd(&txd
, &ring
->tx_dma
[j
]);
673 /* store skb to cleanup */
676 netdev_sent_queue(dev
, skb
->len
);
677 skb_tx_timestamp(skb
);
679 ring
->tx_next_idx
= NEXT_TX_DESP_IDX(j
);
680 /* make sure that all changes to the dma ring are flushed before we
684 if (unlikely(fe_empty_txd(ring
) <= ring
->tx_thresh
)) {
685 netif_stop_queue(dev
);
687 if (unlikely(fe_empty_txd(ring
) > ring
->tx_thresh
))
688 netif_wake_queue(dev
);
691 if (netif_xmit_stopped(netdev_get_tx_queue(dev
, 0)) || !skb
->xmit_more
)
692 fe_reg_w32(ring
->tx_next_idx
, FE_REG_TX_CTX_IDX0
);
697 j
= ring
->tx_next_idx
;
698 for (i
= 0; i
< tx_num
; i
++) {
699 ptxd
= &ring
->tx_dma
[j
];
700 tx_buf
= &ring
->tx_buf
[j
];
703 fe_txd_unmap(&dev
->dev
, tx_buf
);
705 ptxd
->txd2
= TX_DMA_DESP2_DEF
;
706 j
= NEXT_TX_DESP_IDX(j
);
708 /* make sure that all changes to the dma ring are flushed before we
717 static inline int fe_skb_padto(struct sk_buff
*skb
, struct fe_priv
*priv
)
723 if (unlikely(skb
->len
< VLAN_ETH_ZLEN
)) {
724 if ((priv
->flags
& FE_FLAG_PADDING_64B
) &&
725 !(priv
->flags
& FE_FLAG_PADDING_BUG
))
728 if (skb_vlan_tag_present(skb
))
730 else if (skb
->protocol
== cpu_to_be16(ETH_P_8021Q
))
732 else if (!(priv
->flags
& FE_FLAG_PADDING_64B
))
737 if (skb
->len
< len
) {
738 ret
= skb_pad(skb
, len
- skb
->len
);
742 skb_set_tail_pointer(skb
, len
);
749 static inline int fe_cal_txd_req(struct sk_buff
*skb
)
752 struct skb_frag_struct
*frag
;
755 if (skb_is_gso(skb
)) {
756 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
757 frag
= &skb_shinfo(skb
)->frags
[i
];
758 nfrags
+= DIV_ROUND_UP(frag
->size
, TX_DMA_BUF_LEN
);
761 nfrags
+= skb_shinfo(skb
)->nr_frags
;
764 return DIV_ROUND_UP(nfrags
, 2);
767 static int fe_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
769 struct fe_priv
*priv
= netdev_priv(dev
);
770 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
771 struct net_device_stats
*stats
= &dev
->stats
;
775 if (fe_skb_padto(skb
, priv
)) {
776 netif_warn(priv
, tx_err
, dev
, "tx padding failed!\n");
780 tx_num
= fe_cal_txd_req(skb
);
781 if (unlikely(fe_empty_txd(ring
) <= tx_num
)) {
782 netif_stop_queue(dev
);
783 netif_err(priv
, tx_queued
, dev
,
784 "Tx Ring full when queue awake!\n");
785 return NETDEV_TX_BUSY
;
788 if (fe_tx_map_dma(skb
, dev
, tx_num
, ring
) < 0) {
792 stats
->tx_bytes
+= len
;
798 static int fe_poll_rx(struct napi_struct
*napi
, int budget
,
799 struct fe_priv
*priv
, u32 rx_intr
)
801 struct net_device
*netdev
= priv
->netdev
;
802 struct net_device_stats
*stats
= &netdev
->stats
;
803 struct fe_soc_data
*soc
= priv
->soc
;
804 struct fe_rx_ring
*ring
= &priv
->rx_ring
;
805 int idx
= ring
->rx_calc_idx
;
809 struct fe_rx_dma
*rxd
, trxd
;
812 if (netdev
->features
& NETIF_F_RXCSUM
)
813 checksum_bit
= soc
->checksum_bit
;
817 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
822 while (done
< budget
) {
826 idx
= NEXT_RX_DESP_IDX(idx
);
827 rxd
= &ring
->rx_dma
[idx
];
828 data
= ring
->rx_data
[idx
];
830 fe_get_rxd(&trxd
, rxd
);
831 if (!(trxd
.rxd2
& RX_DMA_DONE
))
834 /* alloc new buffer */
835 new_data
= netdev_alloc_frag(ring
->frag_size
);
836 if (unlikely(!new_data
)) {
840 dma_addr
= dma_map_single(&netdev
->dev
,
841 new_data
+ NET_SKB_PAD
+ pad
,
844 if (unlikely(dma_mapping_error(&netdev
->dev
, dma_addr
))) {
845 put_page(virt_to_head_page(new_data
));
850 skb
= build_skb(data
, ring
->frag_size
);
851 if (unlikely(!skb
)) {
852 put_page(virt_to_head_page(new_data
));
855 skb_reserve(skb
, NET_SKB_PAD
+ NET_IP_ALIGN
);
857 dma_unmap_single(&netdev
->dev
, trxd
.rxd1
,
858 ring
->rx_buf_size
, DMA_FROM_DEVICE
);
859 pktlen
= RX_DMA_GET_PLEN0(trxd
.rxd2
);
861 skb_put(skb
, pktlen
);
862 if (trxd
.rxd4
& checksum_bit
)
863 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
865 skb_checksum_none_assert(skb
);
866 skb
->protocol
= eth_type_trans(skb
, netdev
);
869 stats
->rx_bytes
+= pktlen
;
871 napi_gro_receive(napi
, skb
);
873 ring
->rx_data
[idx
] = new_data
;
874 rxd
->rxd1
= (unsigned int)dma_addr
;
877 if (priv
->flags
& FE_FLAG_RX_SG_DMA
)
878 rxd
->rxd2
= RX_DMA_PLEN0(ring
->rx_buf_size
);
880 rxd
->rxd2
= RX_DMA_LSO
;
882 ring
->rx_calc_idx
= idx
;
883 /* make sure that all changes to the dma ring are flushed before
887 fe_reg_w32(ring
->rx_calc_idx
, FE_REG_RX_CALC_IDX0
);
892 fe_reg_w32(rx_intr
, FE_REG_FE_INT_STATUS
);
897 static int fe_poll_tx(struct fe_priv
*priv
, int budget
, u32 tx_intr
,
900 struct net_device
*netdev
= priv
->netdev
;
901 struct device
*dev
= &netdev
->dev
;
902 unsigned int bytes_compl
= 0;
904 struct fe_tx_buf
*tx_buf
;
907 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
909 idx
= ring
->tx_free_idx
;
910 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
912 while ((idx
!= hwidx
) && budget
) {
913 tx_buf
= &ring
->tx_buf
[idx
];
919 if (skb
!= (struct sk_buff
*)DMA_DUMMY_DESC
) {
920 bytes_compl
+= skb
->len
;
924 fe_txd_unmap(dev
, tx_buf
);
925 idx
= NEXT_TX_DESP_IDX(idx
);
927 ring
->tx_free_idx
= idx
;
930 /* read hw index again make sure no new tx packet */
931 hwidx
= fe_reg_r32(FE_REG_TX_DTX_IDX0
);
933 fe_reg_w32(tx_intr
, FE_REG_FE_INT_STATUS
);
941 netdev_completed_queue(netdev
, done
, bytes_compl
);
943 if (unlikely(netif_queue_stopped(netdev
) &&
944 (fe_empty_txd(ring
) > ring
->tx_thresh
)))
945 netif_wake_queue(netdev
);
951 static int fe_poll(struct napi_struct
*napi
, int budget
)
953 struct fe_priv
*priv
= container_of(napi
, struct fe_priv
, rx_napi
);
954 struct fe_hw_stats
*hwstat
= priv
->hw_stats
;
955 int tx_done
, rx_done
, tx_again
;
956 u32 status
, fe_status
, status_reg
, mask
;
957 u32 tx_intr
, rx_intr
, status_intr
;
959 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
961 tx_intr
= priv
->soc
->tx_int
;
962 rx_intr
= priv
->soc
->rx_int
;
963 status_intr
= priv
->soc
->status_int
;
968 if (fe_reg_table
[FE_REG_FE_INT_STATUS2
]) {
969 fe_status
= fe_reg_r32(FE_REG_FE_INT_STATUS2
);
970 status_reg
= FE_REG_FE_INT_STATUS2
;
972 status_reg
= FE_REG_FE_INT_STATUS
;
975 if (status
& tx_intr
)
976 tx_done
= fe_poll_tx(priv
, budget
, tx_intr
, &tx_again
);
978 if (status
& rx_intr
)
979 rx_done
= fe_poll_rx(napi
, budget
, priv
, rx_intr
);
981 if (unlikely(fe_status
& status_intr
)) {
982 if (hwstat
&& spin_trylock(&hwstat
->stats_lock
)) {
983 fe_stats_update(priv
);
984 spin_unlock(&hwstat
->stats_lock
);
986 fe_reg_w32(status_intr
, status_reg
);
989 if (unlikely(netif_msg_intr(priv
))) {
990 mask
= fe_reg_r32(FE_REG_FE_INT_ENABLE
);
991 netdev_info(priv
->netdev
,
992 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
993 tx_done
, rx_done
, status
, mask
);
996 if (!tx_again
&& (rx_done
< budget
)) {
997 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
998 if (status
& (tx_intr
| rx_intr
)) {
999 /* let napi poll again */
1004 napi_complete_done(napi
, rx_done
);
1005 fe_int_enable(tx_intr
| rx_intr
);
1014 static void fe_tx_timeout(struct net_device
*dev
)
1016 struct fe_priv
*priv
= netdev_priv(dev
);
1017 struct fe_tx_ring
*ring
= &priv
->tx_ring
;
1019 priv
->netdev
->stats
.tx_errors
++;
1020 netif_err(priv
, tx_err
, dev
,
1021 "transmit timed out\n");
1022 netif_info(priv
, drv
, dev
, "dma_cfg:%08x\n",
1023 fe_reg_r32(FE_REG_PDMA_GLO_CFG
));
1024 netif_info(priv
, drv
, dev
, "tx_ring=%d, "
1025 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1026 0, fe_reg_r32(FE_REG_TX_BASE_PTR0
),
1027 fe_reg_r32(FE_REG_TX_MAX_CNT0
),
1028 fe_reg_r32(FE_REG_TX_CTX_IDX0
),
1029 fe_reg_r32(FE_REG_TX_DTX_IDX0
),
1032 netif_info(priv
, drv
, dev
,
1033 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1034 0, fe_reg_r32(FE_REG_RX_BASE_PTR0
),
1035 fe_reg_r32(FE_REG_RX_MAX_CNT0
),
1036 fe_reg_r32(FE_REG_RX_CALC_IDX0
),
1037 fe_reg_r32(FE_REG_RX_DRX_IDX0
));
1039 if (!test_and_set_bit(FE_FLAG_RESET_PENDING
, priv
->pending_flags
))
1040 schedule_work(&priv
->pending_work
);
1043 static irqreturn_t
fe_handle_irq(int irq
, void *dev
)
1045 struct fe_priv
*priv
= netdev_priv(dev
);
1046 u32 status
, int_mask
;
1048 status
= fe_reg_r32(FE_REG_FE_INT_STATUS
);
1050 if (unlikely(!status
))
1053 int_mask
= (priv
->soc
->rx_int
| priv
->soc
->tx_int
);
1054 if (likely(status
& int_mask
)) {
1055 if (likely(napi_schedule_prep(&priv
->rx_napi
))) {
1056 fe_int_disable(int_mask
);
1057 __napi_schedule(&priv
->rx_napi
);
1060 fe_reg_w32(status
, FE_REG_FE_INT_STATUS
);
1066 #ifdef CONFIG_NET_POLL_CONTROLLER
1067 static void fe_poll_controller(struct net_device
*dev
)
1069 struct fe_priv
*priv
= netdev_priv(dev
);
1070 u32 int_mask
= priv
->soc
->tx_int
| priv
->soc
->rx_int
;
1072 fe_int_disable(int_mask
);
1073 fe_handle_irq(dev
->irq
, dev
);
1074 fe_int_enable(int_mask
);
1078 int fe_set_clock_cycle(struct fe_priv
*priv
)
1080 unsigned long sysclk
= priv
->sysclk
;
1082 sysclk
/= FE_US_CYC_CNT_DIVISOR
;
1083 sysclk
<<= FE_US_CYC_CNT_SHIFT
;
1085 fe_w32((fe_r32(FE_FE_GLO_CFG
) &
1086 ~(FE_US_CYC_CNT_MASK
<< FE_US_CYC_CNT_SHIFT
)) |
1092 void fe_fwd_config(struct fe_priv
*priv
)
1096 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1098 /* disable jumbo frame */
1099 if (priv
->flags
& FE_FLAG_JUMBO_FRAME
)
1100 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1102 /* set unicast/multicast/broadcast frame to cpu */
1105 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1108 static void fe_rxcsum_config(bool enable
)
1111 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) | (FE_GDM1_ICS_EN
|
1112 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1115 fe_w32(fe_r32(FE_GDMA1_FWD_CFG
) & ~(FE_GDM1_ICS_EN
|
1116 FE_GDM1_TCS_EN
| FE_GDM1_UCS_EN
),
1120 static void fe_txcsum_config(bool enable
)
1123 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) | (FE_ICS_GEN_EN
|
1124 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1127 fe_w32(fe_r32(FE_CDMA_CSG_CFG
) & ~(FE_ICS_GEN_EN
|
1128 FE_TCS_GEN_EN
| FE_UCS_GEN_EN
),
1132 void fe_csum_config(struct fe_priv
*priv
)
1134 struct net_device
*dev
= priv_netdev(priv
);
1136 fe_txcsum_config((dev
->features
& NETIF_F_IP_CSUM
));
1137 fe_rxcsum_config((dev
->features
& NETIF_F_RXCSUM
));
1140 static int fe_hw_init(struct net_device
*dev
)
1142 struct fe_priv
*priv
= netdev_priv(dev
);
1145 err
= devm_request_irq(priv
->device
, dev
->irq
, fe_handle_irq
, 0,
1146 dev_name(priv
->device
), dev
);
1150 if (priv
->soc
->set_mac
)
1151 priv
->soc
->set_mac(priv
, dev
->dev_addr
);
1153 fe_hw_set_macaddr(priv
, dev
->dev_addr
);
1155 /* disable delay interrupt */
1156 fe_reg_w32(0, FE_REG_DLY_INT_CFG
);
1158 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1160 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1161 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1162 for (i
= 0; i
< 16; i
+= 2)
1163 fe_w32(((i
+ 1) << 16) + i
,
1164 fe_reg_table
[FE_REG_FE_DMA_VID_BASE
] +
1167 if (priv
->soc
->fwd_config(priv
))
1168 netdev_err(dev
, "unable to get clock\n");
1170 if (fe_reg_table
[FE_REG_FE_RST_GL
]) {
1171 fe_reg_w32(1, FE_REG_FE_RST_GL
);
1172 fe_reg_w32(0, FE_REG_FE_RST_GL
);
1178 static int fe_open(struct net_device
*dev
)
1180 struct fe_priv
*priv
= netdev_priv(dev
);
1181 unsigned long flags
;
1185 err
= fe_init_dma(priv
);
1191 spin_lock_irqsave(&priv
->page_lock
, flags
);
1193 val
= FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
;
1194 if (priv
->flags
& FE_FLAG_RX_2B_OFFSET
)
1195 val
|= FE_RX_2B_OFFSET
;
1196 val
|= priv
->soc
->pdma_glo_cfg
;
1197 fe_reg_w32(val
, FE_REG_PDMA_GLO_CFG
);
1199 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1202 priv
->phy
->start(priv
);
1204 if (priv
->soc
->has_carrier
&& priv
->soc
->has_carrier(priv
))
1205 netif_carrier_on(dev
);
1207 napi_enable(&priv
->rx_napi
);
1208 fe_int_enable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1209 netif_start_queue(dev
);
1214 static int fe_stop(struct net_device
*dev
)
1216 struct fe_priv
*priv
= netdev_priv(dev
);
1217 unsigned long flags
;
1220 netif_tx_disable(dev
);
1221 fe_int_disable(priv
->soc
->tx_int
| priv
->soc
->rx_int
);
1222 napi_disable(&priv
->rx_napi
);
1225 priv
->phy
->stop(priv
);
1227 spin_lock_irqsave(&priv
->page_lock
, flags
);
1229 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1230 ~(FE_TX_WB_DDONE
| FE_RX_DMA_EN
| FE_TX_DMA_EN
),
1231 FE_REG_PDMA_GLO_CFG
);
1232 spin_unlock_irqrestore(&priv
->page_lock
, flags
);
1235 for (i
= 0; i
< 10; i
++) {
1236 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG
) &
1237 (FE_TX_DMA_BUSY
| FE_RX_DMA_BUSY
)) {
1249 static int __init
fe_init(struct net_device
*dev
)
1251 struct fe_priv
*priv
= netdev_priv(dev
);
1252 struct device_node
*port
;
1253 const char *mac_addr
;
1256 priv
->soc
->reset_fe();
1258 if (priv
->soc
->switch_init
)
1259 if (priv
->soc
->switch_init(priv
)) {
1260 netdev_err(dev
, "failed to initialize switch core\n");
1264 mac_addr
= of_get_mac_address(priv
->device
->of_node
);
1266 ether_addr_copy(dev
->dev_addr
, mac_addr
);
1268 /* If the mac address is invalid, use random mac address */
1269 if (!is_valid_ether_addr(dev
->dev_addr
)) {
1270 random_ether_addr(dev
->dev_addr
);
1271 dev_err(priv
->device
, "generated random MAC address %pM\n",
1275 err
= fe_mdio_init(priv
);
1279 if (priv
->soc
->port_init
)
1280 for_each_child_of_node(priv
->device
->of_node
, port
)
1281 if (of_device_is_compatible(port
, "mediatek,eth-port") &&
1282 of_device_is_available(port
))
1283 priv
->soc
->port_init(priv
, port
);
1286 err
= priv
->phy
->connect(priv
);
1288 goto err_phy_disconnect
;
1291 err
= fe_hw_init(dev
);
1293 goto err_phy_disconnect
;
1295 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && priv
->soc
->switch_config
)
1296 priv
->soc
->switch_config(priv
);
1302 priv
->phy
->disconnect(priv
);
1303 fe_mdio_cleanup(priv
);
1308 static void fe_uninit(struct net_device
*dev
)
1310 struct fe_priv
*priv
= netdev_priv(dev
);
1313 priv
->phy
->disconnect(priv
);
1314 fe_mdio_cleanup(priv
);
1316 fe_reg_w32(0, FE_REG_FE_INT_ENABLE
);
1317 free_irq(dev
->irq
, dev
);
1320 static int fe_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1322 struct fe_priv
*priv
= netdev_priv(dev
);
1329 return phy_ethtool_ioctl(priv
->phy_dev
,
1330 (void *) ifr
->ifr_data
);
1334 return phy_mii_ioctl(priv
->phy_dev
, ifr
, cmd
);
1342 static int fe_change_mtu(struct net_device
*dev
, int new_mtu
)
1344 struct fe_priv
*priv
= netdev_priv(dev
);
1345 int frag_size
, old_mtu
;
1348 if (!(priv
->flags
& FE_FLAG_JUMBO_FRAME
))
1349 return eth_change_mtu(dev
, new_mtu
);
1351 if (IS_ENABLED(CONFIG_SOC_MT7621
))
1355 frag_size
= fe_max_frag_size(new_mtu
);
1356 if (new_mtu
< 68 || frag_size
> PAGE_SIZE
)
1362 /* return early if the buffer sizes will not change */
1363 if (old_mtu
<= ETH_DATA_LEN
&& new_mtu
<= ETH_DATA_LEN
)
1365 if (old_mtu
> ETH_DATA_LEN
&& new_mtu
> ETH_DATA_LEN
)
1368 if (new_mtu
<= ETH_DATA_LEN
)
1369 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1371 priv
->rx_ring
.frag_size
= PAGE_SIZE
;
1372 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1374 if (!netif_running(dev
))
1378 if (!IS_ENABLED(CONFIG_SOC_MT7621
)) {
1379 fwd_cfg
= fe_r32(FE_GDMA1_FWD_CFG
);
1380 if (new_mtu
<= ETH_DATA_LEN
) {
1381 fwd_cfg
&= ~FE_GDM1_JMB_EN
;
1383 fwd_cfg
&= ~(FE_GDM1_JMB_LEN_MASK
<< FE_GDM1_JMB_LEN_SHIFT
);
1384 fwd_cfg
|= (DIV_ROUND_UP(frag_size
, 1024) <<
1385 FE_GDM1_JMB_LEN_SHIFT
) | FE_GDM1_JMB_EN
;
1387 fe_w32(fwd_cfg
, FE_GDMA1_FWD_CFG
);
1390 return fe_open(dev
);
1393 static const struct net_device_ops fe_netdev_ops
= {
1394 .ndo_init
= fe_init
,
1395 .ndo_uninit
= fe_uninit
,
1396 .ndo_open
= fe_open
,
1397 .ndo_stop
= fe_stop
,
1398 .ndo_start_xmit
= fe_start_xmit
,
1399 .ndo_set_mac_address
= fe_set_mac_address
,
1400 .ndo_validate_addr
= eth_validate_addr
,
1401 .ndo_do_ioctl
= fe_do_ioctl
,
1402 .ndo_change_mtu
= fe_change_mtu
,
1403 .ndo_tx_timeout
= fe_tx_timeout
,
1404 .ndo_get_stats64
= fe_get_stats64
,
1405 .ndo_vlan_rx_add_vid
= fe_vlan_rx_add_vid
,
1406 .ndo_vlan_rx_kill_vid
= fe_vlan_rx_kill_vid
,
1407 #ifdef CONFIG_NET_POLL_CONTROLLER
1408 .ndo_poll_controller
= fe_poll_controller
,
1412 static void fe_reset_pending(struct fe_priv
*priv
)
1414 struct net_device
*dev
= priv
->netdev
;
1422 netif_alert(priv
, ifup
, dev
,
1423 "Driver up/down cycle failed, closing device.\n");
1429 static const struct fe_work_t fe_work
[] = {
1430 {FE_FLAG_RESET_PENDING
, fe_reset_pending
},
1433 static void fe_pending_work(struct work_struct
*work
)
1435 struct fe_priv
*priv
= container_of(work
, struct fe_priv
, pending_work
);
1439 for (i
= 0; i
< ARRAY_SIZE(fe_work
); i
++) {
1440 pending
= test_and_clear_bit(fe_work
[i
].bitnr
,
1441 priv
->pending_flags
);
1443 fe_work
[i
].action(priv
);
1447 static int fe_probe(struct platform_device
*pdev
)
1449 struct resource
*res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1450 const struct of_device_id
*match
;
1451 struct fe_soc_data
*soc
;
1452 struct net_device
*netdev
;
1453 struct fe_priv
*priv
;
1455 int err
, napi_weight
;
1457 device_reset(&pdev
->dev
);
1459 match
= of_match_device(of_fe_match
, &pdev
->dev
);
1460 soc
= (struct fe_soc_data
*)match
->data
;
1463 fe_reg_table
= soc
->reg_table
;
1465 soc
->reg_table
= fe_reg_table
;
1467 fe_base
= devm_ioremap_resource(&pdev
->dev
, res
);
1469 err
= -EADDRNOTAVAIL
;
1473 netdev
= alloc_etherdev(sizeof(*priv
));
1475 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
1480 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
1481 netdev
->netdev_ops
= &fe_netdev_ops
;
1482 netdev
->base_addr
= (unsigned long)fe_base
;
1484 netdev
->irq
= platform_get_irq(pdev
, 0);
1485 if (netdev
->irq
< 0) {
1486 dev_err(&pdev
->dev
, "no IRQ resource found\n");
1492 soc
->init_data(soc
, netdev
);
1493 netdev
->vlan_features
= netdev
->hw_features
& ~NETIF_F_HW_VLAN_CTAG_TX
;
1494 netdev
->features
|= netdev
->hw_features
;
1496 /* fake rx vlan filter func. to support tx vlan offload func */
1497 if (fe_reg_table
[FE_REG_FE_DMA_VID_BASE
])
1498 netdev
->features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
1500 priv
= netdev_priv(netdev
);
1501 spin_lock_init(&priv
->page_lock
);
1502 if (fe_reg_table
[FE_REG_FE_COUNTER_BASE
]) {
1503 priv
->hw_stats
= kzalloc(sizeof(*priv
->hw_stats
), GFP_KERNEL
);
1504 if (!priv
->hw_stats
) {
1508 spin_lock_init(&priv
->hw_stats
->stats_lock
);
1511 sysclk
= devm_clk_get(&pdev
->dev
, NULL
);
1512 if (!IS_ERR(sysclk
)) {
1513 priv
->sysclk
= clk_get_rate(sysclk
);
1514 } else if ((priv
->flags
& FE_FLAG_CALIBRATE_CLK
)) {
1515 dev_err(&pdev
->dev
, "this soc needs a clk for calibration\n");
1520 priv
->switch_np
= of_parse_phandle(pdev
->dev
.of_node
, "mediatek,switch", 0);
1521 if ((priv
->flags
& FE_FLAG_HAS_SWITCH
) && !priv
->switch_np
) {
1522 dev_err(&pdev
->dev
, "failed to read switch phandle\n");
1527 priv
->netdev
= netdev
;
1528 priv
->device
= &pdev
->dev
;
1530 priv
->msg_enable
= netif_msg_init(fe_msg_level
, FE_DEFAULT_MSG_ENABLE
);
1531 priv
->rx_ring
.frag_size
= fe_max_frag_size(ETH_DATA_LEN
);
1532 priv
->rx_ring
.rx_buf_size
= fe_max_buf_size(priv
->rx_ring
.frag_size
);
1533 priv
->tx_ring
.tx_ring_size
= NUM_DMA_DESC
;
1534 priv
->rx_ring
.rx_ring_size
= NUM_DMA_DESC
;
1535 INIT_WORK(&priv
->pending_work
, fe_pending_work
);
1538 if (priv
->flags
& FE_FLAG_NAPI_WEIGHT
) {
1540 priv
->tx_ring
.tx_ring_size
*= 4;
1541 priv
->rx_ring
.rx_ring_size
*= 4;
1543 netif_napi_add(netdev
, &priv
->rx_napi
, fe_poll
, napi_weight
);
1544 fe_set_ethtool_ops(netdev
);
1546 err
= register_netdev(netdev
);
1548 dev_err(&pdev
->dev
, "error bringing up device\n");
1552 platform_set_drvdata(pdev
, netdev
);
1554 netif_info(priv
, probe
, netdev
, "mediatek frame engine at 0x%08lx, irq %d\n",
1555 netdev
->base_addr
, netdev
->irq
);
1560 free_netdev(netdev
);
1562 devm_iounmap(&pdev
->dev
, fe_base
);
1567 static int fe_remove(struct platform_device
*pdev
)
1569 struct net_device
*dev
= platform_get_drvdata(pdev
);
1570 struct fe_priv
*priv
= netdev_priv(dev
);
1572 netif_napi_del(&priv
->rx_napi
);
1573 kfree(priv
->hw_stats
);
1575 cancel_work_sync(&priv
->pending_work
);
1577 unregister_netdev(dev
);
1579 platform_set_drvdata(pdev
, NULL
);
1584 static struct platform_driver fe_driver
= {
1586 .remove
= fe_remove
,
1588 .name
= "mtk_soc_eth",
1589 .owner
= THIS_MODULE
,
1590 .of_match_table
= of_fe_match
,
1594 module_platform_driver(fe_driver
);
1596 MODULE_LICENSE("GPL");
1597 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1598 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1599 MODULE_VERSION(MTK_FE_DRV_VERSION
);