ramips: preliminary support for 4.14
[openwrt/openwrt.git] / target / linux / ramips / files-4.14 / drivers / net / ethernet / mtk / mtk_eth_soc.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/init.h>
20 #include <linux/skbuff.h>
21 #include <linux/etherdevice.h>
22 #include <linux/ethtool.h>
23 #include <linux/platform_device.h>
24 #include <linux/of_device.h>
25 #include <linux/clk.h>
26 #include <linux/of_net.h>
27 #include <linux/of_mdio.h>
28 #include <linux/if_vlan.h>
29 #include <linux/reset.h>
30 #include <linux/tcp.h>
31 #include <linux/io.h>
32 #include <linux/bug.h>
33
34 #include <asm/mach-ralink/ralink_regs.h>
35
36 #include "mtk_eth_soc.h"
37 #include "mdio.h"
38 #include "ethtool.h"
39
40 #define MAX_RX_LENGTH 1536
41 #define FE_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
42 #define FE_RX_HLEN (NET_SKB_PAD + FE_RX_ETH_HLEN + NET_IP_ALIGN)
43 #define DMA_DUMMY_DESC 0xffffffff
44 #define FE_DEFAULT_MSG_ENABLE \
45 (NETIF_MSG_DRV | \
46 NETIF_MSG_PROBE | \
47 NETIF_MSG_LINK | \
48 NETIF_MSG_TIMER | \
49 NETIF_MSG_IFDOWN | \
50 NETIF_MSG_IFUP | \
51 NETIF_MSG_RX_ERR | \
52 NETIF_MSG_TX_ERR)
53
54 #define TX_DMA_DESP2_DEF (TX_DMA_LS0 | TX_DMA_DONE)
55 #define TX_DMA_DESP4_DEF (TX_DMA_QN(3) | TX_DMA_PN(1))
56 #define NEXT_TX_DESP_IDX(X) (((X) + 1) & (ring->tx_ring_size - 1))
57 #define NEXT_RX_DESP_IDX(X) (((X) + 1) & (ring->rx_ring_size - 1))
58
59 #define SYSC_REG_RSTCTRL 0x34
60
61 static int fe_msg_level = -1;
62 module_param_named(msg_level, fe_msg_level, int, 0);
63 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
64
65 static const u16 fe_reg_table_default[FE_REG_COUNT] = {
66 [FE_REG_PDMA_GLO_CFG] = FE_PDMA_GLO_CFG,
67 [FE_REG_PDMA_RST_CFG] = FE_PDMA_RST_CFG,
68 [FE_REG_DLY_INT_CFG] = FE_DLY_INT_CFG,
69 [FE_REG_TX_BASE_PTR0] = FE_TX_BASE_PTR0,
70 [FE_REG_TX_MAX_CNT0] = FE_TX_MAX_CNT0,
71 [FE_REG_TX_CTX_IDX0] = FE_TX_CTX_IDX0,
72 [FE_REG_TX_DTX_IDX0] = FE_TX_DTX_IDX0,
73 [FE_REG_RX_BASE_PTR0] = FE_RX_BASE_PTR0,
74 [FE_REG_RX_MAX_CNT0] = FE_RX_MAX_CNT0,
75 [FE_REG_RX_CALC_IDX0] = FE_RX_CALC_IDX0,
76 [FE_REG_RX_DRX_IDX0] = FE_RX_DRX_IDX0,
77 [FE_REG_FE_INT_ENABLE] = FE_FE_INT_ENABLE,
78 [FE_REG_FE_INT_STATUS] = FE_FE_INT_STATUS,
79 [FE_REG_FE_DMA_VID_BASE] = FE_DMA_VID0,
80 [FE_REG_FE_COUNTER_BASE] = FE_GDMA1_TX_GBCNT,
81 [FE_REG_FE_RST_GL] = FE_FE_RST_GL,
82 };
83
84 static const u16 *fe_reg_table = fe_reg_table_default;
85
86 struct fe_work_t {
87 int bitnr;
88 void (*action)(struct fe_priv *);
89 };
90
91 static void __iomem *fe_base;
92
93 void fe_w32(u32 val, unsigned reg)
94 {
95 __raw_writel(val, fe_base + reg);
96 }
97
98 u32 fe_r32(unsigned reg)
99 {
100 return __raw_readl(fe_base + reg);
101 }
102
103 void fe_reg_w32(u32 val, enum fe_reg reg)
104 {
105 fe_w32(val, fe_reg_table[reg]);
106 }
107
108 u32 fe_reg_r32(enum fe_reg reg)
109 {
110 return fe_r32(fe_reg_table[reg]);
111 }
112
113 void fe_reset(u32 reset_bits)
114 {
115 u32 t;
116
117 t = rt_sysc_r32(SYSC_REG_RSTCTRL);
118 t |= reset_bits;
119 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
120 usleep_range(10, 20);
121
122 t &= ~reset_bits;
123 rt_sysc_w32(t, SYSC_REG_RSTCTRL);
124 usleep_range(10, 20);
125 }
126
127 static inline void fe_int_disable(u32 mask)
128 {
129 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) & ~mask,
130 FE_REG_FE_INT_ENABLE);
131 /* flush write */
132 fe_reg_r32(FE_REG_FE_INT_ENABLE);
133 }
134
135 static inline void fe_int_enable(u32 mask)
136 {
137 fe_reg_w32(fe_reg_r32(FE_REG_FE_INT_ENABLE) | mask,
138 FE_REG_FE_INT_ENABLE);
139 /* flush write */
140 fe_reg_r32(FE_REG_FE_INT_ENABLE);
141 }
142
143 static inline void fe_hw_set_macaddr(struct fe_priv *priv, unsigned char *mac)
144 {
145 unsigned long flags;
146
147 spin_lock_irqsave(&priv->page_lock, flags);
148 fe_w32((mac[0] << 8) | mac[1], FE_GDMA1_MAC_ADRH);
149 fe_w32((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5],
150 FE_GDMA1_MAC_ADRL);
151 spin_unlock_irqrestore(&priv->page_lock, flags);
152 }
153
154 static int fe_set_mac_address(struct net_device *dev, void *p)
155 {
156 int ret = eth_mac_addr(dev, p);
157
158 if (!ret) {
159 struct fe_priv *priv = netdev_priv(dev);
160
161 if (priv->soc->set_mac)
162 priv->soc->set_mac(priv, dev->dev_addr);
163 else
164 fe_hw_set_macaddr(priv, p);
165 }
166
167 return ret;
168 }
169
170 static inline int fe_max_frag_size(int mtu)
171 {
172 /* make sure buf_size will be at least MAX_RX_LENGTH */
173 if (mtu + FE_RX_ETH_HLEN < MAX_RX_LENGTH)
174 mtu = MAX_RX_LENGTH - FE_RX_ETH_HLEN;
175
176 return SKB_DATA_ALIGN(FE_RX_HLEN + mtu) +
177 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
178 }
179
180 static inline int fe_max_buf_size(int frag_size)
181 {
182 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
183 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
184
185 BUG_ON(buf_size < MAX_RX_LENGTH);
186 return buf_size;
187 }
188
189 static inline void fe_get_rxd(struct fe_rx_dma *rxd, struct fe_rx_dma *dma_rxd)
190 {
191 rxd->rxd1 = dma_rxd->rxd1;
192 rxd->rxd2 = dma_rxd->rxd2;
193 rxd->rxd3 = dma_rxd->rxd3;
194 rxd->rxd4 = dma_rxd->rxd4;
195 }
196
197 static inline void fe_set_txd(struct fe_tx_dma *txd, struct fe_tx_dma *dma_txd)
198 {
199 dma_txd->txd1 = txd->txd1;
200 dma_txd->txd3 = txd->txd3;
201 dma_txd->txd4 = txd->txd4;
202 /* clean dma done flag last */
203 dma_txd->txd2 = txd->txd2;
204 }
205
206 static void fe_clean_rx(struct fe_priv *priv)
207 {
208 int i;
209 struct fe_rx_ring *ring = &priv->rx_ring;
210
211 if (ring->rx_data) {
212 for (i = 0; i < ring->rx_ring_size; i++)
213 if (ring->rx_data[i]) {
214 if (ring->rx_dma && ring->rx_dma[i].rxd1)
215 dma_unmap_single(&priv->netdev->dev,
216 ring->rx_dma[i].rxd1,
217 ring->rx_buf_size,
218 DMA_FROM_DEVICE);
219 put_page(virt_to_head_page(ring->rx_data[i]));
220 }
221
222 kfree(ring->rx_data);
223 ring->rx_data = NULL;
224 }
225
226 if (ring->rx_dma) {
227 dma_free_coherent(&priv->netdev->dev,
228 ring->rx_ring_size * sizeof(*ring->rx_dma),
229 ring->rx_dma,
230 ring->rx_phys);
231 ring->rx_dma = NULL;
232 }
233 }
234
235 static int fe_alloc_rx(struct fe_priv *priv)
236 {
237 struct net_device *netdev = priv->netdev;
238 struct fe_rx_ring *ring = &priv->rx_ring;
239 int i, pad;
240
241 ring->rx_data = kcalloc(ring->rx_ring_size, sizeof(*ring->rx_data),
242 GFP_KERNEL);
243 if (!ring->rx_data)
244 goto no_rx_mem;
245
246 for (i = 0; i < ring->rx_ring_size; i++) {
247 ring->rx_data[i] = netdev_alloc_frag(ring->frag_size);
248 if (!ring->rx_data[i])
249 goto no_rx_mem;
250 }
251
252 ring->rx_dma = dma_alloc_coherent(&netdev->dev,
253 ring->rx_ring_size * sizeof(*ring->rx_dma),
254 &ring->rx_phys,
255 GFP_ATOMIC | __GFP_ZERO);
256 if (!ring->rx_dma)
257 goto no_rx_mem;
258
259 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
260 pad = 0;
261 else
262 pad = NET_IP_ALIGN;
263 for (i = 0; i < ring->rx_ring_size; i++) {
264 dma_addr_t dma_addr = dma_map_single(&netdev->dev,
265 ring->rx_data[i] + NET_SKB_PAD + pad,
266 ring->rx_buf_size,
267 DMA_FROM_DEVICE);
268 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr)))
269 goto no_rx_mem;
270 ring->rx_dma[i].rxd1 = (unsigned int)dma_addr;
271
272 if (priv->flags & FE_FLAG_RX_SG_DMA)
273 ring->rx_dma[i].rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
274 else
275 ring->rx_dma[i].rxd2 = RX_DMA_LSO;
276 }
277 ring->rx_calc_idx = ring->rx_ring_size - 1;
278 /* make sure that all changes to the dma ring are flushed before we
279 * continue
280 */
281 wmb();
282
283 fe_reg_w32(ring->rx_phys, FE_REG_RX_BASE_PTR0);
284 fe_reg_w32(ring->rx_ring_size, FE_REG_RX_MAX_CNT0);
285 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
286 fe_reg_w32(FE_PST_DRX_IDX0, FE_REG_PDMA_RST_CFG);
287
288 return 0;
289
290 no_rx_mem:
291 return -ENOMEM;
292 }
293
294 static void fe_txd_unmap(struct device *dev, struct fe_tx_buf *tx_buf)
295 {
296 if (tx_buf->flags & FE_TX_FLAGS_SINGLE0) {
297 dma_unmap_single(dev,
298 dma_unmap_addr(tx_buf, dma_addr0),
299 dma_unmap_len(tx_buf, dma_len0),
300 DMA_TO_DEVICE);
301 } else if (tx_buf->flags & FE_TX_FLAGS_PAGE0) {
302 dma_unmap_page(dev,
303 dma_unmap_addr(tx_buf, dma_addr0),
304 dma_unmap_len(tx_buf, dma_len0),
305 DMA_TO_DEVICE);
306 }
307 if (tx_buf->flags & FE_TX_FLAGS_PAGE1)
308 dma_unmap_page(dev,
309 dma_unmap_addr(tx_buf, dma_addr1),
310 dma_unmap_len(tx_buf, dma_len1),
311 DMA_TO_DEVICE);
312
313 tx_buf->flags = 0;
314 if (tx_buf->skb && (tx_buf->skb != (struct sk_buff *)DMA_DUMMY_DESC))
315 dev_kfree_skb_any(tx_buf->skb);
316 tx_buf->skb = NULL;
317 }
318
319 static void fe_clean_tx(struct fe_priv *priv)
320 {
321 int i;
322 struct device *dev = &priv->netdev->dev;
323 struct fe_tx_ring *ring = &priv->tx_ring;
324
325 if (ring->tx_buf) {
326 for (i = 0; i < ring->tx_ring_size; i++)
327 fe_txd_unmap(dev, &ring->tx_buf[i]);
328 kfree(ring->tx_buf);
329 ring->tx_buf = NULL;
330 }
331
332 if (ring->tx_dma) {
333 dma_free_coherent(dev,
334 ring->tx_ring_size * sizeof(*ring->tx_dma),
335 ring->tx_dma,
336 ring->tx_phys);
337 ring->tx_dma = NULL;
338 }
339
340 netdev_reset_queue(priv->netdev);
341 }
342
343 static int fe_alloc_tx(struct fe_priv *priv)
344 {
345 int i;
346 struct fe_tx_ring *ring = &priv->tx_ring;
347
348 ring->tx_free_idx = 0;
349 ring->tx_next_idx = 0;
350 ring->tx_thresh = max((unsigned long)ring->tx_ring_size >> 2,
351 MAX_SKB_FRAGS);
352
353 ring->tx_buf = kcalloc(ring->tx_ring_size, sizeof(*ring->tx_buf),
354 GFP_KERNEL);
355 if (!ring->tx_buf)
356 goto no_tx_mem;
357
358 ring->tx_dma = dma_alloc_coherent(&priv->netdev->dev,
359 ring->tx_ring_size * sizeof(*ring->tx_dma),
360 &ring->tx_phys,
361 GFP_ATOMIC | __GFP_ZERO);
362 if (!ring->tx_dma)
363 goto no_tx_mem;
364
365 for (i = 0; i < ring->tx_ring_size; i++) {
366 if (priv->soc->tx_dma)
367 priv->soc->tx_dma(&ring->tx_dma[i]);
368 ring->tx_dma[i].txd2 = TX_DMA_DESP2_DEF;
369 }
370 /* make sure that all changes to the dma ring are flushed before we
371 * continue
372 */
373 wmb();
374
375 fe_reg_w32(ring->tx_phys, FE_REG_TX_BASE_PTR0);
376 fe_reg_w32(ring->tx_ring_size, FE_REG_TX_MAX_CNT0);
377 fe_reg_w32(0, FE_REG_TX_CTX_IDX0);
378 fe_reg_w32(FE_PST_DTX_IDX0, FE_REG_PDMA_RST_CFG);
379
380 return 0;
381
382 no_tx_mem:
383 return -ENOMEM;
384 }
385
386 static int fe_init_dma(struct fe_priv *priv)
387 {
388 int err;
389
390 err = fe_alloc_tx(priv);
391 if (err)
392 return err;
393
394 err = fe_alloc_rx(priv);
395 if (err)
396 return err;
397
398 return 0;
399 }
400
401 static void fe_free_dma(struct fe_priv *priv)
402 {
403 fe_clean_tx(priv);
404 fe_clean_rx(priv);
405 }
406
407 void fe_stats_update(struct fe_priv *priv)
408 {
409 struct fe_hw_stats *hwstats = priv->hw_stats;
410 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
411 u64 stats;
412
413 u64_stats_update_begin(&hwstats->syncp);
414
415 if (IS_ENABLED(CONFIG_SOC_MT7621)) {
416 hwstats->rx_bytes += fe_r32(base);
417 stats = fe_r32(base + 0x04);
418 if (stats)
419 hwstats->rx_bytes += (stats << 32);
420 hwstats->rx_packets += fe_r32(base + 0x08);
421 hwstats->rx_overflow += fe_r32(base + 0x10);
422 hwstats->rx_fcs_errors += fe_r32(base + 0x14);
423 hwstats->rx_short_errors += fe_r32(base + 0x18);
424 hwstats->rx_long_errors += fe_r32(base + 0x1c);
425 hwstats->rx_checksum_errors += fe_r32(base + 0x20);
426 hwstats->rx_flow_control_packets += fe_r32(base + 0x24);
427 hwstats->tx_skip += fe_r32(base + 0x28);
428 hwstats->tx_collisions += fe_r32(base + 0x2c);
429 hwstats->tx_bytes += fe_r32(base + 0x30);
430 stats = fe_r32(base + 0x34);
431 if (stats)
432 hwstats->tx_bytes += (stats << 32);
433 hwstats->tx_packets += fe_r32(base + 0x38);
434 } else {
435 hwstats->tx_bytes += fe_r32(base);
436 hwstats->tx_packets += fe_r32(base + 0x04);
437 hwstats->tx_skip += fe_r32(base + 0x08);
438 hwstats->tx_collisions += fe_r32(base + 0x0c);
439 hwstats->rx_bytes += fe_r32(base + 0x20);
440 hwstats->rx_packets += fe_r32(base + 0x24);
441 hwstats->rx_overflow += fe_r32(base + 0x28);
442 hwstats->rx_fcs_errors += fe_r32(base + 0x2c);
443 hwstats->rx_short_errors += fe_r32(base + 0x30);
444 hwstats->rx_long_errors += fe_r32(base + 0x34);
445 hwstats->rx_checksum_errors += fe_r32(base + 0x38);
446 hwstats->rx_flow_control_packets += fe_r32(base + 0x3c);
447 }
448
449 u64_stats_update_end(&hwstats->syncp);
450 }
451
452 static void fe_get_stats64(struct net_device *dev,
453 struct rtnl_link_stats64 *storage)
454 {
455 struct fe_priv *priv = netdev_priv(dev);
456 struct fe_hw_stats *hwstats = priv->hw_stats;
457 unsigned int base = fe_reg_table[FE_REG_FE_COUNTER_BASE];
458 unsigned int start;
459
460 if (!base) {
461 netdev_stats_to_stats64(storage, &dev->stats);
462 return;
463 }
464
465 if (netif_running(dev) && netif_device_present(dev)) {
466 if (spin_trylock(&hwstats->stats_lock)) {
467 fe_stats_update(priv);
468 spin_unlock(&hwstats->stats_lock);
469 }
470 }
471
472 do {
473 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
474 storage->rx_packets = hwstats->rx_packets;
475 storage->tx_packets = hwstats->tx_packets;
476 storage->rx_bytes = hwstats->rx_bytes;
477 storage->tx_bytes = hwstats->tx_bytes;
478 storage->collisions = hwstats->tx_collisions;
479 storage->rx_length_errors = hwstats->rx_short_errors +
480 hwstats->rx_long_errors;
481 storage->rx_over_errors = hwstats->rx_overflow;
482 storage->rx_crc_errors = hwstats->rx_fcs_errors;
483 storage->rx_errors = hwstats->rx_checksum_errors;
484 storage->tx_aborted_errors = hwstats->tx_skip;
485 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
486
487 storage->tx_errors = priv->netdev->stats.tx_errors;
488 storage->rx_dropped = priv->netdev->stats.rx_dropped;
489 storage->tx_dropped = priv->netdev->stats.tx_dropped;
490 }
491
492 static int fe_vlan_rx_add_vid(struct net_device *dev,
493 __be16 proto, u16 vid)
494 {
495 struct fe_priv *priv = netdev_priv(dev);
496 u32 idx = (vid & 0xf);
497 u32 vlan_cfg;
498
499 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
500 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
501 return 0;
502
503 if (test_bit(idx, &priv->vlan_map)) {
504 netdev_warn(dev, "disable tx vlan offload\n");
505 dev->wanted_features &= ~NETIF_F_HW_VLAN_CTAG_TX;
506 netdev_update_features(dev);
507 } else {
508 vlan_cfg = fe_r32(fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
509 ((idx >> 1) << 2));
510 if (idx & 0x1) {
511 vlan_cfg &= 0xffff;
512 vlan_cfg |= (vid << 16);
513 } else {
514 vlan_cfg &= 0xffff0000;
515 vlan_cfg |= vid;
516 }
517 fe_w32(vlan_cfg, fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
518 ((idx >> 1) << 2));
519 set_bit(idx, &priv->vlan_map);
520 }
521
522 return 0;
523 }
524
525 static int fe_vlan_rx_kill_vid(struct net_device *dev,
526 __be16 proto, u16 vid)
527 {
528 struct fe_priv *priv = netdev_priv(dev);
529 u32 idx = (vid & 0xf);
530
531 if (!((fe_reg_table[FE_REG_FE_DMA_VID_BASE]) &&
532 (dev->features & NETIF_F_HW_VLAN_CTAG_TX)))
533 return 0;
534
535 clear_bit(idx, &priv->vlan_map);
536
537 return 0;
538 }
539
540 static inline u32 fe_empty_txd(struct fe_tx_ring *ring)
541 {
542 barrier();
543 return (u32)(ring->tx_ring_size -
544 ((ring->tx_next_idx - ring->tx_free_idx) &
545 (ring->tx_ring_size - 1)));
546 }
547
548 static int fe_tx_map_dma(struct sk_buff *skb, struct net_device *dev,
549 int tx_num, struct fe_tx_ring *ring)
550 {
551 struct fe_priv *priv = netdev_priv(dev);
552 struct skb_frag_struct *frag;
553 struct fe_tx_dma txd, *ptxd;
554 struct fe_tx_buf *tx_buf;
555 dma_addr_t mapped_addr;
556 unsigned int nr_frags;
557 u32 def_txd4;
558 int i, j, k, frag_size, frag_map_size, offset;
559
560 tx_buf = &ring->tx_buf[ring->tx_next_idx];
561 memset(tx_buf, 0, sizeof(*tx_buf));
562 memset(&txd, 0, sizeof(txd));
563 nr_frags = skb_shinfo(skb)->nr_frags;
564
565 /* init tx descriptor */
566 if (priv->soc->tx_dma)
567 priv->soc->tx_dma(&txd);
568 else
569 txd.txd4 = TX_DMA_DESP4_DEF;
570 def_txd4 = txd.txd4;
571
572 /* TX Checksum offload */
573 if (skb->ip_summed == CHECKSUM_PARTIAL)
574 txd.txd4 |= TX_DMA_CHKSUM;
575
576 /* VLAN header offload */
577 if (skb_vlan_tag_present(skb)) {
578 u16 tag = skb_vlan_tag_get(skb);
579
580 if (IS_ENABLED(CONFIG_SOC_MT7621))
581 txd.txd4 |= TX_DMA_INS_VLAN_MT7621 | tag;
582 else
583 txd.txd4 |= TX_DMA_INS_VLAN |
584 ((tag >> VLAN_PRIO_SHIFT) << 4) |
585 (tag & 0xF);
586 }
587
588 /* TSO: fill MSS info in tcp checksum field */
589 if (skb_is_gso(skb)) {
590 if (skb_cow_head(skb, 0)) {
591 netif_warn(priv, tx_err, dev,
592 "GSO expand head fail.\n");
593 goto err_out;
594 }
595 if (skb_shinfo(skb)->gso_type &
596 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
597 txd.txd4 |= TX_DMA_TSO;
598 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
599 }
600 }
601
602 mapped_addr = dma_map_single(&dev->dev, skb->data,
603 skb_headlen(skb), DMA_TO_DEVICE);
604 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
605 goto err_out;
606 txd.txd1 = mapped_addr;
607 txd.txd2 = TX_DMA_PLEN0(skb_headlen(skb));
608
609 tx_buf->flags |= FE_TX_FLAGS_SINGLE0;
610 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
611 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
612
613 /* TX SG offload */
614 j = ring->tx_next_idx;
615 k = 0;
616 for (i = 0; i < nr_frags; i++) {
617 offset = 0;
618 frag = &skb_shinfo(skb)->frags[i];
619 frag_size = skb_frag_size(frag);
620
621 while (frag_size > 0) {
622 frag_map_size = min(frag_size, TX_DMA_BUF_LEN);
623 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
624 frag_map_size,
625 DMA_TO_DEVICE);
626 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
627 goto err_dma;
628
629 if (k & 0x1) {
630 j = NEXT_TX_DESP_IDX(j);
631 txd.txd1 = mapped_addr;
632 txd.txd2 = TX_DMA_PLEN0(frag_map_size);
633 txd.txd4 = def_txd4;
634
635 tx_buf = &ring->tx_buf[j];
636 memset(tx_buf, 0, sizeof(*tx_buf));
637
638 tx_buf->flags |= FE_TX_FLAGS_PAGE0;
639 dma_unmap_addr_set(tx_buf, dma_addr0,
640 mapped_addr);
641 dma_unmap_len_set(tx_buf, dma_len0,
642 frag_map_size);
643 } else {
644 txd.txd3 = mapped_addr;
645 txd.txd2 |= TX_DMA_PLEN1(frag_map_size);
646
647 tx_buf->skb = (struct sk_buff *)DMA_DUMMY_DESC;
648 tx_buf->flags |= FE_TX_FLAGS_PAGE1;
649 dma_unmap_addr_set(tx_buf, dma_addr1,
650 mapped_addr);
651 dma_unmap_len_set(tx_buf, dma_len1,
652 frag_map_size);
653
654 if (!((i == (nr_frags - 1)) &&
655 (frag_map_size == frag_size))) {
656 fe_set_txd(&txd, &ring->tx_dma[j]);
657 memset(&txd, 0, sizeof(txd));
658 }
659 }
660 frag_size -= frag_map_size;
661 offset += frag_map_size;
662 k++;
663 }
664 }
665
666 /* set last segment */
667 if (k & 0x1)
668 txd.txd2 |= TX_DMA_LS1;
669 else
670 txd.txd2 |= TX_DMA_LS0;
671 fe_set_txd(&txd, &ring->tx_dma[j]);
672
673 /* store skb to cleanup */
674 tx_buf->skb = skb;
675
676 netdev_sent_queue(dev, skb->len);
677 skb_tx_timestamp(skb);
678
679 ring->tx_next_idx = NEXT_TX_DESP_IDX(j);
680 /* make sure that all changes to the dma ring are flushed before we
681 * continue
682 */
683 wmb();
684 if (unlikely(fe_empty_txd(ring) <= ring->tx_thresh)) {
685 netif_stop_queue(dev);
686 smp_mb();
687 if (unlikely(fe_empty_txd(ring) > ring->tx_thresh))
688 netif_wake_queue(dev);
689 }
690
691 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
692 fe_reg_w32(ring->tx_next_idx, FE_REG_TX_CTX_IDX0);
693
694 return 0;
695
696 err_dma:
697 j = ring->tx_next_idx;
698 for (i = 0; i < tx_num; i++) {
699 ptxd = &ring->tx_dma[j];
700 tx_buf = &ring->tx_buf[j];
701
702 /* unmap dma */
703 fe_txd_unmap(&dev->dev, tx_buf);
704
705 ptxd->txd2 = TX_DMA_DESP2_DEF;
706 j = NEXT_TX_DESP_IDX(j);
707 }
708 /* make sure that all changes to the dma ring are flushed before we
709 * continue
710 */
711 wmb();
712
713 err_out:
714 return -1;
715 }
716
717 static inline int fe_skb_padto(struct sk_buff *skb, struct fe_priv *priv)
718 {
719 unsigned int len;
720 int ret;
721
722 ret = 0;
723 if (unlikely(skb->len < VLAN_ETH_ZLEN)) {
724 if ((priv->flags & FE_FLAG_PADDING_64B) &&
725 !(priv->flags & FE_FLAG_PADDING_BUG))
726 return ret;
727
728 if (skb_vlan_tag_present(skb))
729 len = ETH_ZLEN;
730 else if (skb->protocol == cpu_to_be16(ETH_P_8021Q))
731 len = VLAN_ETH_ZLEN;
732 else if (!(priv->flags & FE_FLAG_PADDING_64B))
733 len = ETH_ZLEN;
734 else
735 return ret;
736
737 if (skb->len < len) {
738 ret = skb_pad(skb, len - skb->len);
739 if (ret < 0)
740 return ret;
741 skb->len = len;
742 skb_set_tail_pointer(skb, len);
743 }
744 }
745
746 return ret;
747 }
748
749 static inline int fe_cal_txd_req(struct sk_buff *skb)
750 {
751 int i, nfrags;
752 struct skb_frag_struct *frag;
753
754 nfrags = 1;
755 if (skb_is_gso(skb)) {
756 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
757 frag = &skb_shinfo(skb)->frags[i];
758 nfrags += DIV_ROUND_UP(frag->size, TX_DMA_BUF_LEN);
759 }
760 } else {
761 nfrags += skb_shinfo(skb)->nr_frags;
762 }
763
764 return DIV_ROUND_UP(nfrags, 2);
765 }
766
767 static int fe_start_xmit(struct sk_buff *skb, struct net_device *dev)
768 {
769 struct fe_priv *priv = netdev_priv(dev);
770 struct fe_tx_ring *ring = &priv->tx_ring;
771 struct net_device_stats *stats = &dev->stats;
772 int tx_num;
773 int len = skb->len;
774
775 if (fe_skb_padto(skb, priv)) {
776 netif_warn(priv, tx_err, dev, "tx padding failed!\n");
777 return NETDEV_TX_OK;
778 }
779
780 tx_num = fe_cal_txd_req(skb);
781 if (unlikely(fe_empty_txd(ring) <= tx_num)) {
782 netif_stop_queue(dev);
783 netif_err(priv, tx_queued, dev,
784 "Tx Ring full when queue awake!\n");
785 return NETDEV_TX_BUSY;
786 }
787
788 if (fe_tx_map_dma(skb, dev, tx_num, ring) < 0) {
789 stats->tx_dropped++;
790 } else {
791 stats->tx_packets++;
792 stats->tx_bytes += len;
793 }
794
795 return NETDEV_TX_OK;
796 }
797
798 static int fe_poll_rx(struct napi_struct *napi, int budget,
799 struct fe_priv *priv, u32 rx_intr)
800 {
801 struct net_device *netdev = priv->netdev;
802 struct net_device_stats *stats = &netdev->stats;
803 struct fe_soc_data *soc = priv->soc;
804 struct fe_rx_ring *ring = &priv->rx_ring;
805 int idx = ring->rx_calc_idx;
806 u32 checksum_bit;
807 struct sk_buff *skb;
808 u8 *data, *new_data;
809 struct fe_rx_dma *rxd, trxd;
810 int done = 0, pad;
811
812 if (netdev->features & NETIF_F_RXCSUM)
813 checksum_bit = soc->checksum_bit;
814 else
815 checksum_bit = 0;
816
817 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
818 pad = 0;
819 else
820 pad = NET_IP_ALIGN;
821
822 while (done < budget) {
823 unsigned int pktlen;
824 dma_addr_t dma_addr;
825
826 idx = NEXT_RX_DESP_IDX(idx);
827 rxd = &ring->rx_dma[idx];
828 data = ring->rx_data[idx];
829
830 fe_get_rxd(&trxd, rxd);
831 if (!(trxd.rxd2 & RX_DMA_DONE))
832 break;
833
834 /* alloc new buffer */
835 new_data = netdev_alloc_frag(ring->frag_size);
836 if (unlikely(!new_data)) {
837 stats->rx_dropped++;
838 goto release_desc;
839 }
840 dma_addr = dma_map_single(&netdev->dev,
841 new_data + NET_SKB_PAD + pad,
842 ring->rx_buf_size,
843 DMA_FROM_DEVICE);
844 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
845 put_page(virt_to_head_page(new_data));
846 goto release_desc;
847 }
848
849 /* receive data */
850 skb = build_skb(data, ring->frag_size);
851 if (unlikely(!skb)) {
852 put_page(virt_to_head_page(new_data));
853 goto release_desc;
854 }
855 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
856
857 dma_unmap_single(&netdev->dev, trxd.rxd1,
858 ring->rx_buf_size, DMA_FROM_DEVICE);
859 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
860 skb->dev = netdev;
861 skb_put(skb, pktlen);
862 if (trxd.rxd4 & checksum_bit)
863 skb->ip_summed = CHECKSUM_UNNECESSARY;
864 else
865 skb_checksum_none_assert(skb);
866 skb->protocol = eth_type_trans(skb, netdev);
867
868 stats->rx_packets++;
869 stats->rx_bytes += pktlen;
870
871 napi_gro_receive(napi, skb);
872
873 ring->rx_data[idx] = new_data;
874 rxd->rxd1 = (unsigned int)dma_addr;
875
876 release_desc:
877 if (priv->flags & FE_FLAG_RX_SG_DMA)
878 rxd->rxd2 = RX_DMA_PLEN0(ring->rx_buf_size);
879 else
880 rxd->rxd2 = RX_DMA_LSO;
881
882 ring->rx_calc_idx = idx;
883 /* make sure that all changes to the dma ring are flushed before
884 * we continue
885 */
886 wmb();
887 fe_reg_w32(ring->rx_calc_idx, FE_REG_RX_CALC_IDX0);
888 done++;
889 }
890
891 if (done < budget)
892 fe_reg_w32(rx_intr, FE_REG_FE_INT_STATUS);
893
894 return done;
895 }
896
897 static int fe_poll_tx(struct fe_priv *priv, int budget, u32 tx_intr,
898 int *tx_again)
899 {
900 struct net_device *netdev = priv->netdev;
901 struct device *dev = &netdev->dev;
902 unsigned int bytes_compl = 0;
903 struct sk_buff *skb;
904 struct fe_tx_buf *tx_buf;
905 int done = 0;
906 u32 idx, hwidx;
907 struct fe_tx_ring *ring = &priv->tx_ring;
908
909 idx = ring->tx_free_idx;
910 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
911
912 while ((idx != hwidx) && budget) {
913 tx_buf = &ring->tx_buf[idx];
914 skb = tx_buf->skb;
915
916 if (!skb)
917 break;
918
919 if (skb != (struct sk_buff *)DMA_DUMMY_DESC) {
920 bytes_compl += skb->len;
921 done++;
922 budget--;
923 }
924 fe_txd_unmap(dev, tx_buf);
925 idx = NEXT_TX_DESP_IDX(idx);
926 }
927 ring->tx_free_idx = idx;
928
929 if (idx == hwidx) {
930 /* read hw index again make sure no new tx packet */
931 hwidx = fe_reg_r32(FE_REG_TX_DTX_IDX0);
932 if (idx == hwidx)
933 fe_reg_w32(tx_intr, FE_REG_FE_INT_STATUS);
934 else
935 *tx_again = 1;
936 } else {
937 *tx_again = 1;
938 }
939
940 if (done) {
941 netdev_completed_queue(netdev, done, bytes_compl);
942 smp_mb();
943 if (unlikely(netif_queue_stopped(netdev) &&
944 (fe_empty_txd(ring) > ring->tx_thresh)))
945 netif_wake_queue(netdev);
946 }
947
948 return done;
949 }
950
951 static int fe_poll(struct napi_struct *napi, int budget)
952 {
953 struct fe_priv *priv = container_of(napi, struct fe_priv, rx_napi);
954 struct fe_hw_stats *hwstat = priv->hw_stats;
955 int tx_done, rx_done, tx_again;
956 u32 status, fe_status, status_reg, mask;
957 u32 tx_intr, rx_intr, status_intr;
958
959 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
960 fe_status = status;
961 tx_intr = priv->soc->tx_int;
962 rx_intr = priv->soc->rx_int;
963 status_intr = priv->soc->status_int;
964 tx_done = 0;
965 rx_done = 0;
966 tx_again = 0;
967
968 if (fe_reg_table[FE_REG_FE_INT_STATUS2]) {
969 fe_status = fe_reg_r32(FE_REG_FE_INT_STATUS2);
970 status_reg = FE_REG_FE_INT_STATUS2;
971 } else {
972 status_reg = FE_REG_FE_INT_STATUS;
973 }
974
975 if (status & tx_intr)
976 tx_done = fe_poll_tx(priv, budget, tx_intr, &tx_again);
977
978 if (status & rx_intr)
979 rx_done = fe_poll_rx(napi, budget, priv, rx_intr);
980
981 if (unlikely(fe_status & status_intr)) {
982 if (hwstat && spin_trylock(&hwstat->stats_lock)) {
983 fe_stats_update(priv);
984 spin_unlock(&hwstat->stats_lock);
985 }
986 fe_reg_w32(status_intr, status_reg);
987 }
988
989 if (unlikely(netif_msg_intr(priv))) {
990 mask = fe_reg_r32(FE_REG_FE_INT_ENABLE);
991 netdev_info(priv->netdev,
992 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
993 tx_done, rx_done, status, mask);
994 }
995
996 if (!tx_again && (rx_done < budget)) {
997 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
998 if (status & (tx_intr | rx_intr)) {
999 /* let napi poll again */
1000 rx_done = budget;
1001 goto poll_again;
1002 }
1003
1004 napi_complete_done(napi, rx_done);
1005 fe_int_enable(tx_intr | rx_intr);
1006 } else {
1007 rx_done = budget;
1008 }
1009
1010 poll_again:
1011 return rx_done;
1012 }
1013
1014 static void fe_tx_timeout(struct net_device *dev)
1015 {
1016 struct fe_priv *priv = netdev_priv(dev);
1017 struct fe_tx_ring *ring = &priv->tx_ring;
1018
1019 priv->netdev->stats.tx_errors++;
1020 netif_err(priv, tx_err, dev,
1021 "transmit timed out\n");
1022 netif_info(priv, drv, dev, "dma_cfg:%08x\n",
1023 fe_reg_r32(FE_REG_PDMA_GLO_CFG));
1024 netif_info(priv, drv, dev, "tx_ring=%d, "
1025 "base=%08x, max=%u, ctx=%u, dtx=%u, fdx=%hu, next=%hu\n",
1026 0, fe_reg_r32(FE_REG_TX_BASE_PTR0),
1027 fe_reg_r32(FE_REG_TX_MAX_CNT0),
1028 fe_reg_r32(FE_REG_TX_CTX_IDX0),
1029 fe_reg_r32(FE_REG_TX_DTX_IDX0),
1030 ring->tx_free_idx,
1031 ring->tx_next_idx);
1032 netif_info(priv, drv, dev,
1033 "rx_ring=%d, base=%08x, max=%u, calc=%u, drx=%u\n",
1034 0, fe_reg_r32(FE_REG_RX_BASE_PTR0),
1035 fe_reg_r32(FE_REG_RX_MAX_CNT0),
1036 fe_reg_r32(FE_REG_RX_CALC_IDX0),
1037 fe_reg_r32(FE_REG_RX_DRX_IDX0));
1038
1039 if (!test_and_set_bit(FE_FLAG_RESET_PENDING, priv->pending_flags))
1040 schedule_work(&priv->pending_work);
1041 }
1042
1043 static irqreturn_t fe_handle_irq(int irq, void *dev)
1044 {
1045 struct fe_priv *priv = netdev_priv(dev);
1046 u32 status, int_mask;
1047
1048 status = fe_reg_r32(FE_REG_FE_INT_STATUS);
1049
1050 if (unlikely(!status))
1051 return IRQ_NONE;
1052
1053 int_mask = (priv->soc->rx_int | priv->soc->tx_int);
1054 if (likely(status & int_mask)) {
1055 if (likely(napi_schedule_prep(&priv->rx_napi))) {
1056 fe_int_disable(int_mask);
1057 __napi_schedule(&priv->rx_napi);
1058 }
1059 } else {
1060 fe_reg_w32(status, FE_REG_FE_INT_STATUS);
1061 }
1062
1063 return IRQ_HANDLED;
1064 }
1065
1066 #ifdef CONFIG_NET_POLL_CONTROLLER
1067 static void fe_poll_controller(struct net_device *dev)
1068 {
1069 struct fe_priv *priv = netdev_priv(dev);
1070 u32 int_mask = priv->soc->tx_int | priv->soc->rx_int;
1071
1072 fe_int_disable(int_mask);
1073 fe_handle_irq(dev->irq, dev);
1074 fe_int_enable(int_mask);
1075 }
1076 #endif
1077
1078 int fe_set_clock_cycle(struct fe_priv *priv)
1079 {
1080 unsigned long sysclk = priv->sysclk;
1081
1082 sysclk /= FE_US_CYC_CNT_DIVISOR;
1083 sysclk <<= FE_US_CYC_CNT_SHIFT;
1084
1085 fe_w32((fe_r32(FE_FE_GLO_CFG) &
1086 ~(FE_US_CYC_CNT_MASK << FE_US_CYC_CNT_SHIFT)) |
1087 sysclk,
1088 FE_FE_GLO_CFG);
1089 return 0;
1090 }
1091
1092 void fe_fwd_config(struct fe_priv *priv)
1093 {
1094 u32 fwd_cfg;
1095
1096 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1097
1098 /* disable jumbo frame */
1099 if (priv->flags & FE_FLAG_JUMBO_FRAME)
1100 fwd_cfg &= ~FE_GDM1_JMB_EN;
1101
1102 /* set unicast/multicast/broadcast frame to cpu */
1103 fwd_cfg &= ~0xffff;
1104
1105 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1106 }
1107
1108 static void fe_rxcsum_config(bool enable)
1109 {
1110 if (enable)
1111 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) | (FE_GDM1_ICS_EN |
1112 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1113 FE_GDMA1_FWD_CFG);
1114 else
1115 fe_w32(fe_r32(FE_GDMA1_FWD_CFG) & ~(FE_GDM1_ICS_EN |
1116 FE_GDM1_TCS_EN | FE_GDM1_UCS_EN),
1117 FE_GDMA1_FWD_CFG);
1118 }
1119
1120 static void fe_txcsum_config(bool enable)
1121 {
1122 if (enable)
1123 fe_w32(fe_r32(FE_CDMA_CSG_CFG) | (FE_ICS_GEN_EN |
1124 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1125 FE_CDMA_CSG_CFG);
1126 else
1127 fe_w32(fe_r32(FE_CDMA_CSG_CFG) & ~(FE_ICS_GEN_EN |
1128 FE_TCS_GEN_EN | FE_UCS_GEN_EN),
1129 FE_CDMA_CSG_CFG);
1130 }
1131
1132 void fe_csum_config(struct fe_priv *priv)
1133 {
1134 struct net_device *dev = priv_netdev(priv);
1135
1136 fe_txcsum_config((dev->features & NETIF_F_IP_CSUM));
1137 fe_rxcsum_config((dev->features & NETIF_F_RXCSUM));
1138 }
1139
1140 static int fe_hw_init(struct net_device *dev)
1141 {
1142 struct fe_priv *priv = netdev_priv(dev);
1143 int i, err;
1144
1145 err = devm_request_irq(priv->device, dev->irq, fe_handle_irq, 0,
1146 dev_name(priv->device), dev);
1147 if (err)
1148 return err;
1149
1150 if (priv->soc->set_mac)
1151 priv->soc->set_mac(priv, dev->dev_addr);
1152 else
1153 fe_hw_set_macaddr(priv, dev->dev_addr);
1154
1155 /* disable delay interrupt */
1156 fe_reg_w32(0, FE_REG_DLY_INT_CFG);
1157
1158 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1159
1160 /* frame engine will push VLAN tag regarding to VIDX feild in Tx desc */
1161 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1162 for (i = 0; i < 16; i += 2)
1163 fe_w32(((i + 1) << 16) + i,
1164 fe_reg_table[FE_REG_FE_DMA_VID_BASE] +
1165 (i * 2));
1166
1167 if (priv->soc->fwd_config(priv))
1168 netdev_err(dev, "unable to get clock\n");
1169
1170 if (fe_reg_table[FE_REG_FE_RST_GL]) {
1171 fe_reg_w32(1, FE_REG_FE_RST_GL);
1172 fe_reg_w32(0, FE_REG_FE_RST_GL);
1173 }
1174
1175 return 0;
1176 }
1177
1178 static int fe_open(struct net_device *dev)
1179 {
1180 struct fe_priv *priv = netdev_priv(dev);
1181 unsigned long flags;
1182 u32 val;
1183 int err;
1184
1185 err = fe_init_dma(priv);
1186 if (err) {
1187 fe_free_dma(priv);
1188 return err;
1189 }
1190
1191 spin_lock_irqsave(&priv->page_lock, flags);
1192
1193 val = FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN;
1194 if (priv->flags & FE_FLAG_RX_2B_OFFSET)
1195 val |= FE_RX_2B_OFFSET;
1196 val |= priv->soc->pdma_glo_cfg;
1197 fe_reg_w32(val, FE_REG_PDMA_GLO_CFG);
1198
1199 spin_unlock_irqrestore(&priv->page_lock, flags);
1200
1201 if (priv->phy)
1202 priv->phy->start(priv);
1203
1204 if (priv->soc->has_carrier && priv->soc->has_carrier(priv))
1205 netif_carrier_on(dev);
1206
1207 napi_enable(&priv->rx_napi);
1208 fe_int_enable(priv->soc->tx_int | priv->soc->rx_int);
1209 netif_start_queue(dev);
1210
1211 return 0;
1212 }
1213
1214 static int fe_stop(struct net_device *dev)
1215 {
1216 struct fe_priv *priv = netdev_priv(dev);
1217 unsigned long flags;
1218 int i;
1219
1220 netif_tx_disable(dev);
1221 fe_int_disable(priv->soc->tx_int | priv->soc->rx_int);
1222 napi_disable(&priv->rx_napi);
1223
1224 if (priv->phy)
1225 priv->phy->stop(priv);
1226
1227 spin_lock_irqsave(&priv->page_lock, flags);
1228
1229 fe_reg_w32(fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1230 ~(FE_TX_WB_DDONE | FE_RX_DMA_EN | FE_TX_DMA_EN),
1231 FE_REG_PDMA_GLO_CFG);
1232 spin_unlock_irqrestore(&priv->page_lock, flags);
1233
1234 /* wait dma stop */
1235 for (i = 0; i < 10; i++) {
1236 if (fe_reg_r32(FE_REG_PDMA_GLO_CFG) &
1237 (FE_TX_DMA_BUSY | FE_RX_DMA_BUSY)) {
1238 msleep(20);
1239 continue;
1240 }
1241 break;
1242 }
1243
1244 fe_free_dma(priv);
1245
1246 return 0;
1247 }
1248
1249 static int __init fe_init(struct net_device *dev)
1250 {
1251 struct fe_priv *priv = netdev_priv(dev);
1252 struct device_node *port;
1253 const char *mac_addr;
1254 int err;
1255
1256 priv->soc->reset_fe();
1257
1258 if (priv->soc->switch_init)
1259 if (priv->soc->switch_init(priv)) {
1260 netdev_err(dev, "failed to initialize switch core\n");
1261 return -ENODEV;
1262 }
1263
1264 mac_addr = of_get_mac_address(priv->device->of_node);
1265 if (mac_addr)
1266 ether_addr_copy(dev->dev_addr, mac_addr);
1267
1268 /* If the mac address is invalid, use random mac address */
1269 if (!is_valid_ether_addr(dev->dev_addr)) {
1270 random_ether_addr(dev->dev_addr);
1271 dev_err(priv->device, "generated random MAC address %pM\n",
1272 dev->dev_addr);
1273 }
1274
1275 err = fe_mdio_init(priv);
1276 if (err)
1277 return err;
1278
1279 if (priv->soc->port_init)
1280 for_each_child_of_node(priv->device->of_node, port)
1281 if (of_device_is_compatible(port, "mediatek,eth-port") &&
1282 of_device_is_available(port))
1283 priv->soc->port_init(priv, port);
1284
1285 if (priv->phy) {
1286 err = priv->phy->connect(priv);
1287 if (err)
1288 goto err_phy_disconnect;
1289 }
1290
1291 err = fe_hw_init(dev);
1292 if (err)
1293 goto err_phy_disconnect;
1294
1295 if ((priv->flags & FE_FLAG_HAS_SWITCH) && priv->soc->switch_config)
1296 priv->soc->switch_config(priv);
1297
1298 return 0;
1299
1300 err_phy_disconnect:
1301 if (priv->phy)
1302 priv->phy->disconnect(priv);
1303 fe_mdio_cleanup(priv);
1304
1305 return err;
1306 }
1307
1308 static void fe_uninit(struct net_device *dev)
1309 {
1310 struct fe_priv *priv = netdev_priv(dev);
1311
1312 if (priv->phy)
1313 priv->phy->disconnect(priv);
1314 fe_mdio_cleanup(priv);
1315
1316 fe_reg_w32(0, FE_REG_FE_INT_ENABLE);
1317 free_irq(dev->irq, dev);
1318 }
1319
1320 static int fe_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1321 {
1322 struct fe_priv *priv = netdev_priv(dev);
1323
1324 if (!priv->phy_dev)
1325 return -ENODEV;
1326
1327 switch (cmd) {
1328 case SIOCETHTOOL:
1329 return phy_ethtool_ioctl(priv->phy_dev,
1330 (void *) ifr->ifr_data);
1331 case SIOCGMIIPHY:
1332 case SIOCGMIIREG:
1333 case SIOCSMIIREG:
1334 return phy_mii_ioctl(priv->phy_dev, ifr, cmd);
1335 default:
1336 break;
1337 }
1338
1339 return -EOPNOTSUPP;
1340 }
1341
1342 static int fe_change_mtu(struct net_device *dev, int new_mtu)
1343 {
1344 struct fe_priv *priv = netdev_priv(dev);
1345 int frag_size, old_mtu;
1346 u32 fwd_cfg;
1347
1348 if (!(priv->flags & FE_FLAG_JUMBO_FRAME))
1349 return eth_change_mtu(dev, new_mtu);
1350
1351 if (IS_ENABLED(CONFIG_SOC_MT7621))
1352 if (new_mtu > 2048)
1353 return -EINVAL;
1354
1355 frag_size = fe_max_frag_size(new_mtu);
1356 if (new_mtu < 68 || frag_size > PAGE_SIZE)
1357 return -EINVAL;
1358
1359 old_mtu = dev->mtu;
1360 dev->mtu = new_mtu;
1361
1362 /* return early if the buffer sizes will not change */
1363 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
1364 return 0;
1365 if (old_mtu > ETH_DATA_LEN && new_mtu > ETH_DATA_LEN)
1366 return 0;
1367
1368 if (new_mtu <= ETH_DATA_LEN)
1369 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1370 else
1371 priv->rx_ring.frag_size = PAGE_SIZE;
1372 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1373
1374 if (!netif_running(dev))
1375 return 0;
1376
1377 fe_stop(dev);
1378 if (!IS_ENABLED(CONFIG_SOC_MT7621)) {
1379 fwd_cfg = fe_r32(FE_GDMA1_FWD_CFG);
1380 if (new_mtu <= ETH_DATA_LEN) {
1381 fwd_cfg &= ~FE_GDM1_JMB_EN;
1382 } else {
1383 fwd_cfg &= ~(FE_GDM1_JMB_LEN_MASK << FE_GDM1_JMB_LEN_SHIFT);
1384 fwd_cfg |= (DIV_ROUND_UP(frag_size, 1024) <<
1385 FE_GDM1_JMB_LEN_SHIFT) | FE_GDM1_JMB_EN;
1386 }
1387 fe_w32(fwd_cfg, FE_GDMA1_FWD_CFG);
1388 }
1389
1390 return fe_open(dev);
1391 }
1392
1393 static const struct net_device_ops fe_netdev_ops = {
1394 .ndo_init = fe_init,
1395 .ndo_uninit = fe_uninit,
1396 .ndo_open = fe_open,
1397 .ndo_stop = fe_stop,
1398 .ndo_start_xmit = fe_start_xmit,
1399 .ndo_set_mac_address = fe_set_mac_address,
1400 .ndo_validate_addr = eth_validate_addr,
1401 .ndo_do_ioctl = fe_do_ioctl,
1402 .ndo_change_mtu = fe_change_mtu,
1403 .ndo_tx_timeout = fe_tx_timeout,
1404 .ndo_get_stats64 = fe_get_stats64,
1405 .ndo_vlan_rx_add_vid = fe_vlan_rx_add_vid,
1406 .ndo_vlan_rx_kill_vid = fe_vlan_rx_kill_vid,
1407 #ifdef CONFIG_NET_POLL_CONTROLLER
1408 .ndo_poll_controller = fe_poll_controller,
1409 #endif
1410 };
1411
1412 static void fe_reset_pending(struct fe_priv *priv)
1413 {
1414 struct net_device *dev = priv->netdev;
1415 int err;
1416
1417 rtnl_lock();
1418 fe_stop(dev);
1419
1420 err = fe_open(dev);
1421 if (err) {
1422 netif_alert(priv, ifup, dev,
1423 "Driver up/down cycle failed, closing device.\n");
1424 dev_close(dev);
1425 }
1426 rtnl_unlock();
1427 }
1428
1429 static const struct fe_work_t fe_work[] = {
1430 {FE_FLAG_RESET_PENDING, fe_reset_pending},
1431 };
1432
1433 static void fe_pending_work(struct work_struct *work)
1434 {
1435 struct fe_priv *priv = container_of(work, struct fe_priv, pending_work);
1436 int i;
1437 bool pending;
1438
1439 for (i = 0; i < ARRAY_SIZE(fe_work); i++) {
1440 pending = test_and_clear_bit(fe_work[i].bitnr,
1441 priv->pending_flags);
1442 if (pending)
1443 fe_work[i].action(priv);
1444 }
1445 }
1446
1447 static int fe_probe(struct platform_device *pdev)
1448 {
1449 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1450 const struct of_device_id *match;
1451 struct fe_soc_data *soc;
1452 struct net_device *netdev;
1453 struct fe_priv *priv;
1454 struct clk *sysclk;
1455 int err, napi_weight;
1456
1457 device_reset(&pdev->dev);
1458
1459 match = of_match_device(of_fe_match, &pdev->dev);
1460 soc = (struct fe_soc_data *)match->data;
1461
1462 if (soc->reg_table)
1463 fe_reg_table = soc->reg_table;
1464 else
1465 soc->reg_table = fe_reg_table;
1466
1467 fe_base = devm_ioremap_resource(&pdev->dev, res);
1468 if (!fe_base) {
1469 err = -EADDRNOTAVAIL;
1470 goto err_out;
1471 }
1472
1473 netdev = alloc_etherdev(sizeof(*priv));
1474 if (!netdev) {
1475 dev_err(&pdev->dev, "alloc_etherdev failed\n");
1476 err = -ENOMEM;
1477 goto err_iounmap;
1478 }
1479
1480 SET_NETDEV_DEV(netdev, &pdev->dev);
1481 netdev->netdev_ops = &fe_netdev_ops;
1482 netdev->base_addr = (unsigned long)fe_base;
1483
1484 netdev->irq = platform_get_irq(pdev, 0);
1485 if (netdev->irq < 0) {
1486 dev_err(&pdev->dev, "no IRQ resource found\n");
1487 err = -ENXIO;
1488 goto err_free_dev;
1489 }
1490
1491 if (soc->init_data)
1492 soc->init_data(soc, netdev);
1493 netdev->vlan_features = netdev->hw_features & ~NETIF_F_HW_VLAN_CTAG_TX;
1494 netdev->features |= netdev->hw_features;
1495
1496 /* fake rx vlan filter func. to support tx vlan offload func */
1497 if (fe_reg_table[FE_REG_FE_DMA_VID_BASE])
1498 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
1499
1500 priv = netdev_priv(netdev);
1501 spin_lock_init(&priv->page_lock);
1502 if (fe_reg_table[FE_REG_FE_COUNTER_BASE]) {
1503 priv->hw_stats = kzalloc(sizeof(*priv->hw_stats), GFP_KERNEL);
1504 if (!priv->hw_stats) {
1505 err = -ENOMEM;
1506 goto err_free_dev;
1507 }
1508 spin_lock_init(&priv->hw_stats->stats_lock);
1509 }
1510
1511 sysclk = devm_clk_get(&pdev->dev, NULL);
1512 if (!IS_ERR(sysclk)) {
1513 priv->sysclk = clk_get_rate(sysclk);
1514 } else if ((priv->flags & FE_FLAG_CALIBRATE_CLK)) {
1515 dev_err(&pdev->dev, "this soc needs a clk for calibration\n");
1516 err = -ENXIO;
1517 goto err_free_dev;
1518 }
1519
1520 priv->switch_np = of_parse_phandle(pdev->dev.of_node, "mediatek,switch", 0);
1521 if ((priv->flags & FE_FLAG_HAS_SWITCH) && !priv->switch_np) {
1522 dev_err(&pdev->dev, "failed to read switch phandle\n");
1523 err = -ENODEV;
1524 goto err_free_dev;
1525 }
1526
1527 priv->netdev = netdev;
1528 priv->device = &pdev->dev;
1529 priv->soc = soc;
1530 priv->msg_enable = netif_msg_init(fe_msg_level, FE_DEFAULT_MSG_ENABLE);
1531 priv->rx_ring.frag_size = fe_max_frag_size(ETH_DATA_LEN);
1532 priv->rx_ring.rx_buf_size = fe_max_buf_size(priv->rx_ring.frag_size);
1533 priv->tx_ring.tx_ring_size = NUM_DMA_DESC;
1534 priv->rx_ring.rx_ring_size = NUM_DMA_DESC;
1535 INIT_WORK(&priv->pending_work, fe_pending_work);
1536
1537 napi_weight = 16;
1538 if (priv->flags & FE_FLAG_NAPI_WEIGHT) {
1539 napi_weight *= 4;
1540 priv->tx_ring.tx_ring_size *= 4;
1541 priv->rx_ring.rx_ring_size *= 4;
1542 }
1543 netif_napi_add(netdev, &priv->rx_napi, fe_poll, napi_weight);
1544 fe_set_ethtool_ops(netdev);
1545
1546 err = register_netdev(netdev);
1547 if (err) {
1548 dev_err(&pdev->dev, "error bringing up device\n");
1549 goto err_free_dev;
1550 }
1551
1552 platform_set_drvdata(pdev, netdev);
1553
1554 netif_info(priv, probe, netdev, "mediatek frame engine at 0x%08lx, irq %d\n",
1555 netdev->base_addr, netdev->irq);
1556
1557 return 0;
1558
1559 err_free_dev:
1560 free_netdev(netdev);
1561 err_iounmap:
1562 devm_iounmap(&pdev->dev, fe_base);
1563 err_out:
1564 return err;
1565 }
1566
1567 static int fe_remove(struct platform_device *pdev)
1568 {
1569 struct net_device *dev = platform_get_drvdata(pdev);
1570 struct fe_priv *priv = netdev_priv(dev);
1571
1572 netif_napi_del(&priv->rx_napi);
1573 kfree(priv->hw_stats);
1574
1575 cancel_work_sync(&priv->pending_work);
1576
1577 unregister_netdev(dev);
1578 free_netdev(dev);
1579 platform_set_drvdata(pdev, NULL);
1580
1581 return 0;
1582 }
1583
1584 static struct platform_driver fe_driver = {
1585 .probe = fe_probe,
1586 .remove = fe_remove,
1587 .driver = {
1588 .name = "mtk_soc_eth",
1589 .owner = THIS_MODULE,
1590 .of_match_table = of_fe_match,
1591 },
1592 };
1593
1594 module_platform_driver(fe_driver);
1595
1596 MODULE_LICENSE("GPL");
1597 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1598 MODULE_DESCRIPTION("Ethernet driver for Ralink SoC");
1599 MODULE_VERSION(MTK_FE_DRV_VERSION);