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ralink: pinctrl fix for non muxed pins
[openwrt/openwrt.git] / target / linux / ramips / patches-3.10 / 0122-pinmux.patch
1 From d59fe652e3674e98caa688b4ddc9308007267adc Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 19 Aug 2013 13:49:52 +0200
4 Subject: [PATCH] pinctrl: ralink; add pinctrl driver
5
6 Signed-off-by: John Crispin <blogic@openwrt.org>
7 ---
8 arch/mips/Kconfig | 2 +
9 arch/mips/ralink/common.h | 21 +--
10 arch/mips/ralink/dts/mt7620a.dtsi | 7 +
11 drivers/pinctrl/Kconfig | 5 +
12 drivers/pinctrl/Makefile | 1 +
13 drivers/pinctrl/pinctrl-rt2880.c | 368 +++++++++++++++++++++++++++++++++++++
14 6 files changed, 385 insertions(+), 19 deletions(-)
15 create mode 100644 drivers/pinctrl/pinctrl-rt2880.c
16
17 Index: linux-3.10.17/arch/mips/Kconfig
18 ===================================================================
19 --- linux-3.10.17.orig/arch/mips/Kconfig 2013-10-24 16:17:14.040072202 +0200
20 +++ linux-3.10.17/arch/mips/Kconfig 2013-10-24 16:17:14.964072221 +0200
21 @@ -446,6 +446,8 @@
22 select HAVE_MACH_CLKDEV
23 select CLKDEV_LOOKUP
24 select ARCH_REQUIRE_GPIOLIB
25 + select PINCTRL
26 + select PINCTRL_RT2880
27
28 config SGI_IP22
29 bool "SGI IP22 (Indy/Indigo2)"
30 Index: linux-3.10.17/drivers/pinctrl/Kconfig
31 ===================================================================
32 --- linux-3.10.17.orig/drivers/pinctrl/Kconfig 2013-10-18 19:44:19.000000000 +0200
33 +++ linux-3.10.17/drivers/pinctrl/Kconfig 2013-10-24 16:17:14.964072221 +0200
34 @@ -114,6 +114,11 @@
35 select PINMUX
36 select PINCONF
37
38 +config PINCTRL_RT2880
39 + bool
40 + depends on RALINK
41 + select PINMUX
42 +
43 config PINCTRL_FALCON
44 bool
45 depends on SOC_FALCON
46 Index: linux-3.10.17/drivers/pinctrl/Makefile
47 ===================================================================
48 --- linux-3.10.17.orig/drivers/pinctrl/Makefile 2013-10-18 19:44:19.000000000 +0200
49 +++ linux-3.10.17/drivers/pinctrl/Makefile 2013-10-24 16:17:14.964072221 +0200
50 @@ -45,6 +45,7 @@
51 obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
52 obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
53 obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
54 +obj-$(CONFIG_PINCTRL_RT2880) += pinctrl-rt2880.o
55
56 obj-$(CONFIG_PLAT_ORION) += mvebu/
57 obj-$(CONFIG_ARCH_SHMOBILE) += sh-pfc/
58 Index: linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c
59 ===================================================================
60 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
61 +++ linux-3.10.17/drivers/pinctrl/pinctrl-rt2880.c 2013-10-24 16:46:23.556113888 +0200
62 @@ -0,0 +1,463 @@
63 +/*
64 + * linux/drivers/pinctrl/pinctrl-rt2880.c
65 + *
66 + * This program is free software; you can redistribute it and/or modify
67 + * it under the terms of the GNU General Public License version 2 as
68 + * publishhed by the Free Software Foundation.
69 + *
70 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
71 + */
72 +
73 +#include <linux/module.h>
74 +#include <linux/device.h>
75 +#include <linux/io.h>
76 +#include <linux/platform_device.h>
77 +#include <linux/slab.h>
78 +#include <linux/of.h>
79 +#include <linux/pinctrl/pinctrl.h>
80 +#include <linux/pinctrl/pinconf.h>
81 +#include <linux/pinctrl/pinmux.h>
82 +#include <linux/pinctrl/consumer.h>
83 +#include <linux/pinctrl/machine.h>
84 +
85 +#include <asm/mach-ralink/ralink_regs.h>
86 +#include <asm/mach-ralink/pinmux.h>
87 +#include <asm/mach-ralink/mt7620.h>
88 +
89 +#include "core.h"
90 +
91 +#define SYSC_REG_GPIO_MODE 0x60
92 +
93 +struct rt2880_priv {
94 + struct device *dev;
95 +
96 + struct pinctrl_pin_desc *pads;
97 + struct pinctrl_desc *desc;
98 +
99 + struct rt2880_pmx_func **func;
100 + int func_count;
101 +
102 + struct rt2880_pmx_group *groups;
103 + const char **group_names;
104 + int group_count;
105 +
106 + uint8_t *gpio;
107 + int max_pins;
108 +};
109 +
110 +struct rt2880_pmx_group *rt2880_pinmux_data = NULL;
111 +
112 +static int rt2880_get_group_count(struct pinctrl_dev *pctrldev)
113 +{
114 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
115 +
116 + return p->group_count;
117 +}
118 +
119 +static const char *rt2880_get_group_name(struct pinctrl_dev *pctrldev,
120 + unsigned group)
121 +{
122 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
123 +
124 + if (group >= p->group_count)
125 + return NULL;
126 +
127 + return p->group_names[group];
128 +}
129 +
130 +static int rt2880_get_group_pins(struct pinctrl_dev *pctrldev,
131 + unsigned group,
132 + const unsigned **pins,
133 + unsigned *num_pins)
134 +{
135 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
136 +
137 + if (group >= p->group_count)
138 + return -EINVAL;
139 +
140 + *pins = p->groups[group].func[0].pins;
141 + *num_pins = p->groups[group].func[0].pin_count;
142 +
143 + return 0;
144 +}
145 +
146 +static void rt2880_pinctrl_dt_free_map(struct pinctrl_dev *pctrldev,
147 + struct pinctrl_map *map, unsigned num_maps)
148 +{
149 + int i;
150 +
151 + for (i = 0; i < num_maps; i++)
152 + if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN ||
153 + map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP)
154 + kfree(map[i].data.configs.configs);
155 + kfree(map);
156 +}
157 +
158 +static void rt2880_pinctrl_pin_dbg_show(struct pinctrl_dev *pctrldev,
159 + struct seq_file *s,
160 + unsigned offset)
161 +{
162 + seq_printf(s, "ralink pio");
163 +}
164 +
165 +static void rt2880_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctrldev,
166 + struct device_node *np,
167 + struct pinctrl_map **map)
168 +{
169 + const char *function;
170 + int func = of_property_read_string(np, "ralink,function", &function);
171 + int grps = of_property_count_strings(np, "ralink,group");
172 + int i;
173 +
174 + if (func || !grps)
175 + return;
176 +
177 + for (i = 0; i < grps; i++) {
178 + const char *group;
179 +
180 + of_property_read_string_index(np, "ralink,group", i, &group);
181 +
182 + (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
183 + (*map)->name = function;
184 + (*map)->data.mux.group = group;
185 + (*map)->data.mux.function = function;
186 + (*map)++;
187 + }
188 +}
189 +
190 +static int rt2880_pinctrl_dt_node_to_map(struct pinctrl_dev *pctrldev,
191 + struct device_node *np_config,
192 + struct pinctrl_map **map,
193 + unsigned *num_maps)
194 +{
195 + int max_maps = 0;
196 + struct pinctrl_map *tmp;
197 + struct device_node *np;
198 +
199 + for_each_child_of_node(np_config, np) {
200 + int ret = of_property_count_strings(np, "ralink,group");
201 +
202 + if (ret >= 0)
203 + max_maps += ret;
204 + }
205 +
206 + if (!max_maps)
207 + return max_maps;
208 +
209 + *map = kzalloc(max_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
210 + if (!*map)
211 + return -ENOMEM;
212 +
213 + tmp = *map;
214 +
215 + for_each_child_of_node(np_config, np)
216 + rt2880_pinctrl_dt_subnode_to_map(pctrldev, np, &tmp);
217 + *num_maps = max_maps;
218 +
219 + return 0;
220 +}
221 +
222 +static const struct pinctrl_ops rt2880_pctrl_ops = {
223 + .get_groups_count = rt2880_get_group_count,
224 + .get_group_name = rt2880_get_group_name,
225 + .get_group_pins = rt2880_get_group_pins,
226 + .pin_dbg_show = rt2880_pinctrl_pin_dbg_show,
227 + .dt_node_to_map = rt2880_pinctrl_dt_node_to_map,
228 + .dt_free_map = rt2880_pinctrl_dt_free_map,
229 +};
230 +
231 +static int rt2880_pmx_func_count(struct pinctrl_dev *pctrldev)
232 +{
233 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
234 +
235 + return p->func_count;
236 +}
237 +
238 +static const char *rt2880_pmx_func_name(struct pinctrl_dev *pctrldev,
239 + unsigned func)
240 +{
241 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
242 +
243 + return p->func[func]->name;
244 +}
245 +
246 +static int rt2880_pmx_group_get_groups(struct pinctrl_dev *pctrldev,
247 + unsigned func,
248 + const char * const **groups,
249 + unsigned * const num_groups)
250 +{
251 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
252 +
253 + if (p->func[func]->group_count == 1)
254 + *groups = &p->group_names[p->func[func]->groups[0]];
255 + else
256 + *groups = p->group_names;
257 +
258 + *num_groups = p->func[func]->group_count;
259 +
260 + return 0;
261 +}
262 +
263 +static int rt2880_pmx_group_enable(struct pinctrl_dev *pctrldev,
264 + unsigned func,
265 + unsigned group)
266 +{
267 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
268 + u32 mode = 0;
269 +
270 + /* dont allow double use */
271 + if (p->groups[group].enabled) {
272 + dev_err(p->dev, "%s is already enabled\n", p->groups[group].name);
273 + return -EBUSY;
274 + }
275 +
276 + p->groups[group].enabled = 1;
277 + p->func[func]->enabled = 1;
278 +
279 + mode = rt_sysc_r32(SYSC_REG_GPIO_MODE);
280 + mode &= ~(p->groups[group].mask << p->groups[group].shift);
281 +
282 + /* function 0 is gpio and needs special handling */
283 + if (func == 0) {
284 + int i;
285 +
286 + mode |= p->groups[group].mask << p->groups[group].shift;
287 + /* mark the pins as gpio */
288 + for (i = 0; i < p->groups[group].func[0].pin_count; i++)
289 + p->gpio[p->groups[group].func[0].pins[i]] = 1;
290 + } else {
291 + mode |= p->func[func]->value << p->groups[group].shift;
292 + }
293 + rt_sysc_w32(mode, SYSC_REG_GPIO_MODE);
294 +
295 + return 0;
296 +}
297 +
298 +static int rt2880_pmx_group_gpio_request_enable(struct pinctrl_dev *pctrldev,
299 + struct pinctrl_gpio_range *range,
300 + unsigned pin)
301 +{
302 + struct rt2880_priv *p = pinctrl_dev_get_drvdata(pctrldev);
303 +
304 + if (!p->gpio[pin]) {
305 + dev_err(p->dev, "pin %d is not set to gpio mux\n", pin);
306 + return -EINVAL;
307 + }
308 +
309 + return 0;
310 +}
311 +
312 +static const struct pinmux_ops rt2880_pmx_group_ops = {
313 + .get_functions_count = rt2880_pmx_func_count,
314 + .get_function_name = rt2880_pmx_func_name,
315 + .get_function_groups = rt2880_pmx_group_get_groups,
316 + .enable = rt2880_pmx_group_enable,
317 + .gpio_request_enable = rt2880_pmx_group_gpio_request_enable,
318 +};
319 +
320 +static struct pinctrl_desc rt2880_pctrl_desc = {
321 + .owner = THIS_MODULE,
322 + .name = "rt2880-pinmux",
323 + .pctlops = &rt2880_pctrl_ops,
324 + .pmxops = &rt2880_pmx_group_ops,
325 +};
326 +
327 +static struct rt2880_pmx_func gpio_func = {
328 + .name = "gpio",
329 +};
330 +
331 +static int rt2880_pinmux_index(struct rt2880_priv *p)
332 +{
333 + struct rt2880_pmx_func **f;
334 + struct rt2880_pmx_group *mux = p->groups;
335 + int i, j, c = 0;
336 +
337 + /* count the mux functions */
338 + while (mux->name) {
339 + p->group_count++;
340 + mux++;
341 + }
342 +
343 + /* allocate the group names array needed by the gpio function */
344 + p->group_names = devm_kzalloc(p->dev, sizeof(char *) * p->group_count, GFP_KERNEL);
345 + if (!p->group_names)
346 + return -1;
347 +
348 + for (i = 0; i < p->group_count; i++) {
349 + p->group_names[i] = p->groups[i].name;
350 + p->func_count += p->groups[i].func_count;
351 + }
352 +
353 + /* we have a dummy function[0] for gpio */
354 + p->func_count++;
355 +
356 + /* allocate our function and group mapping index buffers */
357 + f = p->func = devm_kzalloc(p->dev, sizeof(struct rt2880_pmx_func) * p->func_count, GFP_KERNEL);
358 + gpio_func.groups = devm_kzalloc(p->dev, sizeof(int) * p->group_count, GFP_KERNEL);
359 + if (!f || !gpio_func.groups)
360 + return -1;
361 +
362 + /* add a backpointer to the function so it knows its group */
363 + gpio_func.group_count = p->group_count;
364 + for (i = 0; i < gpio_func.group_count; i++)
365 + gpio_func.groups[i] = i;
366 +
367 + f[c] = &gpio_func;
368 + c++;
369 +
370 + /* add remaining functions */
371 + for (i = 0; i < p->group_count; i++) {
372 + for (j = 0; j < p->groups[i].func_count; j++) {
373 + f[c] = &p->groups[i].func[j];
374 + f[c]->groups = devm_kzalloc(p->dev, sizeof(int), GFP_KERNEL);
375 + f[c]->groups[0] = i;
376 + f[c]->group_count = 1;
377 + c++;
378 + }
379 + }
380 + return 0;
381 +}
382 +
383 +static int rt2880_pinmux_pins(struct rt2880_priv *p)
384 +{
385 + int i, j;
386 +
387 + /* loop over the functions and initialize the pins array. also work out the highest pin used */
388 + for (i = 0; i < p->func_count; i++) {
389 + int pin;
390 +
391 + if (!p->func[i]->pin_count)
392 + continue;
393 +
394 + p->func[i]->pins = devm_kzalloc(p->dev, sizeof(int) * p->func[i]->pin_count, GFP_KERNEL);
395 + for (j = 0; j < p->func[i]->pin_count; j++)
396 + p->func[i]->pins[j] = p->func[i]->pin_first + j;
397 +
398 + pin = p->func[i]->pin_first + p->func[i]->pin_count;
399 + if (pin > p->max_pins)
400 + p->max_pins = pin;
401 + }
402 +
403 + /* the buffer that tells us which pins are gpio */
404 + p->gpio = devm_kzalloc(p->dev,sizeof(uint8_t) * p->max_pins,
405 + GFP_KERNEL);
406 + /* the pads needed to tell pinctrl about our pins */
407 + p->pads = devm_kzalloc(p->dev,
408 + sizeof(struct pinctrl_pin_desc) * p->max_pins,
409 + GFP_KERNEL);
410 + if (!p->pads || !p->gpio ) {
411 + dev_err(p->dev, "Failed to allocate gpio data\n");
412 + return -ENOMEM;
413 + }
414 +
415 + memset(p->gpio, 1, sizeof(uint8_t) * p->max_pins);
416 + for (i = 0; i < p->func_count; i++) {
417 + if (!p->func[i]->pin_count)
418 + continue;
419 +
420 + for (j = 0; j < p->func[i]->pin_count; j++)
421 + p->gpio[p->func[i]->pins[j]] = 0;
422 + }
423 +
424 + /* pin 0 is always a gpio */
425 + p->gpio[0] = 1;
426 +
427 + /* set the pads */
428 + for (i = 0; i < p->max_pins; i++) {
429 + /* strlen("ioXY") + 1 = 5 */
430 + char *name = devm_kzalloc(p->dev, 5, GFP_KERNEL);
431 +
432 + if (!name) {
433 + dev_err(p->dev, "Failed to allocate pad name\n");
434 + return -ENOMEM;
435 + }
436 + snprintf(name, 5, "io%d", i);
437 + p->pads[i].number = i;
438 + p->pads[i].name = name;
439 + }
440 + p->desc->pins = p->pads;
441 + p->desc->npins = p->max_pins;
442 +
443 + return 0;
444 +}
445 +
446 +static int rt2880_pinmux_probe(struct platform_device *pdev)
447 +{
448 + struct rt2880_priv *p;
449 + struct pinctrl_dev *dev;
450 + struct device_node *np;
451 +
452 + if (!rt2880_pinmux_data)
453 + return -ENOSYS;
454 +
455 + /* setup the private data */
456 + p = devm_kzalloc(&pdev->dev, sizeof(struct rt2880_priv), GFP_KERNEL);
457 + if (!p)
458 + return -ENOMEM;
459 +
460 + p->dev = &pdev->dev;
461 + p->desc = &rt2880_pctrl_desc;
462 + p->groups = rt2880_pinmux_data;
463 + platform_set_drvdata(pdev, p);
464 +
465 + /* init the device */
466 + if (rt2880_pinmux_index(p)) {
467 + dev_err(&pdev->dev, "failed to load index\n");
468 + return -EINVAL;
469 + }
470 + if (rt2880_pinmux_pins(p)) {
471 + dev_err(&pdev->dev, "failed to load pins\n");
472 + return -EINVAL;
473 + }
474 + dev = pinctrl_register(p->desc, &pdev->dev, p);
475 + if (IS_ERR(dev))
476 + return PTR_ERR(dev);
477 +
478 + /* finalize by adding gpio ranges for enables gpio controllers */
479 + for_each_compatible_node(np, NULL, "ralink,rt2880-gpio") {
480 + const __be32 *ngpio, *gpiobase;
481 + struct pinctrl_gpio_range *range;
482 + char *name;
483 +
484 + if (!of_device_is_available(np))
485 + continue;
486 +
487 + ngpio = of_get_property(np, "ralink,num-gpios", NULL);
488 + gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
489 + if (!ngpio || !gpiobase) {
490 + dev_err(&pdev->dev, "failed to load chip info\n");
491 + return -EINVAL;
492 + }
493 +
494 + range = devm_kzalloc(p->dev, sizeof(struct pinctrl_gpio_range) + 4, GFP_KERNEL);
495 + range->name = name = (char *) &range[1];
496 + sprintf(name, "pio");
497 + range->npins = __be32_to_cpu(*ngpio);
498 + range->base = __be32_to_cpu(*gpiobase);
499 + pinctrl_add_gpio_range(dev, range);
500 + }
501 +
502 + return 0;
503 +}
504 +
505 +static const struct of_device_id rt2880_pinmux_match[] = {
506 + { .compatible = "ralink,rt2880-pinmux" },
507 + {},
508 +};
509 +MODULE_DEVICE_TABLE(of, rt2880_pinmux_match);
510 +
511 +static struct platform_driver rt2880_pinmux_driver = {
512 + .probe = rt2880_pinmux_probe,
513 + .driver = {
514 + .name = "rt2880-pinmux",
515 + .owner = THIS_MODULE,
516 + .of_match_table = rt2880_pinmux_match,
517 + },
518 +};
519 +
520 +int __init rt2880_pinmux_init(void)
521 +{
522 + return platform_driver_register(&rt2880_pinmux_driver);
523 +}
524 +
525 +core_initcall_sync(rt2880_pinmux_init);
526 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h
527 ===================================================================
528 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
529 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/pinmux.h 2013-10-24 16:17:14.968072221 +0200
530 @@ -0,0 +1,47 @@
531 +/*
532 + * This program is free software; you can redistribute it and/or modify
533 + * it under the terms of the GNU General Public License version 2 as
534 + * publishhed by the Free Software Foundation.
535 + *
536 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
537 + */
538 +
539 +#ifndef _RT288X_PINMUX_H__
540 +#define _RT288X_PINMUX_H__
541 +
542 +#define FUNC(name, value, pin_first, pin_count) { name, value, pin_first, pin_count }
543 +#define GRP(_name, _func, _mask, _shift) \
544 + { .name = _name, .mask = _mask, .shift = _shift, \
545 + .func = _func, \
546 + .func_count = ARRAY_SIZE(_func) }
547 +
548 +struct rt2880_pmx_group;
549 +
550 +struct rt2880_pmx_func {
551 + const char *name;
552 + const char value;
553 +
554 + int pin_first;
555 + int pin_count;
556 + int *pins;
557 +
558 + int *groups;
559 + int group_count;
560 +
561 + int enabled;
562 +};
563 +
564 +struct rt2880_pmx_group {
565 + const char *name;
566 + int enabled;
567 +
568 + const u32 shift;
569 + const char mask;
570 +
571 + struct rt2880_pmx_func *func;
572 + int func_count;
573 +};
574 +
575 +extern struct rt2880_pmx_group *rt2880_pinmux_data;
576 +
577 +#endif
578 Index: linux-3.10.17/arch/mips/ralink/mt7620.c
579 ===================================================================
580 --- linux-3.10.17.orig/arch/mips/ralink/mt7620.c 2013-10-24 16:17:14.428072211 +0200
581 +++ linux-3.10.17/arch/mips/ralink/mt7620.c 2013-10-24 16:17:14.968072221 +0200
582 @@ -17,6 +17,7 @@
583 #include <asm/mipsregs.h>
584 #include <asm/mach-ralink/ralink_regs.h>
585 #include <asm/mach-ralink/mt7620.h>
586 +#include <asm/mach-ralink/pinmux.h>
587
588 #include "common.h"
589
590 @@ -48,118 +49,40 @@
591 /* the pll dividers */
592 static u32 mt7620_clk_divider[] = { 2, 3, 4, 8 };
593
594 -static struct ralink_pinmux_grp mode_mux[] = {
595 - {
596 - .name = "i2c",
597 - .mask = MT7620_GPIO_MODE_I2C,
598 - .gpio_first = 1,
599 - .gpio_last = 2,
600 - }, {
601 - .name = "spi",
602 - .mask = MT7620_GPIO_MODE_SPI,
603 - .gpio_first = 3,
604 - .gpio_last = 6,
605 - }, {
606 - .name = "uartlite",
607 - .mask = MT7620_GPIO_MODE_UART1,
608 - .gpio_first = 15,
609 - .gpio_last = 16,
610 - }, {
611 - .name = "wdt",
612 - .mask = MT7620_GPIO_MODE_WDT,
613 - .gpio_first = 17,
614 - .gpio_last = 17,
615 - }, {
616 - .name = "mdio",
617 - .mask = MT7620_GPIO_MODE_MDIO,
618 - .gpio_first = 22,
619 - .gpio_last = 23,
620 - }, {
621 - .name = "rgmii1",
622 - .mask = MT7620_GPIO_MODE_RGMII1,
623 - .gpio_first = 24,
624 - .gpio_last = 35,
625 - }, {
626 - .name = "spi refclk",
627 - .mask = MT7620_GPIO_MODE_SPI_REF_CLK,
628 - .gpio_first = 37,
629 - .gpio_last = 39,
630 - }, {
631 - .name = "jtag",
632 - .mask = MT7620_GPIO_MODE_JTAG,
633 - .gpio_first = 40,
634 - .gpio_last = 44,
635 - }, {
636 - /* shared lines with jtag */
637 - .name = "ephy",
638 - .mask = MT7620_GPIO_MODE_EPHY,
639 - .gpio_first = 40,
640 - .gpio_last = 44,
641 - }, {
642 - .name = "nand",
643 - .mask = MT7620_GPIO_MODE_JTAG,
644 - .gpio_first = 45,
645 - .gpio_last = 59,
646 - }, {
647 - .name = "rgmii2",
648 - .mask = MT7620_GPIO_MODE_RGMII2,
649 - .gpio_first = 60,
650 - .gpio_last = 71,
651 - }, {
652 - .name = "wled",
653 - .mask = MT7620_GPIO_MODE_WLED,
654 - .gpio_first = 72,
655 - .gpio_last = 72,
656 - }, {0}
657 +static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 1, 2) };
658 +static struct rt2880_pmx_func spi_grp[] = { FUNC("spi", 0, 3, 4) };
659 +static struct rt2880_pmx_func uartf_grp[] = {
660 + FUNC("uartf", MT7620_GPIO_MODE_UARTF, 7, 8),
661 + FUNC("pcm uartf", MT7620_GPIO_MODE_PCM_UARTF, 7, 8),
662 + FUNC("pcm i2s", MT7620_GPIO_MODE_PCM_I2S, 7, 8),
663 + FUNC("i2s uartf", MT7620_GPIO_MODE_I2S_UARTF, 7, 8),
664 + FUNC("pcm gpio", MT7620_GPIO_MODE_PCM_GPIO, 11, 4),
665 + FUNC("gpio uartf", MT7620_GPIO_MODE_GPIO_UARTF, 7, 4),
666 + FUNC("gpio i2s", MT7620_GPIO_MODE_GPIO_I2S, 7, 4),
667 };
668 -
669 -static struct ralink_pinmux_grp uart_mux[] = {
670 - {
671 - .name = "uartf",
672 - .mask = MT7620_GPIO_MODE_UARTF,
673 - .gpio_first = 7,
674 - .gpio_last = 14,
675 - }, {
676 - .name = "pcm uartf",
677 - .mask = MT7620_GPIO_MODE_PCM_UARTF,
678 - .gpio_first = 7,
679 - .gpio_last = 14,
680 - }, {
681 - .name = "pcm i2s",
682 - .mask = MT7620_GPIO_MODE_PCM_I2S,
683 - .gpio_first = 7,
684 - .gpio_last = 14,
685 - }, {
686 - .name = "i2s uartf",
687 - .mask = MT7620_GPIO_MODE_I2S_UARTF,
688 - .gpio_first = 7,
689 - .gpio_last = 14,
690 - }, {
691 - .name = "pcm gpio",
692 - .mask = MT7620_GPIO_MODE_PCM_GPIO,
693 - .gpio_first = 11,
694 - .gpio_last = 14,
695 - }, {
696 - .name = "gpio uartf",
697 - .mask = MT7620_GPIO_MODE_GPIO_UARTF,
698 - .gpio_first = 7,
699 - .gpio_last = 10,
700 - }, {
701 - .name = "gpio i2s",
702 - .mask = MT7620_GPIO_MODE_GPIO_I2S,
703 - .gpio_first = 7,
704 - .gpio_last = 10,
705 - }, {
706 - .name = "gpio",
707 - .mask = MT7620_GPIO_MODE_GPIO,
708 - }, {0}
709 -};
710 -
711 -struct ralink_pinmux rt_gpio_pinmux = {
712 - .mode = mode_mux,
713 - .uart = uart_mux,
714 - .uart_shift = MT7620_GPIO_MODE_UART0_SHIFT,
715 - .uart_mask = MT7620_GPIO_MODE_UART0_MASK,
716 +static struct rt2880_pmx_func uartlite_grp[] = { FUNC("uartlite", 0, 15, 2) };
717 +static struct rt2880_pmx_func wdt_grp[] = { FUNC("wdt", 0, 17, 1) };
718 +static struct rt2880_pmx_func mdio_grp[] = { FUNC("mdio", 0, 22, 2) };
719 +static struct rt2880_pmx_func rgmii1_grp[] = { FUNC("rgmii1", 0, 24, 12) };
720 +static struct rt2880_pmx_func refclk_grp[] = { FUNC("spi refclk", 0, 37, 3) };
721 +static struct rt2880_pmx_func ephy_grp[] = { FUNC("ephy", 0, 40, 5) };
722 +static struct rt2880_pmx_func rgmii2_grp[] = { FUNC("rgmii2", 0, 60, 12) };
723 +static struct rt2880_pmx_func wled_grp[] = { FUNC("wled", 0, 72, 1) };
724 +
725 +static struct rt2880_pmx_group mt7620a_pinmux_data[] = {
726 + GRP("i2c", i2c_grp, 1, MT7620_GPIO_MODE_I2C),
727 + GRP("spi", spi_grp, 1, MT7620_GPIO_MODE_SPI),
728 + GRP("uartlite", uartlite_grp, 1, MT7620_GPIO_MODE_UART1),
729 + GRP("wdt", wdt_grp, 1, MT7620_GPIO_MODE_WDT),
730 + GRP("mdio", mdio_grp, 1, MT7620_GPIO_MODE_MDIO),
731 + GRP("rgmii1", rgmii1_grp, 1, MT7620_GPIO_MODE_RGMII1),
732 + GRP("spi refclk", refclk_grp, 1, MT7620_GPIO_MODE_SPI_REF_CLK),
733 + GRP("rgmii2", rgmii2_grp, 1, MT7620_GPIO_MODE_RGMII2),
734 + GRP("ephy", ephy_grp, 1, MT7620_GPIO_MODE_EPHY),
735 + GRP("wled", wled_grp, 1, MT7620_GPIO_MODE_WLED),
736 + GRP("uartf", uartf_grp, MT7620_GPIO_MODE_UART0_MASK,
737 + MT7620_GPIO_MODE_UART0_SHIFT),
738 + { 0 }
739 };
740
741 void __init ralink_clk_init(void)
742 @@ -281,4 +204,6 @@
743 (pmu0 & PMU_SW_SET) ? ("sw") : ("hw"));
744 pr_info("Digital PMU set to %s control\n",
745 (pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
746 +
747 + rt2880_pinmux_data = mt7620a_pinmux_data;
748 }
749 Index: linux-3.10.17/arch/mips/ralink/rt305x.c
750 ===================================================================
751 --- linux-3.10.17.orig/arch/mips/ralink/rt305x.c 2013-10-24 16:17:14.664072214 +0200
752 +++ linux-3.10.17/arch/mips/ralink/rt305x.c 2013-10-24 16:17:14.968072221 +0200
753 @@ -17,90 +17,71 @@
754 #include <asm/mipsregs.h>
755 #include <asm/mach-ralink/ralink_regs.h>
756 #include <asm/mach-ralink/rt305x.h>
757 +#include <asm/mach-ralink/pinmux.h>
758
759 #include "common.h"
760
761 enum rt305x_soc_type rt305x_soc;
762
763 -static struct ralink_pinmux_grp mode_mux[] = {
764 - {
765 - .name = "i2c",
766 - .mask = RT305X_GPIO_MODE_I2C,
767 - .gpio_first = RT305X_GPIO_I2C_SD,
768 - .gpio_last = RT305X_GPIO_I2C_SCLK,
769 - }, {
770 - .name = "spi",
771 - .mask = RT305X_GPIO_MODE_SPI,
772 - .gpio_first = RT305X_GPIO_SPI_EN,
773 - .gpio_last = RT305X_GPIO_SPI_CLK,
774 - }, {
775 - .name = "uartlite",
776 - .mask = RT305X_GPIO_MODE_UART1,
777 - .gpio_first = RT305X_GPIO_UART1_TXD,
778 - .gpio_last = RT305X_GPIO_UART1_RXD,
779 - }, {
780 - .name = "jtag",
781 - .mask = RT305X_GPIO_MODE_JTAG,
782 - .gpio_first = RT305X_GPIO_JTAG_TDO,
783 - .gpio_last = RT305X_GPIO_JTAG_TDI,
784 - }, {
785 - .name = "mdio",
786 - .mask = RT305X_GPIO_MODE_MDIO,
787 - .gpio_first = RT305X_GPIO_MDIO_MDC,
788 - .gpio_last = RT305X_GPIO_MDIO_MDIO,
789 - }, {
790 - .name = "sdram",
791 - .mask = RT305X_GPIO_MODE_SDRAM,
792 - .gpio_first = RT305X_GPIO_SDRAM_MD16,
793 - .gpio_last = RT305X_GPIO_SDRAM_MD31,
794 - }, {
795 - .name = "rgmii",
796 - .mask = RT305X_GPIO_MODE_RGMII,
797 - .gpio_first = RT305X_GPIO_GE0_TXD0,
798 - .gpio_last = RT305X_GPIO_GE0_RXCLK,
799 - }, {0}
800 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
801 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
802 +static struct rt2880_pmx_func uartf_func[] = {
803 + FUNC("uartf", RT305X_GPIO_MODE_UARTF, 7, 8),
804 + FUNC("pcm uartf", RT305X_GPIO_MODE_PCM_UARTF, 7, 8),
805 + FUNC("pcm i2s", RT305X_GPIO_MODE_PCM_I2S, 7, 8),
806 + FUNC("i2s uartf", RT305X_GPIO_MODE_I2S_UARTF, 7, 8),
807 + FUNC("pcm gpio", RT305X_GPIO_MODE_PCM_GPIO, 11, 4),
808 + FUNC("gpio uartf", RT305X_GPIO_MODE_GPIO_UARTF, 7, 4),
809 + FUNC("gpio i2s", RT305X_GPIO_MODE_GPIO_I2S, 7, 4),
810 +};
811 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
812 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
813 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
814 +static struct rt2880_pmx_func rt5350_led_func[] = { FUNC("led", 0, 22, 5) };
815 +static struct rt2880_pmx_func sdram_func[] = { FUNC("sdram", 0, 24, 16) };
816 +static struct rt2880_pmx_func rt3352_rgmii_func[] = { FUNC("rgmii", 0, 24, 12) };
817 +static struct rt2880_pmx_func rgmii_func[] = { FUNC("rgmii", 0, 40, 12) };
818 +static struct rt2880_pmx_func rt3352_lna_func[] = { FUNC("lna", 0, 36, 2) };
819 +static struct rt2880_pmx_func rt3352_pa_func[] = { FUNC("pa", 0, 38, 2) };
820 +static struct rt2880_pmx_func rt3352_led_func[] = { FUNC("led", 0, 40, 5) };
821 +
822 +static struct rt2880_pmx_group rt3050_pinmux_data[] = {
823 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
824 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
825 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
826 + RT305X_GPIO_MODE_UART0_SHIFT),
827 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
828 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
829 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
830 + GRP("rgmii", rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
831 + GRP("sdram", sdram_func, 1, RT305X_GPIO_MODE_SDRAM),
832 + { 0 }
833 +};
834 +
835 +static struct rt2880_pmx_group rt3352_pinmux_data[] = {
836 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
837 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
838 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
839 + RT305X_GPIO_MODE_UART0_SHIFT),
840 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
841 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
842 + GRP("mdio", mdio_func, 1, RT305X_GPIO_MODE_MDIO),
843 + GRP("rgmii", rt3352_rgmii_func, 1, RT305X_GPIO_MODE_RGMII),
844 + GRP("lna", rt3352_lna_func, 1, RT3352_GPIO_MODE_LNA),
845 + GRP("pa", rt3352_pa_func, 1, RT3352_GPIO_MODE_PA),
846 + GRP("led", rt3352_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
847 + { 0 }
848 };
849
850 -static struct ralink_pinmux_grp uart_mux[] = {
851 - {
852 - .name = "uartf",
853 - .mask = RT305X_GPIO_MODE_UARTF,
854 - .gpio_first = RT305X_GPIO_7,
855 - .gpio_last = RT305X_GPIO_14,
856 - }, {
857 - .name = "pcm uartf",
858 - .mask = RT305X_GPIO_MODE_PCM_UARTF,
859 - .gpio_first = RT305X_GPIO_7,
860 - .gpio_last = RT305X_GPIO_14,
861 - }, {
862 - .name = "pcm i2s",
863 - .mask = RT305X_GPIO_MODE_PCM_I2S,
864 - .gpio_first = RT305X_GPIO_7,
865 - .gpio_last = RT305X_GPIO_14,
866 - }, {
867 - .name = "i2s uartf",
868 - .mask = RT305X_GPIO_MODE_I2S_UARTF,
869 - .gpio_first = RT305X_GPIO_7,
870 - .gpio_last = RT305X_GPIO_14,
871 - }, {
872 - .name = "pcm gpio",
873 - .mask = RT305X_GPIO_MODE_PCM_GPIO,
874 - .gpio_first = RT305X_GPIO_10,
875 - .gpio_last = RT305X_GPIO_14,
876 - }, {
877 - .name = "gpio uartf",
878 - .mask = RT305X_GPIO_MODE_GPIO_UARTF,
879 - .gpio_first = RT305X_GPIO_7,
880 - .gpio_last = RT305X_GPIO_10,
881 - }, {
882 - .name = "gpio i2s",
883 - .mask = RT305X_GPIO_MODE_GPIO_I2S,
884 - .gpio_first = RT305X_GPIO_7,
885 - .gpio_last = RT305X_GPIO_10,
886 - }, {
887 - .name = "gpio",
888 - .mask = RT305X_GPIO_MODE_GPIO,
889 - }, {0}
890 +static struct rt2880_pmx_group rt5350_pinmux_data[] = {
891 + GRP("i2c", i2c_func, 1, RT305X_GPIO_MODE_I2C),
892 + GRP("spi", spi_func, 1, RT305X_GPIO_MODE_SPI),
893 + GRP("uartf", uartf_func, RT305X_GPIO_MODE_UART0_MASK,
894 + RT305X_GPIO_MODE_UART0_SHIFT),
895 + GRP("uartlite", uartlite_func, 1, RT305X_GPIO_MODE_UART1),
896 + GRP("jtag", jtag_func, 1, RT305X_GPIO_MODE_JTAG),
897 + GRP("led", rt5350_led_func, 1, RT5350_GPIO_MODE_PHY_LED),
898 + { 0 }
899 };
900
901 static void rt305x_wdt_reset(void)
902 @@ -114,14 +95,6 @@
903 rt_sysc_w32(t, SYSC_REG_SYSTEM_CONFIG);
904 }
905
906 -struct ralink_pinmux rt_gpio_pinmux = {
907 - .mode = mode_mux,
908 - .uart = uart_mux,
909 - .uart_shift = RT305X_GPIO_MODE_UART0_SHIFT,
910 - .uart_mask = RT305X_GPIO_MODE_UART0_MASK,
911 - .wdt_reset = rt305x_wdt_reset,
912 -};
913 -
914 static unsigned long rt5350_get_mem_size(void)
915 {
916 void __iomem *sysc = (void __iomem *) KSEG1ADDR(RT305X_SYSC_BASE);
917 @@ -291,11 +264,14 @@
918 soc_info->mem_base = RT305X_SDRAM_BASE;
919 if (soc_is_rt5350()) {
920 soc_info->mem_size = rt5350_get_mem_size();
921 + rt2880_pinmux_data = rt5350_pinmux_data;
922 } else if (soc_is_rt305x() || soc_is_rt3350()) {
923 soc_info->mem_size_min = RT305X_MEM_SIZE_MIN;
924 soc_info->mem_size_max = RT305X_MEM_SIZE_MAX;
925 + rt2880_pinmux_data = rt3050_pinmux_data;
926 } else if (soc_is_rt3352()) {
927 soc_info->mem_size_min = RT3352_MEM_SIZE_MIN;
928 soc_info->mem_size_max = RT3352_MEM_SIZE_MAX;
929 + rt2880_pinmux_data = rt3352_pinmux_data;
930 }
931 }
932 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h
933 ===================================================================
934 --- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-18 19:44:19.000000000 +0200
935 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt305x.h 2013-10-24 16:17:14.968072221 +0200
936 @@ -125,24 +125,28 @@
937 #define RT305X_GPIO_GE0_TXD0 40
938 #define RT305X_GPIO_GE0_RXCLK 51
939
940 -#define RT305X_GPIO_MODE_I2C BIT(0)
941 -#define RT305X_GPIO_MODE_SPI BIT(1)
942 #define RT305X_GPIO_MODE_UART0_SHIFT 2
943 #define RT305X_GPIO_MODE_UART0_MASK 0x7
944 #define RT305X_GPIO_MODE_UART0(x) ((x) << RT305X_GPIO_MODE_UART0_SHIFT)
945 -#define RT305X_GPIO_MODE_UARTF 0x0
946 -#define RT305X_GPIO_MODE_PCM_UARTF 0x1
947 -#define RT305X_GPIO_MODE_PCM_I2S 0x2
948 -#define RT305X_GPIO_MODE_I2S_UARTF 0x3
949 -#define RT305X_GPIO_MODE_PCM_GPIO 0x4
950 -#define RT305X_GPIO_MODE_GPIO_UARTF 0x5
951 -#define RT305X_GPIO_MODE_GPIO_I2S 0x6
952 -#define RT305X_GPIO_MODE_GPIO 0x7
953 -#define RT305X_GPIO_MODE_UART1 BIT(5)
954 -#define RT305X_GPIO_MODE_JTAG BIT(6)
955 -#define RT305X_GPIO_MODE_MDIO BIT(7)
956 -#define RT305X_GPIO_MODE_SDRAM BIT(8)
957 -#define RT305X_GPIO_MODE_RGMII BIT(9)
958 +#define RT305X_GPIO_MODE_UARTF 0
959 +#define RT305X_GPIO_MODE_PCM_UARTF 1
960 +#define RT305X_GPIO_MODE_PCM_I2S 2
961 +#define RT305X_GPIO_MODE_I2S_UARTF 3
962 +#define RT305X_GPIO_MODE_PCM_GPIO 4
963 +#define RT305X_GPIO_MODE_GPIO_UARTF 5
964 +#define RT305X_GPIO_MODE_GPIO_I2S 6
965 +#define RT305X_GPIO_MODE_GPIO 7
966 +
967 +#define RT305X_GPIO_MODE_I2C 0
968 +#define RT305X_GPIO_MODE_SPI 1
969 +#define RT305X_GPIO_MODE_UART1 5
970 +#define RT305X_GPIO_MODE_JTAG 6
971 +#define RT305X_GPIO_MODE_MDIO 7
972 +#define RT305X_GPIO_MODE_SDRAM 8
973 +#define RT305X_GPIO_MODE_RGMII 9
974 +#define RT5350_GPIO_MODE_PHY_LED 14
975 +#define RT3352_GPIO_MODE_LNA 18
976 +#define RT3352_GPIO_MODE_PA 20
977
978 #define RT3352_SYSC_REG_SYSCFG0 0x010
979 #define RT3352_SYSC_REG_SYSCFG1 0x014
980 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h
981 ===================================================================
982 --- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-24 16:17:14.220072209 +0200
983 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/mt7620.h 2013-10-24 16:17:14.968072221 +0200
984 @@ -59,7 +59,6 @@
985 #define MT7620_DDR2_SIZE_MIN 32
986 #define MT7620_DDR2_SIZE_MAX 256
987
988 -#define MT7620_GPIO_MODE_I2C BIT(0)
989 #define MT7620_GPIO_MODE_UART0_SHIFT 2
990 #define MT7620_GPIO_MODE_UART0_MASK 0x7
991 #define MT7620_GPIO_MODE_UART0(x) ((x) << MT7620_GPIO_MODE_UART0_SHIFT)
992 @@ -71,15 +70,17 @@
993 #define MT7620_GPIO_MODE_GPIO_UARTF 0x5
994 #define MT7620_GPIO_MODE_GPIO_I2S 0x6
995 #define MT7620_GPIO_MODE_GPIO 0x7
996 -#define MT7620_GPIO_MODE_UART1 BIT(5)
997 -#define MT7620_GPIO_MODE_MDIO BIT(8)
998 -#define MT7620_GPIO_MODE_RGMII1 BIT(9)
999 -#define MT7620_GPIO_MODE_RGMII2 BIT(10)
1000 -#define MT7620_GPIO_MODE_SPI BIT(11)
1001 -#define MT7620_GPIO_MODE_SPI_REF_CLK BIT(12)
1002 -#define MT7620_GPIO_MODE_WLED BIT(13)
1003 -#define MT7620_GPIO_MODE_JTAG BIT(15)
1004 -#define MT7620_GPIO_MODE_EPHY BIT(15)
1005 -#define MT7620_GPIO_MODE_WDT BIT(22)
1006 +
1007 +#define MT7620_GPIO_MODE_I2C 0
1008 +#define MT7620_GPIO_MODE_UART1 5
1009 +#define MT7620_GPIO_MODE_MDIO 8
1010 +#define MT7620_GPIO_MODE_RGMII1 9
1011 +#define MT7620_GPIO_MODE_RGMII2 10
1012 +#define MT7620_GPIO_MODE_SPI 11
1013 +#define MT7620_GPIO_MODE_SPI_REF_CLK 12
1014 +#define MT7620_GPIO_MODE_WLED 13
1015 +#define MT7620_GPIO_MODE_JTAG 15
1016 +#define MT7620_GPIO_MODE_EPHY 15
1017 +#define MT7620_GPIO_MODE_WDT 22
1018
1019 #endif
1020 Index: linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h
1021 ===================================================================
1022 --- linux-3.10.17.orig/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-18 19:44:19.000000000 +0200
1023 +++ linux-3.10.17/arch/mips/include/asm/mach-ralink/rt3883.h 2013-10-24 16:17:14.968072221 +0200
1024 @@ -112,8 +112,6 @@
1025 #define RT3883_CLKCFG1_PCI_CLK_EN BIT(19)
1026 #define RT3883_CLKCFG1_UPHY0_CLK_EN BIT(18)
1027
1028 -#define RT3883_GPIO_MODE_I2C BIT(0)
1029 -#define RT3883_GPIO_MODE_SPI BIT(1)
1030 #define RT3883_GPIO_MODE_UART0_SHIFT 2
1031 #define RT3883_GPIO_MODE_UART0_MASK 0x7
1032 #define RT3883_GPIO_MODE_UART0(x) ((x) << RT3883_GPIO_MODE_UART0_SHIFT)
1033 @@ -125,11 +123,15 @@
1034 #define RT3883_GPIO_MODE_GPIO_UARTF 0x5
1035 #define RT3883_GPIO_MODE_GPIO_I2S 0x6
1036 #define RT3883_GPIO_MODE_GPIO 0x7
1037 -#define RT3883_GPIO_MODE_UART1 BIT(5)
1038 -#define RT3883_GPIO_MODE_JTAG BIT(6)
1039 -#define RT3883_GPIO_MODE_MDIO BIT(7)
1040 -#define RT3883_GPIO_MODE_GE1 BIT(9)
1041 -#define RT3883_GPIO_MODE_GE2 BIT(10)
1042 +
1043 +#define RT3883_GPIO_MODE_I2C 0
1044 +#define RT3883_GPIO_MODE_SPI 1
1045 +#define RT3883_GPIO_MODE_UART1 5
1046 +#define RT3883_GPIO_MODE_JTAG 6
1047 +#define RT3883_GPIO_MODE_MDIO 7
1048 +#define RT3883_GPIO_MODE_GE1 9
1049 +#define RT3883_GPIO_MODE_GE2 10
1050 +
1051 #define RT3883_GPIO_MODE_PCI_SHIFT 11
1052 #define RT3883_GPIO_MODE_PCI_MASK 0x7
1053 #define RT3883_GPIO_MODE_PCI (RT3883_GPIO_MODE_PCI_MASK << RT3883_GPIO_MODE_PCI_SHIFT)
1054 Index: linux-3.10.17/arch/mips/ralink/common.h
1055 ===================================================================
1056 --- linux-3.10.17.orig/arch/mips/ralink/common.h 2013-10-24 16:17:14.040072202 +0200
1057 +++ linux-3.10.17/arch/mips/ralink/common.h 2013-10-24 16:17:14.968072221 +0200
1058 @@ -11,25 +11,6 @@
1059
1060 #define RAMIPS_SYS_TYPE_LEN 32
1061
1062 -struct ralink_pinmux_grp {
1063 - const char *name;
1064 - u32 mask;
1065 - int gpio_first;
1066 - int gpio_last;
1067 -};
1068 -
1069 -struct ralink_pinmux {
1070 - struct ralink_pinmux_grp *mode;
1071 - struct ralink_pinmux_grp *uart;
1072 - int uart_shift;
1073 - u32 uart_mask;
1074 - void (*wdt_reset)(void);
1075 - struct ralink_pinmux_grp *pci;
1076 - int pci_shift;
1077 - u32 pci_mask;
1078 -};
1079 -extern struct ralink_pinmux rt_gpio_pinmux;
1080 -
1081 struct ralink_soc_info {
1082 unsigned char sys_type[RAMIPS_SYS_TYPE_LEN];
1083 unsigned char *compatible;
1084 Index: linux-3.10.17/arch/mips/ralink/rt3883.c
1085 ===================================================================
1086 --- linux-3.10.17.orig/arch/mips/ralink/rt3883.c 2013-10-18 19:44:19.000000000 +0200
1087 +++ linux-3.10.17/arch/mips/ralink/rt3883.c 2013-10-24 16:17:14.972072223 +0200
1088 @@ -17,132 +17,50 @@
1089 #include <asm/mipsregs.h>
1090 #include <asm/mach-ralink/ralink_regs.h>
1091 #include <asm/mach-ralink/rt3883.h>
1092 +#include <asm/mach-ralink/pinmux.h>
1093
1094 #include "common.h"
1095
1096 -static struct ralink_pinmux_grp mode_mux[] = {
1097 - {
1098 - .name = "i2c",
1099 - .mask = RT3883_GPIO_MODE_I2C,
1100 - .gpio_first = RT3883_GPIO_I2C_SD,
1101 - .gpio_last = RT3883_GPIO_I2C_SCLK,
1102 - }, {
1103 - .name = "spi",
1104 - .mask = RT3883_GPIO_MODE_SPI,
1105 - .gpio_first = RT3883_GPIO_SPI_CS0,
1106 - .gpio_last = RT3883_GPIO_SPI_MISO,
1107 - }, {
1108 - .name = "uartlite",
1109 - .mask = RT3883_GPIO_MODE_UART1,
1110 - .gpio_first = RT3883_GPIO_UART1_TXD,
1111 - .gpio_last = RT3883_GPIO_UART1_RXD,
1112 - }, {
1113 - .name = "jtag",
1114 - .mask = RT3883_GPIO_MODE_JTAG,
1115 - .gpio_first = RT3883_GPIO_JTAG_TDO,
1116 - .gpio_last = RT3883_GPIO_JTAG_TCLK,
1117 - }, {
1118 - .name = "mdio",
1119 - .mask = RT3883_GPIO_MODE_MDIO,
1120 - .gpio_first = RT3883_GPIO_MDIO_MDC,
1121 - .gpio_last = RT3883_GPIO_MDIO_MDIO,
1122 - }, {
1123 - .name = "ge1",
1124 - .mask = RT3883_GPIO_MODE_GE1,
1125 - .gpio_first = RT3883_GPIO_GE1_TXD0,
1126 - .gpio_last = RT3883_GPIO_GE1_RXCLK,
1127 - }, {
1128 - .name = "ge2",
1129 - .mask = RT3883_GPIO_MODE_GE2,
1130 - .gpio_first = RT3883_GPIO_GE2_TXD0,
1131 - .gpio_last = RT3883_GPIO_GE2_RXCLK,
1132 - }, {
1133 - .name = "pci",
1134 - .mask = RT3883_GPIO_MODE_PCI,
1135 - .gpio_first = RT3883_GPIO_PCI_AD0,
1136 - .gpio_last = RT3883_GPIO_PCI_AD31,
1137 - }, {
1138 - .name = "lna a",
1139 - .mask = RT3883_GPIO_MODE_LNA_A,
1140 - .gpio_first = RT3883_GPIO_LNA_PE_A0,
1141 - .gpio_last = RT3883_GPIO_LNA_PE_A2,
1142 - }, {
1143 - .name = "lna g",
1144 - .mask = RT3883_GPIO_MODE_LNA_G,
1145 - .gpio_first = RT3883_GPIO_LNA_PE_G0,
1146 - .gpio_last = RT3883_GPIO_LNA_PE_G2,
1147 - }, {0}
1148 +static struct rt2880_pmx_func i2c_func[] = { FUNC("i2c", 0, 1, 2) };
1149 +static struct rt2880_pmx_func spi_func[] = { FUNC("spi", 0, 3, 4) };
1150 +static struct rt2880_pmx_func uartf_func[] = {
1151 + FUNC("uartf", RT3883_GPIO_MODE_UARTF, 7, 8),
1152 + FUNC("pcm uartf", RT3883_GPIO_MODE_PCM_UARTF, 7, 8),
1153 + FUNC("pcm i2s", RT3883_GPIO_MODE_PCM_I2S, 7, 8),
1154 + FUNC("i2s uartf", RT3883_GPIO_MODE_I2S_UARTF, 7, 8),
1155 + FUNC("pcm gpio", RT3883_GPIO_MODE_PCM_GPIO, 11, 4),
1156 + FUNC("gpio uartf", RT3883_GPIO_MODE_GPIO_UARTF, 7, 4),
1157 + FUNC("gpio i2s", RT3883_GPIO_MODE_GPIO_I2S, 7, 4),
1158 };
1159 -
1160 -static struct ralink_pinmux_grp uart_mux[] = {
1161 - {
1162 - .name = "uartf",
1163 - .mask = RT3883_GPIO_MODE_UARTF,
1164 - .gpio_first = RT3883_GPIO_7,
1165 - .gpio_last = RT3883_GPIO_14,
1166 - }, {
1167 - .name = "pcm uartf",
1168 - .mask = RT3883_GPIO_MODE_PCM_UARTF,
1169 - .gpio_first = RT3883_GPIO_7,
1170 - .gpio_last = RT3883_GPIO_14,
1171 - }, {
1172 - .name = "pcm i2s",
1173 - .mask = RT3883_GPIO_MODE_PCM_I2S,
1174 - .gpio_first = RT3883_GPIO_7,
1175 - .gpio_last = RT3883_GPIO_14,
1176 - }, {
1177 - .name = "i2s uartf",
1178 - .mask = RT3883_GPIO_MODE_I2S_UARTF,
1179 - .gpio_first = RT3883_GPIO_7,
1180 - .gpio_last = RT3883_GPIO_14,
1181 - }, {
1182 - .name = "pcm gpio",
1183 - .mask = RT3883_GPIO_MODE_PCM_GPIO,
1184 - .gpio_first = RT3883_GPIO_11,
1185 - .gpio_last = RT3883_GPIO_14,
1186 - }, {
1187 - .name = "gpio uartf",
1188 - .mask = RT3883_GPIO_MODE_GPIO_UARTF,
1189 - .gpio_first = RT3883_GPIO_7,
1190 - .gpio_last = RT3883_GPIO_10,
1191 - }, {
1192 - .name = "gpio i2s",
1193 - .mask = RT3883_GPIO_MODE_GPIO_I2S,
1194 - .gpio_first = RT3883_GPIO_7,
1195 - .gpio_last = RT3883_GPIO_10,
1196 - }, {
1197 - .name = "gpio",
1198 - .mask = RT3883_GPIO_MODE_GPIO,
1199 - }, {0}
1200 +static struct rt2880_pmx_func uartlite_func[] = { FUNC("uartlite", 0, 15, 2) };
1201 +static struct rt2880_pmx_func jtag_func[] = { FUNC("jtag", 0, 17, 25) };
1202 +static struct rt2880_pmx_func mdio_func[] = { FUNC("mdio", 0, 22, 2) };
1203 +static struct rt2880_pmx_func lna_a_func[] = { FUNC("lna a", 0, 32, 3) };
1204 +static struct rt2880_pmx_func lna_g_func[] = { FUNC("lna a", 0, 35, 3) };
1205 +static struct rt2880_pmx_func pci_func[] = {
1206 + FUNC("pci-dev", 0, 40, 32),
1207 + FUNC("pci-host2", 1, 40, 32),
1208 + FUNC("pci-host1", 2, 40, 32),
1209 + FUNC("pci-fnc", 3, 40, 32)
1210 };
1211 +static struct rt2880_pmx_func ge1_func[] = { FUNC("ge1", 0, 72, 12) };
1212 +static struct rt2880_pmx_func ge2_func[] = { FUNC("ge1", 0, 84, 12) };
1213
1214 -static struct ralink_pinmux_grp pci_mux[] = {
1215 - {
1216 - .name = "pci-dev",
1217 - .mask = 0,
1218 - .gpio_first = RT3883_GPIO_PCI_AD0,
1219 - .gpio_last = RT3883_GPIO_PCI_AD31,
1220 - }, {
1221 - .name = "pci-host2",
1222 - .mask = 1,
1223 - .gpio_first = RT3883_GPIO_PCI_AD0,
1224 - .gpio_last = RT3883_GPIO_PCI_AD31,
1225 - }, {
1226 - .name = "pci-host1",
1227 - .mask = 2,
1228 - .gpio_first = RT3883_GPIO_PCI_AD0,
1229 - .gpio_last = RT3883_GPIO_PCI_AD31,
1230 - }, {
1231 - .name = "pci-fnc",
1232 - .mask = 3,
1233 - .gpio_first = RT3883_GPIO_PCI_AD0,
1234 - .gpio_last = RT3883_GPIO_PCI_AD31,
1235 - }, {
1236 - .name = "pci-gpio",
1237 - .mask = 7,
1238 - .gpio_first = RT3883_GPIO_PCI_AD0,
1239 - .gpio_last = RT3883_GPIO_PCI_AD31,
1240 - }, {0}
1241 +static struct rt2880_pmx_group rt3883_pinmux_data[] = {
1242 + GRP("i2c", i2c_func, 1, RT3883_GPIO_MODE_I2C),
1243 + GRP("spi", spi_func, 1, RT3883_GPIO_MODE_SPI),
1244 + GRP("uartf", uartf_func, RT3883_GPIO_MODE_UART0_MASK,
1245 + RT3883_GPIO_MODE_UART0_SHIFT),
1246 + GRP("uartlite", uartlite_func, 1, RT3883_GPIO_MODE_UART1),
1247 + GRP("jtag", jtag_func, 1, RT3883_GPIO_MODE_JTAG),
1248 + GRP("mdio", mdio_func, 1, RT3883_GPIO_MODE_MDIO),
1249 + GRP("lna a", lna_a_func, 1, RT3883_GPIO_MODE_LNA_A),
1250 + GRP("lna g", lna_g_func, 1, RT3883_GPIO_MODE_LNA_G),
1251 + GRP("pci", pci_func, RT3883_GPIO_MODE_PCI_MASK,
1252 + RT3883_GPIO_MODE_PCI_SHIFT),
1253 + GRP("ge1", ge1_func, 1, RT3883_GPIO_MODE_GE1),
1254 + GRP("ge2", ge2_func, 1, RT3883_GPIO_MODE_GE2),
1255 + { 0 }
1256 };
1257
1258 static void rt3883_wdt_reset(void)
1259 @@ -155,17 +73,6 @@
1260 rt_sysc_w32(t, RT3883_SYSC_REG_SYSCFG1);
1261 }
1262
1263 -struct ralink_pinmux rt_gpio_pinmux = {
1264 - .mode = mode_mux,
1265 - .uart = uart_mux,
1266 - .uart_shift = RT3883_GPIO_MODE_UART0_SHIFT,
1267 - .uart_mask = RT3883_GPIO_MODE_UART0_MASK,
1268 - .wdt_reset = rt3883_wdt_reset,
1269 - .pci = pci_mux,
1270 - .pci_shift = RT3883_GPIO_MODE_PCI_SHIFT,
1271 - .pci_mask = RT3883_GPIO_MODE_PCI_MASK,
1272 -};
1273 -
1274 void __init ralink_clk_init(void)
1275 {
1276 unsigned long cpu_rate, sys_rate;
1277 @@ -243,4 +150,6 @@
1278 soc_info->mem_base = RT3883_SDRAM_BASE;
1279 soc_info->mem_size_min = RT3883_MEM_SIZE_MIN;
1280 soc_info->mem_size_max = RT3883_MEM_SIZE_MAX;
1281 +
1282 + rt2880_pinmux_data = rt3883_pinmux_data;
1283 }
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